THCV233-THCV234_Rev.3.10_E
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THCV233 and THCV234
V-by-One®HS High-speed video data transmitter and receiver
1. General Description
THCV233 and THCV234 are V-by-One® HS High-speed
digital data transmitter/receiver.
It has one high-speed data lane and, effective maximum
serial data rate is 2.72Gbps/lane.
2. Features
LVDS Input internal termination
CORE 1.8V, LVDS 3.3V
Package: 48 pin QFN
EU RoHS Compliant
Data width selectable: 24/32 bit
Single/Dual Link selectable
AC coupling
Wide frequency range
CDR requires no external freq. reference
Supports Spread Spectrum Clocking:
Up to 30kHz/0.5%(center spread)
Si/So:Single-in/Single-out, Si/Do:Single-in/Dual-out
Si/DDo:Single-in/Distributed Dual-out
Di/So:Dual-in/Single-out, Di/SSo:Dual-in/Selected Single-out
Table 1
3.Block Diagram
Figure 1
Product TMP VDL Width Link LVDS Clock Freq.
Si/So 9MHz to 100MHz
Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 85MHz
Si/DDo 20MHz to 85MHz
Si/Do 40MHz to 85MHz
Si/So 9MHz to 100MHz
Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 75MHz
Si/DDo 20MHz to 75MHz
Si/Do 40MHz to 75MHz
Si/So 9MHz to 100MHz
Si/DDo 20MHz to 100MHz
Si/Do 40MHz to 100MHz
Si/So 9MHz to 81MHz
Si/DDo 20MHz to 81MHz
Si/Do 40MHz to 81MHz
Si/So 9MHz to 100MHz
Di/SSo 20MHz to 100MHz
Di/So 40MHz to 100MHz
Si/So 9MHz to 85MHz
Di/SSo 20MHz to 85MHz
Di/So 40MHz to 85MHz
Si/So 9MHz to 95MHz
Di/SSo 20MHz to 95MHz
Di/So 40MHz to 95MHz
Si/So 9MHz to 71.25MHz
Di/SSo 20MHz to 71.25MHz
Di/So 40MHz to 71.25MHz
THCV234
0°C~
70°C
1.62V~
1.98V
24bit
32bit
-40°C~
105°C
1.7V~
1.98V
24bit
32bit
THCV233
0°C~
70°C
1.62V~
1.98V
24bit
32bit
-40°C~
105°C
24bit
32bit
1.7V~
1.98V
24bit
32bit
THCV233-THCV234_Rev.3.10_E
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Contents Page
1. General Description ............................................................................................................................................. 1
2. Features ................................................................................................................................................................ 1
3.Block Diagram ...................................................................................................................................................... 1
4. Pin Configuration ................................................................................................................................................ 4
5. Pin Description ..................................................................................................................................................... 5
6. Operation Mode ................................................................................................................................................... 7
7. Function Description ........................................................................................................................................... 8
Functional Overview ............................................................................................................................................. 8
DE signal (TLC[6] / DEIN) Input Requirement .................................................................................................... 9
Data Enable input of THCV233 (DEIN) ............................................................................................................. 10
Data Enable output of THCV234 (DEOUT) ....................................................................................................... 10
Data Enable Select of THCV233 ......................................................................................................................... 10
Color depth or data width setting function (COL) ................................................................................................11
Operation mode function of THCV233 (MODE[1:0]) .........................................................................................11
Operation mode function of THCV234 (MODE[1:0]) .........................................................................................11
Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK) .......................................................... 12
LVDS Mapping .................................................................................................................................................... 13
THCV234 LVDS Reduced swing output function (RS) ...................................................................................... 15
CML Buffer ......................................................................................................................................................... 16
Lock detect and Hot-plug function ...................................................................................................................... 17
No HTPDN connection option ............................................................................................................................ 17
THCV233 Pre-emphasis function (PRE) ............................................................................................................. 18
Field BET Operation ............................................................................................................................................ 18
8. Absolute Maximum Ratings .............................................................................................................................. 19
9. Operating Conditions ........................................................................................................................................ 20
10. Electrical Specifications .................................................................................................................................. 21
DC Specifications ................................................................................................................................................ 21
Supply Currents ................................................................................................................................................... 22
Switching Characteristics .................................................................................................................................... 23
11. AC Timing Diagrams and Test Circuits ......................................................................................................... 26
LVDS Input Switching Characteristics ................................................................................................................ 26
LVDS Output Switching Characteristics ............................................................................................................. 27
CML Output Switching Characteristics ............................................................................................................... 28
Latency Characteristics ........................................................................................................................................ 29
Lock and Unlock Sequence ................................................................................................................................. 30
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Package ................................................................................................................................................................... 33
Notices and Requests ............................................................................................................................................. 34
THCV233-THCV234_Rev.3.10_E
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4. Pin Configuration
THCV233 THCV234
Figure 2
LAVDH
LAGND
Reserved[8]
Reserved[7]
MODE [1]
MODE [0]
VDD
PRE
Reserved[6]
BET
Reserved[5]
PDN
36 35 34 33 32 31 30 29 28 27 26 25
TLA- 37 24 HTPDN
TLA+ 38 23 LOCKN
TLB- 39 22 CAVDL
TLB+ 40 21 CAGND
TLC- 41 20 TX0N
TLC+ 42 19 TX0P
TLCLK- 43 18 CAGND
TLCLK+ 44 17 TX1N
TLD- 45 16 TX1P
TLD+ 46 15 CAGND
TLE- 47 14 CAVDL
TLE+ 48 13 CPVDL
12345678910 11 12
LAVDH
LAGND
COL
DEIN
Reserved[0]
VSS
VDD
Reserved[1]
DESEL
Reserved[2]
Reserved[3]
Reserved[4]
THCV233
QFN-48pin
Exposed PAD
(TOP VIEW)
49 EXPGND
DGLOCK
PDN
Reserved[9]
Reserved[8]
RS
VDD
MODE[0]
MODE[1]
Reserved[7]
Reserved[6]
LAGND
LAVDH
36 35 34 33 32 31 30 29 28 27 26 25
HTPDN 37 24 RLA-
LOCKN 38 23 RLA+
CAGND 39 22 RLB-
RX0N 40 21 RLB+
RX0P 41 20 RLC-
CAVDL 42 19 RLC+
CAGND 43 18 RLCLK-
RX1N 44 17 RLCLK+
RX1P 45 16 RLD-
CAGND 46 15 RLD+
CAVDL 47 14 RLE-
BET 48 13 RLE+
1 2 3 4 5 6 7 8 9 10 11 12
Reserved[0]
Reserved[1]
Reserved[2]
Reserved[3]
Reserved[4]
VDD
VSS
Reserved[5]
DEOUT
COL
LAGND
LAVDH
THCV234
QFN-48pin
Exposed PAD
(TOP VIEW)
49 EXPGND
THCV233-THCV234_Rev.3.10_E
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5. Pin Description Table 2 THCV233 Pin Description
Pin Name Pin # Type* Description
TLA -/+ 37,38
LI
TLB -/+ 39,40
LI
TLC -/+ 41,42
LI
TLCLK -/+ 43,44
LI
TLD -/+ 45,46
LI
TLE -/+ 47,48
LI
TX0N/P 20,19
CO
TX1N/P 17,16
CO
LOCKN
23 ILock detect input(LOCKN).
It must be connected to Rx LOCKN with a Tx side 10kΩ pull-up resistor. LOCKN is input only.
HTPDN
24 IHot plug detect input (HTPDN).
It must be connected to Rx HTPDN with a Tx side 10kΩ pull-up resistor. HTPDN is input only.
Reserved [3,2,0] 11,10,5 -
It must be open.
Reserved [1] 8
- It must be connected with a pull-up resistor to 3.3V.
DEIN 4
I
DE input for LVDS data sets (DEIN).
DEIN is external DE input pin. When input LVDS does not contain DE signal, DE can be provided as external input.
Activation of DEIN function follow the following settings.
DESEL=L : DE input from DEIN is used for processing.
DESEL=H : DE input from LVDS is used for processing.
DESEL 9
IDE input selector.
H : DE input from LVDS is used for processing
L : DE input from DEIN is used for processing
Reserved
[4,5,6,7,8]
12,26,28
33,34
I
It must be connected to GND.
MODE [1:0] 32,31 I
Operation mode select input.
MODE[1:0] =LL : Single-in/Distribution dual-out
=LH : Sing l e -in /Sin g l e -ou t
=HL : Sing l e -in /Dual -ou t
=HH : Reserved (Forbid d en )
PDN 25 I
Power down Schmitt input.
H: Normal operation, L: Power down
PRE 29 I
Pre-Emphasis level select input for High Speed CML signal output.
H : 100%, L : 0%
COL 3 I
Data width setting for High speed CML signal output.
H : 24bit, L : 32bit
BET 27 I
Field-BET entry.
H : Field BET Operation, L : Normal Operation
LAVDH 1,36 P33 LVDS power supply (3.3V)
LAGND 2,35 GND LVDS GND
CAVDL 22,14 P18 High-speed signal analog power supply (1.8V)
CAGND 21,18,15 GND High-speed signal analog GND
CPVDL 13 P18 High-speed signal PLL power supply (1.8V)
VDD 7,30 P18 Logic power supply (1.8V)
VSS 6 GND Logic GND
EXPGND 49 GND EXPOSED PAD GND
*Type symbol
I=3.3V CMOS input
LI=LVDS input, CO=CML output
P33=Power 3.3V, P18=Power 1.8V, GND=GND
LVDS signal input.
High-speed CML signal output.
THCV233-THCV234_Rev.3.10_E
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Table 3 THCV234 Pin Description
Pin Name Pin # Type* Description
RLA -/+ 24,23
LO
RLB -/+ 22,21
LO
RLC -/+ 20,19
LO
RLCLK -/+ 18,17
LO
RLD -/+ 16,15
LO
RLE -/+ 14,13
LO
RX0N/P 40,41
CI
RX1N/P 44,45
CI
LOCKN
38 OD Lock detect output (LOCKN).
It must be connected to Tx LOCKN with a Tx side10kΩ pull-up resistor. LOCKN is output only.
HTPDN
37 OD Hot plug detect output (HTPDN).
It must be connected to Tx HTPDN with a Tx side 10kΩ pull-up resistor. HTPDN is output only.
Reserved [1,2] 2,3 -
It must be open.
Reserved [5] 8
- It must be connected with a pull-up resistor to 3.3V.
DEOUT 9
O
DE signal output (DEOUT) for LVDS data sets.
When used as DEOUT, no external component is required. It is push pull output.
DEOUT output DE timing depending upon data stream state. DEOUT is output only.
Bit Error Test (BET) result output under Field-BET operation
H : No error, L : Bit error occured
DGLOCK 36
BPU
Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK).
When used as DGLOCK, it is internally connected with a pull-up resistor to 3.3V. No external component is required.
LOCKN arrange among Rx Multiple-chip configuration is achieved by connecting all DGLOCK pins.
Reserved
[0,3,4,6,7,8,9]
1,4,5,27,
28,33,34
-It must be connected to GND.
MODE [1:0] 29,30 I
Operation mode select input.
MODE [1:0] =LL : Dual-in/Selected single-out (Lane0)
=LH : Dual-in /Sin g l e -ou t
=HL : Dual-in /Sel e cted single-out (La n e 1 )
=HH : Single-in/Sing l e -ou t
PDN 35 I
Power down Schmitt input.
H: Normal operation, L: Power down
RS 32 I
LVDS output swing range select input.
H : Normal swing (350mv@typ.), L : Reduced swing (200mv@typ.)
Latch select input under Field-BET operation
H : Latched result, L : NOT Latched result
COL 10 I
Data width setting for High Speed CML signal output.
H : 24bit, L : 32bit
BET 48 I
Field-BET entry.
H : Field BET Operation, L : Normal Operation
LAVDH 12,25 P33 LVDS power supply (3.3V)
LAGND 11,26 GND LVDS GND
CAVDL 42,47 P18 High-speed signal analog power supply (1.8V)
CAGND 39,43,46 GND High-speed signal analog GND
VDD 6,31 P18 Logic power supply (1.8V)
VSS 7 GND Logic GND
EXPGND 49 GND Exposed PAD GND
*Type symbol
I=3.3V CMOS input, O=3.3V CMOS output, OD= OpenDrain output
BPU =CMOS Bi-directional buffer with an on-chip pullup resistor
LO=LVDS output, CO=CML output
P33=Power 3.3V, P18=Power 1.8V, GND=GND
LVDS signal output.
High-speed CML signal input.
THCV233-THCV234_Rev.3.10_E
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6. Operation Mode
Table 4
(0°C≤TMP≤70°C)
THCV233
THCV234
Single-In/Single-Out
3.4G
32bit
@85MHz
LVDS
MODE[1:0]=LH
Single-In/Single-Out
3.4G
32bit
@85MHz
LVDS
MODE[1:0]=HH
Single-In/Dual-Out
1.7G
32bit
@85MHz
LVDS
1.7G
MODE[1:0]=HL
Dual-In/Single-Out
1.7G
32bit
@85MHz
LVDS
1.7G
MODE[1:0]=LH
Single-In/Single-Out * 2
3.4G
32bit
@85MHz
LVDS
3.4G
32bit
@85MHz
LVDS
MODE[1:0]=LH
Dual-In/Selected Single-Out
3.4G
32bit
@85MHz
LVDS
3.4G
MODE[1:0]=LL / HL
Single-In/Distributed Dual-Out
3.4G
32bit
@85MHz
LVDS
3.4G
MODE[1:0]=LL
Single-In/Single-Out * 2
3.4G
32bit
@85MHz
LVDS
3.4G
32bit
@85MHz
LVDS
MODE[1:0]=HH
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7. Function Description
Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV233 and THCV234 enable transmission of 24/32bit video data, 2bit control data and Data Enable (DE)
through high speed serial line by single/dual differential pair cable with minimal external components.
THCV233, LVDS data (including video data, control data and DE) and serializes video data and control data
separately, depending on polarity of DE. DE is a signal which indicates whether video or control data are active.
When DE is high, it serializes video data inputs into CML data streams. And it transmits serialized control data
when DE is low. Instead of DE in the LVDS format, THCV233 has DEIN LVCMOS-input pin, which enables to
transfer LVDS input data with external DE input via DEIN.
THCV234, automatically extracts clock from the incoming data streams and converts high-speed serial data into
video data with DE being high or control data with DE being low, recognizing which type of serial data is being
sent by transmitter. And it outputs the recovered data in the form of LVDS data. THCV234 has DEOUT output pin
which transmits DE signal in LVCMOS. THCV234 can seamlessly operate for a wide range of a serial bit rate
from 270Mbps to 3.4Gbps/lane.
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DE signal (TLC[6] / DEIN) Input Requirement
There are some requirements for DE signal as described in Figure 3, Figure 4 Figure 14 and Table 24.
If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and the last pixel are
transmitted. Otherwise video data are transmitted during DE=High.
Control data from receiver in DE=High period are previous data of DE transition. See Figure 4.
The length of DE being low and high is at least 2 clock cycles long, as described in Figure 14 and Table 24.
Data Enable must be toggled like High -> Low -> High at regular interval.
Data bit : R/G/B, CONT
Control bit : V,HSYNC
Data bit : CTL*
H
L
DE
THCV234THCV233
R/G/B,
CONT,
CTL
V,
HSYNC
DE=H R/G/B,CONT
DE=L, CTL* except the 1st and the last pixel
other R/G/B,CONT=Low Fixed
DE=H, V,HSYNC=Fixed
DE=L, V,HSYNC
DE
*CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period.
Figure 3 Conceptual diagram of the basic operation of the chipset
Figure 4 Data bit and control bit transmission when DE is from LVDS (default)
TLCLK +/-
6543210
D
EV H 3 2 1 0
TLn +/-
n=A,B,D,E
TLC +/-
6543210
D
EV H 3 2 1 0
6543210
D
EV H 3 2 1 0
6543210
D
EV H 3 2 1 0
6543210
D
EV H 3 2 1 0
6543210
D
EV H 3 2 1 0
DE=High
Active period
DE=Low
Blanking period
Data : Low fixed
H, V : Keep the last data of blanking period
THCV233
input
THCV234
output
DE input via LVDS Data : Particular assigned bit ‘CTL’ is transmitted except the
first and the last pixel of Blanking period. / Others are Low fixed.
RLCLK +/-
6543210
HV H 3 2 1 0
RLn +/-
n=A,B,D,E
RLC +/-
6543210
LV H 3 2 1 0
6543210
LV H 3 2 1 0
6543210
LV H 3 2 1 0
6543210
HV H 3 2 1 0
6543210
HV H 3 2 1 0
Indefinite region
Indefinite region
DEOUT
(CMOS)
±3/7tTCIP
±3/7tTCIP
tRALN tRALN
Indefinite region
Typ;5tTCIP/7
Typ;5tTCIP/7
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Data Enable input of THCV233 (DEIN)
DEIN is external DE input. When input LVDS does not contain DE signal, DE can be provided via DEIN.
Activation setting of DEIN function is described in the following “Data Enable Select of THCV233”.
Data Enable output of THCV234 (DEOUT)
DEOUT output DE timing depending upon data stream state.
Data Enable Select of THCV233
Depending on pin setting THCV233 can deal with several DE alternatives.
DESEL pin is "choice of DE input" selector.
H : DE input from LVDS is used for processing, L : DE input from DEIN is used for processing
Figure 5 indicate DEIN operation. User must take care of data indefinite region and had better ignore them.
Figure 5 Data bit and control bit transmission when DE is from DEIN
TLCLK +/-
6543210
XV H 3 2 1 0
TLn +/-
n=A,B,D,E
TLC +/-
6543210
XV H 3 2 1 0
6543210
XV H 3 2 1 0
6543210
XV H 3 2 1 0
6543210
XV H 3 2 1 0
6543210
XV H 3 2 1 0
DE=High
Active period
DE=Low
Blanking period
RLCLK +/-
6543210
HV H 3 2 1 0
RLn +/-
n=A,B,D,E
RLC +/-
6543210
LV H 3 2 1 0
6543210
LV H 3 2 1 0
6543210
LV H 3 2 1 0
6543210
HV H 3 2 1 0
6543210
HV H 3 2 1 0
DEIN
(CMOS)
THCV233
input
THCV234
output
DE input via DEIN Data : Low fixed
H, V : Keep the last data of blanking period XIgnored
Indefinite region Indefinite region
DEOUT
(CMOS)
±3/7tTCIP
Data : Particular assigned bit ‘CTL’ is transmitted except the
first and the last pixel of Blanking period. / Others are Low fixed.
tTALN tTALN
±3/7tTCIP
tRALN
Typ;5tTCIP/7 tRALN
Typ;5tTCIP/7
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Color depth or data width setting function (COL)
COL pin enables to select data width. E-ch. (TLE-/+ and RLE-/+) is disable with COL=H.
Table 5 Data Width Setting Function
COL
Mode Function
L
32bit-Data width
H
24bit-Data width
Operation mode function of THCV233 (MODE[1:0])
MODE[1:0] pins select data transfer mode of THCV233 as Table 2.
Table 6 Operation Mode Setting Function for THCV233
MODE[1:0]
Operation mode
LL
Single-in / Distribution Dual-out
LH
Single-in / Single-out
HL
Single-in / Dual-out
HH
Reserved (forbidden)
Operation mode function of THCV234 (MODE[1:0])
MODE[1:0] pins select data transfer mode of THCV234 as Table 2.
Table 7 Operation Mode Setting Function for THCV234
MODE[1:0]
Operation mode
LL
Dual-in / Selected single-out (Lane 0)
LH
Dual-in / Single-out
HL
Dual-in / Selected single-out (Lane 1)
HH
Single-in /Single-out
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Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK)
In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-Rx chip configuration,
THCV234 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 6, the
connected Rx chips can share the CDR lock status, making all the Rx chips in the same operation status.
HTPDN
LOCKN
RX0P/N
RX1P/N
RX2P/N
RX3P/N
Open
THCV234
THCV234
HTPDN
LOCKN
DGLOCK
V-by-One®
HS
Transmitter
DGLOCK
HTPDN
LOCKN
Open
Figure 6 Usage of DGLOCK in multiple-Rx configuration
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LVDS Mapping
LVDS data (video data, control data, DE) are mapped as Figure 7. TLC[6] is special bit for DE(data enable), and
TLC[5:4] are for control data bits and the other bits are for video data. Among video data there are special
assigned bit ‘CTL’ are defined for the data transmission under DE=low condition.
The number of LVDS channel depends on color depth mode(COL).
TLD[6] is not available in 24bit Data-width mode.
TLA6
Vdiff = (TLCLK +) - (TLCLK-)
TLA5 TLA4 TLA3 TLA2 TLA1 TLA0 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1
tTCIP
Vdiff = 0V
next cyclecurrent cycle
TLA2 TLA1
previous cycle
TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLB0 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1TLB2 TLB1
TLC6
(DE) TLC5
(V) TLC4
(H) TLC3 TLC2 TLC1 TLC0 TLC3 TLC2 TLC1TLC2 TLC1
TLD6 TLD5 TLD4 TLD3 TLD2 TLD1 TLD0 TLD6 TLD5 TLD4 TLD3 TLD2 TLD1TLD2 TLD1
TLE6 TLE5 TLE4 TLE3 TLE2 TLE1 TLE0 TLE6 TLE5 TLE4 TLE3 TLE2 TLE1TLE2 TLE1
TLA +/-
TLB +/-
TLC +/-
TLD +/-
TLE +/-
Control data bitData Enable
TLC6
(DE) TLC5
(V) TLC4
(H)
Data width
32, 24
Figure 7 LVDS Data mapping timing diagram
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Table 8 LVDS Color Data Mapping Table
H (8bit) L (10bit)
TLA[0] RLA[0] R[2] R[4] D2
TLA[1] RLA[1] R[3] R[5] D3
TLA[2] RLA[2] R[4] R[6] D4
TLA[3] RLA[3] R[5] R[7] D5
TLA[4] RLA[4] R[6] R[8] D6
TLA[5] RLA[5] R[7] R[9] D7
TLA[6] RLA[6] G[2] G[4] D10
TLB[0] RLB[0] G[3] G[5] D11
TLB[1] RLB[1] G[4] G[6] D12
TLB[2] RLB[2] G[5] G[7] D13
TLB[3] RLB[3] G[6] G[8] D14
TLB[4] RLB[4] G[7] G[9] D15
TLB[5] RLB[5] B[2]*2 B[4]*2 D18
TLB[6] RLB[6] B[3]*2 B[5]*2 D19
TLC[0] RLC[0] B[4]*2 B[6]*2 D20
TLC[1] RLC[1] B[5]*2 B[7]*2 D21
TLC[2] RLC[2] B[6]*2 B[8]*2 D22
TLC[3] RLC[3] B[7]*2 B[9]*2 D23
TLC[4] RLC[4] HSYNC HSYNC Hsync
TLC[5] RLC[5] VSYNC VSYNC Vsync
TLC[6] RLC[6] DE DE DE
TLD[0] RLD[0] R[0] R[2] D0
TLD[1] RLD[1] R[1] R[3] D1
TLD[2] RLD[2] G[0] G[2] D8
TLD[3] RLD[3] G[1] G[3] D9
TLD[4] RLD[4] B[0]*2 B[2]*2 D16
TLD[5] RLD[5] B[1]*2 B[3]*2 D17
TLD[6] RLD[6] N/A*1 CONT[1]*2*3 D25*3
TLE[0] RLE[0] R[0]*2 D30
TLE[1] RLE[1] R[1]*2 D31
TLE[2] RLE[2] G[0]*2 D28
TLE[3] RLE[3] G[1]*2 D29
TLE[4] RLE[4] B[0]*2 D26
TLE[5] RLE[5] B[1]*2 D27
TLE[6] RLE[6] CONT[2]*2*3 D24*3
*1 N/A: Not available, THCV234 output RLDn[6]=Low.
*2 CTL bits, which are carried during DE=Low except the 1st and the last pixel
*3 3D flags defined in the V-by-One® HS Standard are assigned to the following bit.
V-by-One® HS Standard Packer/Unpacker D[24](3DLR) <=> LVDS T/RLE[6]
V-by-One® HS Standard Packer/Unpacker D[25](3DEN) <=> LVDS T/RLD[6]
Channel
Power
Down
THCV233
Input
THCV234
Output
COL
Symbol defined by
V-by-One® HS
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THCV234 LVDS Reduced swing output function (RS)
RS controls THCV234 LVDS output swing level.
Table 9 LVDS output swing level
RS
Output swing
L
Reduced swing (200mV typical)
H
Normal swing (350mV typical)
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CML Buffer
CAVDL
TXnP RXnP
TXnN RXnN
Vterm～1.3v
Zdiff=100W
C=75～
200nF
50W
n=0,1
CAVDL
CAGND
THCV233 THCV234
CML
Transmitter CML
Receiver
50W
C=75～
200nF
Capacitor on transmitter side is mandatory, while receiver side is optional and recommended.
50W
50W
Figure 8 High-Speed CML Buffer Scheme
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Lock detect and Hot-plug function
LOCKN and HTPDN are both open drain outputs from THCV234. Pull-up resistors are needed at THCV233
side to 3.3V. See Figure 9.
If THCV234 is not active (power down mode (PDN=L) or powered off), HTPDN is open. Otherwise, HTPDN is
pulled down by THCV234.
HTPDN of THCV233 side is high when THCV234 is not active or the receiver board is not connected. Then
THCV233 enters into the power down mode. When HTPDN transits from High to Low, THCV233 starts up and
transmits training pattern for link training.
LOCKN indicates whether THCV234 is in the lock state or not. If THCV234 is in the unlock state, LOCKN is
open. Otherwise (in the lock state), it’s pulled down by THCV234.
THCV233 keeps transmitting training pattern until LOCKN transits to Low. After training done, THCV234 sinks
current and LOCKN is Low. Then THCV233 starts transmitting normal data pattern.
Figure 9 Hot-plug and Lock Detect Scheme
No HTPDN connection option
HTPDN connection between THCV233 and THCV234 can be omitted as an application option. In this case,
HTPDN at the Transmitter side should always be taken as Low. See Figure 10.
Figure 10 HTPDN is not Connected Scheme
3.3V
(THCV233 side)
3.3V
(THCV233 side)
HTPDN
LOCKN
10kΩ
THCV233 THCV234
10kΩ
3.3V
(THCV233 side)
HTPDN
LOCKN
10kΩ
THCV233 THCV234
HTPDN
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THCV233 Pre-emphasis function (PRE)
Pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission.
PRE, select the strength of pre-emphasis.
Table 10 Pre-emphasis function table
PRE
Description
L
without Pre-emphasis
H
with 100% Pre-emphasis
Field BET Operation
In order to help users to check validity of high speed serial lines, THCV233/THCV234 has an operation mode in
which they act as a bit error tester (BET). In this mode, THCV233 internally generates test pattern which is then
serialized onto the high speed serial line. THCV234 receives the data stream and checks bit errors.
This "Field BET" mode is activated by setting BET= H both on THCV233 and THCV234. Pattern Generator
CLK is from LVDS-CLK and the pattern is then 8b/10b encoded, scrambled, and serialized onto the high speed
serial lines. As for THCV234, the internal test pattern check circuit gets enabled and reports result on DEOUT pin.
The DEOUT pin goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error. Refer to Figure
11. User can select 2 kinds of check result, “Latched-result” or “NOT latched result”. The latch is reset by setting
RS=L.
Table 11 THCV233-234 Field BET operation pin settings
Table 12 THCV234 Field BET result
Figure 11 Field BET Configuration
DEOUT Output
L Bit error occurred
H No error
THCV233
BET BET RS Operation Output Latch select
L L - Normal Operation -
H
H L NOT latched result
H
H H Latched result
THCV234
Condition
FieldBET Operation
THCV233 THCV234
LVDS-CLK
BET=H
Test
Pattern
Checker
Test Pattern
Generator DEOUT Test Point
for
Field BET
BET=H Latch select
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8. Absolute Maximum Ratings
Table 13 THCV233 Absolute Maximum Ratings
Table 14 THCV234 Absolute Maximum Ratings
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage（CAVDL,CPVDL,VDD）VDL -0.3 - +2.1 V
3.3v Supply Voltage(LAVDH) VDH -0.3 - +4.0 V
CMOS Input Voltage - -0.3 - VDH+0.3 V
LVDS Receiver Input Voltage - -0.3 - VDH+0.3 V
CML Transmitter Output Voltage - -0.3 - VDL+0.3 V
Output Current - -50 - 50 mA
Storage Temperature - -55 - +125 °C
Junction Temperature - - - +125 °C
Reflow Peak Temperature/Time - - - +260/10sec °C
Maximum Power Dissipation @＋25°C - - - 3.2 W
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage(CAVDL,VDD) VDL -0.3 - +2.1 V
3.3v Supply Voltage(LAVDH) VDH -0.3 - +4.0 V
CMOS Input Voltage - -0.3 - VDH+0.3 V
CML Receiver Input Voltage - -0.3 - VDL+0.3 V
LVDS Transmitter Output Voltage - -0.3 - VDH+0.3 V
Output Current - -30 - 30 mA
Storage Temperature - -55 - +125 °C
Junction Temperature - - - +125 °C
Reflow Peak Temperature/Time - - - +260/10sec °C
Maximum Power Dissipation @＋25°C - - - 3.2 W
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9. Operating Conditions
There are two types of operating temperature ranges as shown below.
1. From 0°C to 70°C
2. From -40°C to 105°C
Details are shown in the table below.
Table 15 THCV233 Operating Conditions (0°C≤TMP≤70°C)
Table 16 THCV233 Operating Conditions (-40°C≤TMP≤105°C)
Table 17 THCV234 Operating Conditions (0°C≤TMP≤70°C)
Table 18 THCV234 Operating Conditions (-40°C≤TMP≤105°C)
(1) Maximum value of LVDS CLK Frequency depends on minimum value of VDL. Refer to Table 1.
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage（CAVDL,CPVDL,VDD）VDL 1.62 1.80 1.98 V
3.3v Supply Voltage(LAVDH) VDH 3.00 3.30 3.60 V
Operating Temperature TMP 0 - 70 °C
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage（CAVDL,CPVDL,VDD）VDL
1.62 or 1.70 (1)
1.80 1.98 V
3.3v Supply Voltage(LAVDH) VDH 3.00 3.30 3.60 V
Operating Temperature TMP -40 - 105 °C
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage（CAVDL,CPVDL,VDD）VDL 1.62 1.80 1.98 V
3.3v Supply Voltage(LAVDH) VDH 3.00 3.30 3.60 V
Operating Temperature TMP 0 - 70 °C
Parameter Symbol Min. Typ. Max. Units
1.8v Supply Voltage（CAVDL,CPVDL,VDD）VDL 1.70 1.80 1.98 V
3.3v Supply Voltage(LAVDH) VDH 3.00 3.30 3.60 V
Operating Temperature TMP -40 - 105 °C
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10. Electrical Specifications
DC Specifications
Table 19 THCV233 and THCV234 3.3V CMOS DC Specifications
Table 20 THCV233 LVDS, CML DC Specifications
Table 21 THCV234 LVDS, CML DC Specifications
Symbol Parameter Conditions Min. Typ. Max. Units
VIH High Level Input Voltage I,BPU 2.1 - VDH V
VIL Low Level Input Voltage I,BPU 0 - 0.7 V
VOH High Level Output Voltage O IOH=-8mA 2.4 - VDH V
O IOL=8mA - - 0.4 V
O,BPU IOL=4mA - - 0.4 V
IIH Input Leak Current High VIN=VDH -10 - +10 uA
IIL Input Leak Current Low VIN=GND -10 - +10 uA
VOL
Low Level Output Voltage
Symbol Parameter Conditions Min. Typ. Max. Units
VTTH LVDS Differential Input High Threshold - - - 100 mV
VTTL LVDS Differential Input Low Threshold - -100 - - mV
ITIH LVDS Input Leak Current High
TLx+/-=VDH, PDN=L
x=A~E,CLK
- - ±10 uA
ITIL LVDS Input Leak Current Low
TLx+/-=GND, PDN=L
x=A~E,CLK
- - ±10 uA
RTIN LVDS Differential Input Resistance PDN=L 80 100 120 Ω
VTOD CML Differential Mode Output Voltage
-200 300 400 mV
PRE=L - 0 - %
PRE=H 80 100 120 %
PRE=L mV
PRE=H mV
ITOH CML Output Leak Current High
PDN=L - - ±10 uA
ITOS CML Output Short Circuit Current
VDL=1.8V -90 - - mA
PRE
CML Pre-emphasis Level
VTOC
CML Common Mode Output Voltage
VDL-VTOD
VDL-2×VTOD
Symbol Parameter Conditions Min. Typ. Max. Units
VRTH CML Differential Input High Threshold - - - 50 mV
VRTL CML Differential Input Low Threshold - -50 - - mV
IRIH CML Input Leak Current High
PDN=L, RXnP/N=VDL
n=0,1
- - ±10 uA
IRIL CML Input Leak Current Low
PDN=L, RXnP/N=GND
n=0,1
- - ±10 uA
IRRIH CML Input Current High RXnP/N=VDL, n=0,1 - - 2 mA
IRRIL CML Input Current Low RXnP/N=GND, n=0,1 -6 - - mA
RRIN CML Differential Input Resistance - 80 100 120 Ω
LVDS Differential Mode Output Voltage
(Normal Swing)
RL=100Ω, RS=H 250 350 450 mV
LVDS Differential Mode Output Voltage
(Reduced Swing)
RL=100Ω, RS=L 100 200 300 mV
ΔVROD
Change in VROD between
Complementary Output States
RL=100Ω - - 35 mV
VROC LVDS Common Mode Output Voltage RL=100Ω 1.125 1.25 1.375 V
ΔVROC
Change in VROC between
Complementary Output States
RL=100Ω - - 35 mV
IROS LVDS Output Short Circuit Current RLx+/-=GND -30 - - mA
IROZ LVDS Output TRI-STATE Current
PDN=L,
RLx+/-=GND, VDH
x=A~E,CLK
- - ±10 uA
VROD
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Supply Currents
Table 22 THCV233 Supply Currents
Table 23 THCV234 Supply Currents
Vdiff = (TLCLK +) - (TLCLK -) tTCIP
Vdiff = 0V
next cyclecurrent cycleprevious cycle
TLA +/-
TLB +/-
TLC +/-
TLD +/-
TLE +/-
Control bitData Enable
H H
Figure 12 Worst Case Pattern
Symbol Parameter Conditions Min. Typ. Max. Units
SiSo 10bit, PRE=H
PDN=H
- - 150 mA
SiDo 10bit, PRE=H
PDN=H
- - 185 mA
SiDDo 10bit, PRE=H
PDN=H
- - 225 mA
SiSo 10bit, PRE=H
PDN=H
- - 12 mA
SiDo 10bit, PRE=H
PDN=H
- - 12 mA
SiDDo 10bit, PRE=H
PDN=H
- - 12 mA
ITCCS
Transmitter Power Down
Supply Current
PDN=L
All Inputs =Fixed LorH
- - 170 uA
ITCCW_M
Transmitter Supply Current for VDL
(Worst Case Pattern as shown in Figure 12)
ITCCW33_M
Transmitter Supply Current for VDH
(Worst Case Pattern as shown in Figure 12)
Symbol Parameter Conditions Min. Typ. Max. Units
SiSo 10bit, PDN=H - - 90 mA
DiSo 10bit, PDN=H - - 90 mA
DiSSo 10bit, PDN=H - - 90 mA
SiSo 10bit, P PDN=H - - 90 mA
DiSo 10bit, PDN=H - - 90 mA
DiSSo 10bit, PDN=H - - 90 mA
IRCCS
Receiver Power Down
Supply Current
PDN=L
All Inputs =Fixed LorH
- - 150 uA
Receiver Supply Current for VDL
(Worst Case Pattern as shown in Figure 12)
Receiver Supply Current for VDH
(Worst Case Pattern as shown in Figure 12)
IRCCW33_M
IRCCW_M
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Switching Characteristics
Table 24 DE signal (TLC[6] / DEIN) Input Requirement
Table 25 THCV233 Switching Characteristics (0°C≤TMP≤70°C)
Symbol Parameter Conditions Min. Typ. Max. Units
tDEH DE=High Duration - 2×tTCIP - - sec
SiSo, SiDDo 2×tTCIP - - sec
SiDo 4×tTCIP - - sec
tDEL
DE=Low Duration
Symbol Parameter Conditions Min. Typ. Max. Units
COL=H, Si/So 10 -111 ns
COL=H, Si/DDo 10 -50 ns
COL=H, Si/Do 10 -25 ns
COL=L, Si/So 11.76 - 111 ns
COL=L, Si/DDo 11.76 - 50 ns
COL=L, Si/Do 11.76 - 25 ns
tTCIH LVDS Differential Clock High Time - 2×tTCIP/7 4×tTCIP/7 5×tTCIP/7 ns
tTCIL LVDS Differential Clock Low Time - 2×tTCIP/7 3×tTCIP/7 5×tTCIP/7 ns
tTCIP=75MHz -440 - 440 ps
tTCIP=85MHz -390 - 390 ps
tTCIP=100MHz -330 - 330 ps
tTIP1
LVDS Input Data Position1 - -tSK 0 +tSK ns
tTIP0
LVDS Input Data Position0 - tTCIP/7-tSK tTCIP/7 tTCIP/7+tSK ns
tTIP6
LVDS Input Data Position2 - 2×tTCIP/7-tSK 2×tTCIP/7 2×tTCIP/7+tSK ns
tTIP5
LVDS Input Data Position3 - 3×tTCIP/7-tSK 3×tTCIP/7 3×tTCIP/7+tSK ns
tTIP4
LVDS Input Data Position4 - 4×tTCIP/7-tSK 4×tTCIP/7 4×tTCIP/7+tSK ns
tTIP3
LVDS Input Data Position5 - 5×tTCIP/7-tSK 5×tTCIP/7 5×tTCIP/7+tSK ns
tTIP2
LVDS Input Data Position6 - 6×tTCIP/7-tSK 6×tTCIP/7 6×tTCIP/7+tSK ns
tTALN
LVDS-ALNIN timing tolerance - 0 - 3×tTCIP/7 ns
tTRF
CML Output Rise and Fall Time(20%-80%) - 50 -150 ps
tTOSK
CML Lane0/1 Output Inter Pair Skew - -2 - 2 UI
tTCD Input Clock to Output Data Delay SiDDo 10bit 85MHz 143.4 - 150.2 ns
tTLH VDL On to VDH On Delay - 0 - - ns
tTPD Power On to PDN High Delay - 0 - - ns
tTPDL PDN Low Pulse Width - 1 - - ms
tTPLL0
PDN High to CML Output Delay - - - 10 ms
tTPLL1
PDN Low to CML Output High Fix Delay - - - 20 ns
tTNP0
LOCKN High to Training Pattern Output Delay - - - 10 ms
tTNP1
LOCKN Low to Data Pattern Output Delay - - - 10 ms
tTCIP
TLCLK Period
tSK
LVDS Receiver Skew Margin
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Table 26 THCV233 Switching Characteristics (-40°C≤TMP≤105°C)
Symbol Parameter Conditions Min. Typ. Max. Units
COL=H, Si/So 10 -111 ns
COL=H, Si/DDo 10 -50 ns
COL=H, Si/Do 10 -25 ns
COL=L, Si/So
VDL=1.62V~1.98V
13.33 - 111 ns
COL=L, Si/DDo
VDL=1.62V~1.98V
13.33 - 50 ns
COL=L, Si/Do
VDL=1.62V~1.98V
13.33 - 25 ns
COL=L, Si/So
VDL=1.7V~1.98V
12.35 - 111 ns
COL=L, Si/DDo
VDL=1.7V~1.98V
12.35 - 50 ns
COL=L, Si/Do
VDL=1.7V~1.98V
12.35 - 25 ns
tTCIH LVDS Differential Clock High Time - 2×tTCIP/7 4×tTCIP/7 5×tTCIP/7 ns
tTCIL LVDS Differential Clock Low Time - 2×tTCIP/7 3×tTCIP/7 5×tTCIP/7 ns
tTCIP=75MHz -440 - 440 ps
tTCIP=85MHz -390 - 390 ps
tTCIP=100MHz -330 - 330 ps
tTIP1
LVDS Input Data Position1 - -tSK 0 +tSK ns
tTIP0
LVDS Input Data Position0 - tTCIP/7-tSK tTCIP/7 tTCIP/7+tSK ns
tTIP6
LVDS Input Data Position2 - 2×tTCIP/7-tSK 2×tTCIP/7 2×tTCIP/7+tSK ns
tTIP5
LVDS Input Data Position3 - 3×tTCIP/7-tSK 3×tTCIP/7 3×tTCIP/7+tSK ns
tTIP4
LVDS Input Data Position4 - 4×tTCIP/7-tSK 4×tTCIP/7 4×tTCIP/7+tSK ns
tTIP3
LVDS Input Data Position5 - 5×tTCIP/7-tSK 5×tTCIP/7 5×tTCIP/7+tSK ns
tTIP2
LVDS Input Data Position6 - 6×tTCIP/7-tSK 6×tTCIP/7 6×tTCIP/7+tSK ns
tTALN
LVDS-ALNIN timing tolerance - 0 - 3tTCIP/7 ns
tTRF
CML Output Rise and Fall Time(20%-80%) - 50 -150 ps
tTOSK
CML Lane0/1 Output Inter Pair Skew - -2 - 2 UI
tTCD Input Clock to Output Data Delay SiDDo 10bit 85MHz 143.4 - 150.2 ns
tTLH VDL On to VDH On Delay - 0 - - ns
tTPD Power On to PDN High Delay - 0 - - ns
tTPDL PDN Low Pulse Width - 1 - - ms
tTPLL0
PDN High to CML Output Delay - - - 10 ms
tTPLL1
PDN Low to CML Output High Fix Delay - - - 20 ns
tTNP0
LOCKN High to Training Pattern Output
Delay - - - 10 ms
tTNP1
LOCKN Low to Data Pattern Output
Delay - - - 10 ms
tSK
tTCIP
LVDS Receiver Skew Margin
TLCLK Period
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Table 27 THCV234 Switching Characteristics (0°C≤TMP≤70°C)
Table 28 THCV234 Switching Characteristics (-40°C≤TMP≤105°C)
Symbol Parameter Conditions Min. Typ. Max. Units
COL=H 333 tTCIP/30 3704 ps
COL=L 294 tTCIP/40 2778 ps
tRISK CML Lane0/1 Input Inter Pair Skew Margin - - - 15 UI
tRLVT LVDS Differential Output Transition Time - - 0.6 1.5 ns
tROP1
LVDS Output Data Position1 SiSo 10bit 85MHz -0.2 0 0.2 ns
tROP0
LVDS Output Data Position0 SiSo 10bit 85MHz tTCIP/7-0.2 tTCIP/7 tTCIP/7+0.2 ns
tROP6
LVDS Output Data Position6 SiSo 10bit 85MHz 2×tTCIP/7-0.2 2×tTCIP/7 2×tTCIP/7+0.2 ns
tROP5
LVDS Output Data Position5 SiSo 10bit 85MHz 3×tTCIP/7-0.2 3×tTCIP/7 3×tTCIP/7+0.2 ns
tROP4 LVDS Output Data Position4 SiSo 10bit 85MHz 4×tTCIP/7-0.2 4×tTCIP/7 4×tTCIP/7+0.2 ns
tROP3 LVDS Output Data Position3 SiSo 10bit 85MHz 5×tTCIP/7-0.2 5×tTCIP/7 5×tTCIP/7+0.2 ns
tROP2 LVDS Output Data Position2 SiSo 10bit 85MHz 6×tTCIP/7-0.2 6×tTCIP/7 6×tTCIP/7+0.2 ns
tRALN
LVDS-ALNOUT timing accuracy - 2×tTCIP/7 5×tTCIP/7 8tTCIP/7 ns
tRDC Input Data to Output Clock Delay SiSo 10bit 808×tRBIT+8 - 808×tRBIT+14.5 ns
tRLH VDL On to VDH On Delay - 0 - - ns
tRPD Power On to PDN High Delay - 0 - - ns
tRPDL PDN Low Pulse Width - 1.0 - - ms
tRHPD0
PDN High to HTPDN Low Delay - - - 1 us
tRHPD1
PDN Low to HTPDN High Delay - - - 1 us
tRPLL0
Training Pattern Input to LOCKN Low
Delay - - - 10 ms
tRPLL1
PDN Low to LOCKN High Delay - - - 10 us
tRLCK0
LOCKN Low to LVDS Output Delay - - - 1 ms
tRLCK1
LOCKN High to LVDS HighZ Delay - - - 0 ns
tRBIT
Unit Interval
Symbol Parameter Conditions Min. Typ. Max. Units
COL=H 351 tTCIP/30 3704 ps
COL=L 351 tTCIP/40 2778 ps
tRISK CML Lane0/1 Input Inter Pair Skew Margin - - - 15 UI
tRLVT LVDS Differential Output Transition Time - - 0.6 1.5 ns
tROP1
LVDS Output Data Position1 SiSo 10bit 85MHz -0.2 0 0.2 ns
tROP0
LVDS Output Data Position0 SiSo 10bit 85MHz tTCIP/7-0.2 tTCIP/7 tTCIP/7+0.2 ns
tROP6
LVDS Output Data Position6 SiSo 10bit 85MHz 2×tTCIP/7-0.2 2×tTCIP/7 2×tTCIP/7+0.2 ns
tROP5
LVDS Output Data Position5 SiSo 10bit 85MHz 3×tTCIP/7-0.2 3×tTCIP/7 3×tTCIP/7+0.2 ns
tROP4 LVDS Output Data Position4 SiSo 10bit 85MHz 4×tTCIP/7-0.2 4×tTCIP/7 4×tTCIP/7+0.2 ns
tROP3 LVDS Output Data Position3 SiSo 10bit 85MHz 5×tTCIP/7-0.2 5×tTCIP/7 5×tTCIP/7+0.2 ns
tROP2 LVDS Output Data Position2 SiSo 10bit 85MHz 6×tTCIP/7-0.2 6×tTCIP/7 6×tTCIP/7+0.2 ns
tRALN
LVDS-ALNOUT timing accuracy - 2×tTCIP/7 5×tTCIP/7 8×tTCIP/7 ns
tRDC Input Data to Output Clock Delay SiSo 10bit 808×tRBIT+8 - 808×tRBIT+14.5 ns
tRLH VDL On to VDH On Delay - 0 - - ns
tRPD Power On to PDN High Delay - 0 - - ns
tRPDL PDN Low Pulse Width - 1.0 - - ms
tRHPD0
PDN High to HTPDN Low Delay - - - 1 us
tRHPD1
PDN Low to HTPDN High Delay - - - 1 us
tRPLL0
Training Pattern Input to LOCKN Low
Delay - - - 10 ms
tRPLL1
PDN Low to LOCKN High Delay - - - 10 us
tRLCK0
LOCKN Low to LVDS Output Delay - - - 1 ms
tRLCK1
LOCKN High to LVDS HighZ Delay - - - 0 ns
Unit Interval
tRBIT
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11. AC Timing Diagrams and Test Circuits
LVDS Input Switching Characteristics
TLx6
Vdiff = (TLCLK+) - (TLCLK-)
x=A,B,C,D,E
TLx5 TLx4 TLx3 TLx2 TLx1 TLx0 TLx6 TLx5 TLx4 TLx3 TLx2 TLx1
Vdiff = (TLx +) - (TLx -)
tTCIP
Vdiff = 0V
tTIP1
tTIP0
tTIP6
tTIP5
tTIP4
tTIP3
tTIP2
Vdiff = (TLCLK +) - (TLCLK -) Vdiff = 0V
tTCIH tTCIL
Figure 13 LVDS Input Switching Timing Diagrams
Vdiff = (TLCLK0+) – (TLCLK0-)
Vdiff = (TLC0+) – (TLC0-)
DE DE DE DE DE DE
tDEH tDEL
Figure 14 DE period requirement
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LVDS Output Switching Characteristics
RLx6
Vdiff = (RLCLK +) - (RLCLK-)
x=A,B,C,D,E
RLx5 RLx4 RLx3 RLx2 RLx1 RLx0 RLx6 RLx5 RLx4 RLx3 RLx2 RLx1
Vdiff = (RLx +) - (RLx-)
tROP1
tROP0
tROP6
tROP5
tROP4
tROP3
tROP2
tTCIP
Vdiff = 0V
Figure 15 LVDS Output Switching Timing Diagrams
RL=100W
5pF
20%
80%
RLx+
RLx-
x=A,B,C,D,E
Vdiff = (RLx +) - (RLx-)
tRLVT tRLVT
Figure 16 LVDS Output Switching Timing Diagram and Test Circuit.
THCV233-THCV234_Rev.3.10_E
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CML Output Switching Characteristics
TXnP
TXnN
n=0,1
100nF
100nF
< 5mm
20%
80%
Vdiff = (TXnP) - (TXnN)
tTRF tTRF
Vdiff = (TX0P) - (TX0N)
Vdiff = (TX1P) - (TX1N)
tTOSK
Vdiff = (RX0 +) - (RX0-)
Vdiff = (RX1 +) - (RX1-)
tRISK
50W
50W
Vdiff = 0V
Vdiff = 0V
Vdiff = 0V
Vdiff = 0V
Figure 17 High-Speed CML Output Switching Timing Diagrams and Test Circuit
THCV233-THCV234_Rev.3.10_E
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Latency Characteristics
Vdiff = (TLCLK +) - (TLCLK -) Vdiff = 0V
tTCD
Vdiff = (TX0 +) - (TX0-)
Vdiff = (RX0 +) - (RX0-)
Vdiff = 0V
tRDC
pixel 1st bit
pixel 1st bit
Vdiff = (RLCLK +) - (RLCLK -)
Figure 18 THCV233 and THCV234 Latency
THCV233-THCV234_Rev.3.10_E
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Lock and Unlock Sequence
Figure 19 THCV233 and THCV234 Lock/Unlock Sequence
VDH must not precedes VDL, while tTLH and tRLH min. is 0sec; therefore, VDL/H can be at the same time.
tTPD and tRPD minimum is 0sec; therefore, PDN can be applied at the same time as VDL and VDH.
tTPLL0 is the time from “both PDN=High and HTPDN=Low“ moment to Training pattern ignition.
HTPDN could transit from High to Low under PDN=High condition at THCV233, which is different from what
Figure 19 indicates but is natural situation.
Power OnVDH
TLCLK +/-
HTPDN Low-level
PDN
LOCKN
RX0P/N
Fix to VDL CDR Training
pattern Normal
pattern
tTPLL0 tTNP1 tTNP0 tTPLL1
HTPDN
PDN
LOCKN
Normal
pattern
tRHPD0
tRPLL0 tRPLL1
tRHPD1
TX0P/N
RLx +/-
High Z
tRLCK0 tRLCK1
Data PatternTLx +/-
3.0V
tTPD
tRPD
x=A,B,C,D,E
High Z Valid Data
Pattern
RLCLK +/-
x=A,B,C,D,E
Power OnVDL 1.62V
tTLH
Power OnVDH
3.0V
Power OnVDL 1.62V
tRLH
THCV233
THCV234
tTPDL
tRPDL
ALN Training
pattern CDR Training
pattern Normal
pattern
CDR Training
pattern ALN Training
pattern
THCV233-THCV234_Rev.3.10_E
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Note
1)LVDS input pin connection
When LVDS line is not driven from the previous device, the line is pulled up to 3.3V internally in
THCV233.This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose
operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of
the whole system including THCV233. One solution for this problem is PDN=L control during no LVDS input
period because pull-up resistors are cut off at power down state.
2)Power On Sequence
Do not apply VDH before VDL. VDL and VDH can be applied at the same time.
3)Data Input Sequence
Don’t input TLCLK+/- before THCV233 is on in order to keep absolute maximum ratings.
4)Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.
5)GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THCV233-234 on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.
6)Low Input Pulse into PDN Period Requirement
Don’t Input Low Pulse within 1msec into PDN.
VDD
LVDS input buffer
Internal circuit of THCV233
Low VDD
LVDS Tx
THCV233
or
LVDS Tx
integrated
device
LVDS Tx side PCB LVDS Rx side PCB
THCV233-THCV234_Rev.3.10_E
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7)Multiple device connection
HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure.
HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx.
LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data.
LOCKN of Tx side can be simply split to multiple Tx.
THCV234 DGLOCK connection is appropriate for multiple Rx use.
Also possible time difference of internal processing time (p.23 to 24 THCV233 tTCD and p.25 THCV234 tRDC)
on multiple data stream must be accommodated and compensated by the following destination device connected
to multiple THCV234, which may have internal FIFO.
THCV233
HTPDN
LOCKN
THCV233
HTPDN
LOCKN
THCV234
HTPDN
LOCKN
DGLOCK
THCV234
HTPDN
LOCKN
DGLOCK
Source
Device Destination
Device
Ex. synchronized Time diff. comes up
clkin.1
clkin.2
clkout.1
clkout.2
Internal processing time tTCD Internal processing time tRDC
FIFO
FIFO
THCV233-THCV234_Rev.3.10_E
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Package
Exposed PAD is GND and must be soldered to PCB.
4.03
4.03
7.00
7.00
TOP VIEW SIDE VIEW
BOTTOM VIEW
1 PIN INDEX
1
12
13 24
36
25
48 37
SEATING PLANE
0.25
0.50 0.40
1.085
1.085
0.40
0.450
1 PIN ID
0.20 R
0.125 R
0.85
0.65 0.20
0.025
0.10
Unit:mm
THCV233-THCV234_Rev.3.10_E
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to
the customer's design. We are not responsible for possible errors and omissions in this material. Please note if
errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the
contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will
be exempted from the responsibility unless it directly relates to the production process or functions of the
product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video device,
office automation device, communication device, consumer electronics, smartphone, feature phone, and
amusement machine device. This product must not be used for applications that require extremely
high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control
device, combustion chamber device, medical device related to critical care, or any kind of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product
conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet.
THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified
Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the
user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain
small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have
sufficiently redundant or error preventive design applied to the use of the product so as not to have our product
cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to
support warranty for performance of this product. Except where mandated by applicable law or deemed
necessary by THine based on the user’s request, testing of all functions and performance of the product is not
necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking
and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such
as fuses.
THine Electronics, Inc.
sales@thine.co.jp
http://www.thine.co.jp