DESCRIPTION
The 4524 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
main clock selection function, serial I/O, four 8-bit timers (each
timer has one or two reload registers), 10-bit A/D converter, inter-
rupts, and LCD control circuit.
The various microcomputers in the 4524 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
●Minimum instruction execution time .................................. 0.5
µ
s
(at 6 MHz oscillation frequency, in high-speed through-mode)
●Supply voltage
Mask ROM version...................................................... 2.0 to 5.5 V
One Time PROM version............................................. 2.5 to 5.5 V
(It depends on oscillation frequency and operation mode)
●Timers
Timer 1...................................... 8-bit timer with a reload register
Timer 2...................................... 8-bit timer with a reload register
Timer 3...................................... 8-bit timer with a reload register
Timer 4................................. 8-bit timer with two reload registers
Timer 5..............................16-bit timer (fixed dividing frequency)
Part number
M34524M8-XXXFP
M34524MC-XXXFP
M34524EDFP (Note)
ROM type
Mask ROM
Mask ROM
One T ime PROM
Package
64P6N-A
64P6N-A
64P6N-A
RAM size
(✕ 4 bits)
512 words
512 words
512 words
ROM (PROM) size
(✕ 10 bits)
8192 words
12288 words
16384 words
●Interrupt ........................................................................ 9 sources
●Key-on wakeup function pins ................................................... 10
● LCD control circuit
Segment output ........................................................................ 20
Common output.......................................................................... 4
●Serial I/O......................................................................... 8-bit ✕ 1
●A/D converter ..............10-bit successive approximation method
●Voltage drop detection circuit (Reset) .........................Typ. 3.5 V
●Watchdog timer
●Clock generating circuit
Main clock
(ceramic resonator/RC oscillation/internal on-chip oscillator)
Sub-clock
(quartz-crystal oscillation)
●LED drive directly enabled (port D)
APPLICATION
Household appliance, consumer electronics, office automation
equipment
Note: Shipped in blank.
4524 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0091-0200Z
Rev.2.00
2004.07.27
Rev.2.00 Jul 27, 2004 page 1 of 159
REJ03B0091-0200Z
Rev.2.00 Jul 27, 2004 page 2 of 159
REJ03B0091-0200Z
4524 Group
PIN CONFIGURATION
Pin configuration (top view) (4524 Group)
OUTLINE 64P6N-A
6
4
4
9
50
5
1
5
2
53
5
4
55
56
5
7
58
5
9
6
0
61
6
2
63
78910111
2131
4151
6345612
17
3
2
31
30
2
9
2
8
27
2
6
2
5
24
23
2
2
21
20
1
9
1
8
D
3
P
3
1
/
A
I
N
5
P
3
0
/
A
I
N
4
P
0
0
P
0
1
P
0
2
P
0
3
P
1
1
P
1
3
P
1
0
P
1
2
D
1
D
2
R
E
S
E
T
P
3
3
/
A
I
N
7
P
3
2
/
A
I
N
6
XC
O
U
T
XCIN
C
N
V
S
S
X
O
U
T
X
IN
V
SS
V
D
D
D
5
/
S
O
U
T
D
4
/
S
I
N
4
84
74
24
14
0393
83
73
6353
43
346 45 44 43
SEG
14
S
E
G
1
5
S
E
G
1
3
SEG
12
D
0
V
D
C
E
P
2
1
/
A
I
N
1
P
2
2
/
A
I
N
2
S
E
G
6
S
E
G
5
SEG
4
S
E
G
3
V
LC
1
/SEG
2
V
L
C
2
/
S
E
G
1
V
L
C
3
/
S
E
G
0
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
7
SEG
8
S
E
G
9
S
E
G
1
1
P
2
3
/
A
I
N
3
SEG
10
S
E
G
1
6
D
7
/CNTR0
C
/
C
N
T
R
1
D
8
/INT0
D
9
/
I
N
T
1
D
6
/S
CK
M34524Mx-XXXFP
M34524EDFP
S
E
G
1
9
P
2
0
/
A
I
N
0
S
E
G
1
7
S
E
G
1
8
P
4
1
P
4
0
P
4
3
P
4
2
Rev.2.00 Jul 27, 2004 page 3 of 159
REJ03B0091-0200Z
4524 Group
Block diagram (4524 Group)
4
4
4
2
0
4
4
4
8
1
2
R
A
M
R
O
M
M
e
m
o
r
y
I
/
O
p
o
r
t
I
n
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n
a
l
p
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p
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f
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t
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s
T
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T
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1
(
8
b
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s
)
S
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T
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m
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r
2
(
8
b
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t
s
)
5
1
2
w
o
r
d
s
✕
4
b
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L
C
D
d
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p
l
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y
R
A
M
i
n
c
l
u
d
i
n
g
2
0
w
o
r
d
s
✕
4
b
i
t
s
8
1
9
2
,
1
2
2
8
8
,
1
6
3
8
4
w
o
r
d
s
✕
1
0
b
i
t
s
4
5
0
0
s
e
r
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s
C
P
U
c
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R
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g
i
s
t
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B
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
A
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
D
(
3
b
i
t
s
)
R
e
g
i
s
t
e
r
E
(
8
b
i
t
s
)
S
t
a
c
k
r
e
g
i
s
t
e
r
S
K
(
8
l
e
v
e
l
s
)
I
n
t
e
r
r
u
p
t
s
t
a
c
k
r
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g
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t
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S
D
P
(
1
l
e
v
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)
A
L
U
(
4
b
i
t
s
)
W
a
t
c
h
d
o
g
t
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m
e
r
(
1
6
b
i
t
s
)
P
o
r
t
P
0
P
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P
1
P
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P
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w
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8
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T
i
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(
8
b
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M
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.
2
0
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g
m
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✕
4
c
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)
X
I
N
-
X
O
U
T
(
M
a
i
n
c
l
o
c
k
)
X
C
I
N
-
X
C
O
U
T
(
S
u
b
-
c
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c
k
)
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P
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P
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P
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T
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5
(
1
6
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P
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P
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P
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S
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r
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/
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(
8
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✕
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/
D
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✕
8
c
h
)
Rev.2.00 Jul 27, 2004 page 4 of 159
REJ03B0091-0200Z
4524 Group
PERFORMANCE OVERVIEW Function
159
0.5
µ
s (at 6 MHz oscillation frequency, in high-speed through mode)
8192 words ✕ 10 bits
12288 words ✕ 10 bits
16384 words ✕ 10 bits
512 words ✕ 4 bits (including LCD display RAM 20 words ✕ 4 bits)
Eight independent I/O ports.
Input is examined by skip decision.
The output structure can be switched by software.
Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin.
Two independent output ports.
Ports D8 and D9 are also used as INT0 and INT1, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; Ports P20–P23 are also used as AIN0–AIN3, respectively.
4-bit I/O port; Ports P30–P33 are also used as AIN4–AIN7, respectively.
4-bit I/O port; The output structure can be switched by software.
1-bit output; Port C is also used as CNTR1 pin.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with two reload registers.
16-bit timer, fixed dividing frequency
10-bit ✕ 1, 8-bit comparator is equipped.
8-bit ✕ 1
1/2, 1/3 bias
2, 3, 4 duty
4
20
2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (they can be switched by software.)
9 (two for external, five for timer, A/D, serial I/O)
1 level
8 levels
CMOS silicon gate
64-pin plastic molded QFP (64P6N)
–20 °C to 85 °C
2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.8 mA (Ta=25°C, VDD = 5 V, f(X IN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN))
20
µ
A (Ta=25°C, VDD = 5 V, f(XCIN) = 32 kHz)
0.1
µ
A (Ta=25°C, VDD = 5 V)
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
Input/Output
ports
Timers
A/D converter
Serial I/O
LCD control
circuit
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply
voltage
Power
dissipation
ROM
RAM
D0–D7
D8, D9
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
C
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Selective bias value
Selective duty value
Common output
Segment output
Internal resistor for
power supply
Sources
Nesting
Mask ROM version
One Time PROM version
Active mode
Clock operating mode
At RAM back-up
M34524M8
M34524MC
M34524ED
I/O
Output
I/O
I/O
I/O
I/O
I/O
Output
Rev.2.00 Jul 27, 2004 page 5 of 159
REJ03B0091-0200Z
4524 Group
PIN DESCRIPTION
Name
Power supply
Ground
CNVSS
Voltage drop
detection circuit
enable
Reset input/output
Main clock input
Sub-clock input
Sub-clock output
Pin
VDD
VSS
CNVSS
VDCE
RESET
XIN
XCIN
XCOUT
Input/Output
—
—
—
Input
I/O
Input
Input
Output
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is
input to this pin, the circuit starts operating. When “L“ level is input to this pin, the
circuit stops operating.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the
built-in power-on reset or the voltage drop detection circuit causes the system to be
reset, the RESET pin outputs “L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, con-
nect it between pins XIN and XOUT. A feedback resistor is built-in between them.
When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave
XOUT pin open.
I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator
between pins XCIN and XCOUT. A feedback resistor is built-in between them.
XOUT Main clock output Output
D0–D7
D8, D9
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
Port C
COM0–
COM3
SEG
0
–SEG
19
VLC3–VLC1
CNTR0,
CNTR1
INT0, INT1
AIN0–AIN7
SCK
SOUT
SIN
I/O port D
Input is examined by
skip decision.
Output port D
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Output port C
Common output
Segment output
LCD power supply
Timer input/output
Interrupt input
Analog input
Serial I/O data I/O
Serial I/O data output
Serial I/O clock input
I/O
Output
I/O
I/O
I/O
I/O
I/O
Output
Output
Output
–
I/O
Input
Input
I/O
Output
Input
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Ports D4–D7
is also used as SIN, SOUT, SCK and CNTR0 pin.
Each pin of port D has an independent 1-bit wide output function. The output struc-
ture is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1
pin, respectively.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P2 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P20–P23 are also used as AIN0–AIN3, respectively.
Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P30–P33 are also used as AIN4–AIN7, respectively.
Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain.
1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin.
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
LCD segment output pins. SEG
0
–SEG
2
pins are used as V
LC3
–V
LC1
pins, respectively.
LCD power supply pins.
When the internal resistor is used, VDD pin is connected to VLC3 pin (if luminance ad-
justment is required, VDD pin is connected to VLC3 pin through a resistor).
When the external power supply is used, apply the voltage 0 ≤ VLC1 ≤ VLC2 ≤ VLC3 ≤ VDD.
V
LC3
–V
LC1
pins are used as SEG
0
–SEG
2
pins, respectively.
CNTR0 pin has the function to input the clock for the timer 1 event counter, and to
output the timer 1 or timer 2 underflow signal divided by 2.
CNTR1 pin has the function to input the clock for the timer 3 event counter, and to
output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also
used as Ports D7 and C, respectively.
INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup func-
tion which can be switched by software. INT0 pin and INT1 pin are also used as
Ports D8 and D9, respectively.
A/D converter analog input pins. AIN0–AIN7 are also used as ports P20–P23 and P30–
P33, respectively.
Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port D6.
Serial I/O data output pin. SOUT pin is also used as port D5.
Serial I/O data input pin. SIN pin is also used as port D4.
Rev.2.00 Jul 27, 2004 page 6 of 159
REJ03B0091-0200Z
4524 Group
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
Register MR System clock
f(STCK) = f(XIN) or f(RING)
f(STCK) = f(XCIN)
f(STCK) = f(XIN)/2 or f(RING)/2
f(STCK) = f(XCIN)/2
f(STCK) = f(XIN)/4 or f(RING)/4
f(STCK) = f(XCIN)/4
f(STCK) = f(XIN)/8 or f(RING)/8
f(STCK) = f(XCIN)/8
Table Selection of system clock
✕: 0 or 1
Note: The f(RING)/8 is selected after system is released from reset.
MR2
0
1
0
1
MR3
0
0
1
1
Operation mode
High-speed through mode
Low-speed through mode
High-speed frequency divided by 2 mode
Low-speed frequency divided by 2 mode
High-speed frequency divided by 4 mode
Low-speed frequency divided by 4 mode
High-speed frequency divided by 8 mode
Low-speed frequency divided by 8 mode
● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
● Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle gen-
erates the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
MR0
0
1
0
1
0
1
0
1
MR1
0
✕
0
✕
0
✕
0
✕
Notes 1: Pins except above have just single function.
2: The output of D8 and D9 can be used even when INT0 and INT1 are selected.
3: The input of ports D4–D6 can be used even when SIN, SOUT and SCK are selected.
4: The input/output of D7 can be used even when CNTR0 (input) is selected.
5: The input of D7 can be used even when CNTR0 (output) is selected.
6: The port C “H” output function can be used even when CNTR1 (output) is selected.
Pin
D4
D5
D6
D7
D8
D9
VLC3
VLC2
VLC1
Multifunction
SIN
SOUT
SCK
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
MULTIFUNCTION Pin
SIN
SOUT
SCK
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
Multifunction
D4
D5
D6
D7
D8
D9
VLC3
VLC2
VLC1
Pin
C
P20
P21
P22
P23
P30
P31
P32
P33
Multifunction
CNTR1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Pin
CNTR1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Multifunction
C
P20
P21
P22
P23
P30
P31
P32
P33
Rev.2.00 Jul 27, 2004 page 7 of 159
REJ03B0091-0200Z
4524 Group
PORT FUNCTION
Port
Port D
Port P0
Port P1
Port P2
Port P3
Port P4
Port C
I/O
unit
1
4
4
4
4
4
1
Control
instructions
SD, RD
SZD
CLD
OP0A
IAP0
OP1A
IAP1
OP2A
IAP2
OP3A
IAP3
OP4A
IAP4
RCP
SCP
Control
registers
FR1, FR2
J1
W6
I1, I2
K2
FR0
PU0
K0
FR0
PU1
K1
Q2
Q3
FR3
W4
Output structure
N-channel open-drain/
CMOS
N-channel open-drain
N-channel open-drain/
CMOS
N-channel open-drain/
CMOS
N-channel open-drain
N-channel open-drain
N-channel open-drain/
CMOS
CMOS
Input
Output
I/O
(8)
Output
(2)
I/O
(4)
I/O
(4)
I/O
(4)
I/O
(4)
I/O
(4)
Output
(1)
RemarkPin
D0–D3, D4/SIN,
D5/SOUT, D6/SCK,
D7/CNTR0
D8/INT0, D9/INT1
P00–P03
P10–P13
P20/AIN0–P23/AIN3
P30/AIN4–P33/AIN7
P40–P43
C/CNTR1
Output structure selection
function (programmable)
Key-on wakeup function
(programmable)
Built-in programmable pull-up
functions and key-on wakeup
functions (programmable)
Built-in programmable pull-up
functions and key-on wakeup
functions (programmable)
Output structure selection
function (programmable)
Rev.2.00 Jul 27, 2004 page 8 of 159
REJ03B0091-0200Z
4524 Group
CONNECTIONS OF UNUSED PINS
Connection
Connect to VSS.
Open.
Connect to VSS.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Open.
Open.
Open.
Open.
Pin
XIN
XOUT
XCIN
XCOUT
D0–D3
D4/SIN
D5/SOUT
D6/SCK
D7/CNTR0
D8/INT0
D9/INT1
C/CNTR1
P00–P03
P10–P13
P20/AIN0–
P23/AIN3
P30/AIN4–
P33/AIN7
P40–P43
COM0–COM3
VLC3/SEG0
VLC2/SEG1
VLC1/SEG2
SEG3–SEG19
Usage condition
Internal oscillator is selected (CMCK and CRCK instructions are not executed.)
(Note 1)
Sub-clock input is selected for system clock (MR0=1). (Note 2)
Internal oscillator is selected (CMCK and CRCK instructions are not executed.)
(Note 1)
RC oscillator is selected (CRCK instruction is executed)
External clock input is selected for main clock (CMCK instruction is executed).
(Note 3)
Sub-clock input is selected for system clock (MR0=1). (Note 2)
Sub-clock is not used.
Sub-clock is not used.
N-channel open-drain is selected for the output structure. (Note 4)
SIN pin is not selected.
N-channel open-drain is selected for the output structure.
N-channel open-drain is selected for the output structure.
SCK pin is not selected.
N-channel open-drain is selected for the output structure.
CNTR0 input is not selected for timer 1 count source.
N-channel open-drain is selected for the output structure.
“0” is set to output latch.
“0” is set to output latch.
CNTR1 input is not selected for timer 3 count source.
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
The pull-up function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
The pull-up function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
SEG0 pin is selected.
SEG1 pin is selected.
SEG2 pin is selected.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock.
2:
When sub-clock (X
CIN
) input is selected (MR
0
= 1) for the system clock by setting “1” to bit 1 (MR
1
) of clock control register MR, main clock is stopped.
3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock.
4: Be sure to select the output structure of ports D0–D3 and P40–P43 and the pull-up function and key-on wakeup function of P00–P03 and P10–P13
with every one port. Set the corresponding bits of registers for each port.
5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open.
(Note when connecting to VSS and VDD)
● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
Rev.2.00 Jul 27, 2004 page 9 of 159
REJ03B0091-0200Z
4524 Group
PORT BLOCK DIAGRAMS
Port block diagram (1)
D
0
S
RQ
FR1
0
D
1
S
RQ
FR1
1
D
2
S
RQ
FR1
2
D
3
S
RQ
FR1
3
C/CNTR1
D
T
QR
W3
2
W6
1
S
C
P
i
n
s
t
r
u
c
t
i
o
n
R
C
P
i
n
s
t
r
u
c
t
i
o
n
S
R
W3
1
W3
0
Q
P
W
M
O
D
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
S
D
i
n
s
t
r
u
c
t
i
o
n
RD instruction
S
k
i
p
d
e
c
i
s
i
o
n
(
S
Z
D
i
n
s
t
r
u
c
t
i
o
n
)
CLD
instruction (
N
o
t
e
1
)
(Note 2)
C
l
o
c
k
(
i
n
p
u
t
)
f
o
r
t
i
m
e
r
3
e
v
e
n
t
c
o
u
n
t
Timer 3 underflow signal
T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
o
n
t
h
e
p
o
r
t
.
2
:
A
p
p
l
i
e
d
p
o
t
e
n
t
i
a
l
t
o
t
h
e
s
e
p
o
r
t
s
m
u
s
t
b
e
V
D
D
o
r
l
e
s
s
.
3
:
W
h
e
n
C
N
T
R
1
i
n
p
u
t
i
s
s
e
l
e
c
t
e
d
,
o
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
i
s
t
u
r
n
e
d
O
F
F
.
N
o
t
e
s
1
:
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
S
D
i
n
s
t
r
u
c
t
i
o
n
RD instruction
Skip decision
(SZD instruction)
C
L
D
i
n
s
t
r
u
c
t
i
o
n(
N
o
t
e
1
)
(Note 2)
R
e
g
i
s
t
e
r
Y Decoder
S
D
i
n
s
t
r
u
c
t
i
o
n
R
D
i
n
s
t
r
u
c
t
i
o
n
S
k
i
p
d
e
c
i
s
i
o
n
(
S
Z
D
i
n
s
t
r
u
c
t
i
o
n
)
CLD
instruction (Note 1)
(
N
o
t
e
2
)
Register Y Decoder
S
D
i
n
s
t
r
u
c
t
i
o
n
R
D
i
n
s
t
r
u
c
t
i
o
n
Skip decision
(SZD instruction)
C
L
D
i
n
s
t
r
u
c
t
i
o
n(
N
o
t
e
1
)
(Note 2)
(
N
o
t
e
1
)
(Note 2,
Note 3)
Rev.2.00 Jul 27, 2004 page 10 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (2)
S
RQ
FR2
1
J1
0
0
1
S
e
r
i
a
l
d
a
t
a
o
u
t
p
u
t
D
5
/S
OUT
D
4
/
S
I
N
F
R
2
0
S
e
r
i
a
l
d
a
t
a
i
n
p
u
t
J1
1
S
R
Q
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Notes 1:
R
e
g
i
s
t
e
r
YDecoder
S
D
i
n
s
t
r
u
c
t
i
o
n
RD instruction
S
k
i
p
d
e
c
i
s
i
o
n
(
S
Z
D
i
n
s
t
r
u
c
t
i
o
n
)
C
L
D
i
n
s
t
r
u
c
t
i
o
n(Note 1) (
N
o
t
e
2
)
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
S
D
i
n
s
t
r
u
c
t
i
o
n
R
D
i
n
s
t
r
u
c
t
i
o
n
S
k
i
p
d
e
c
i
s
i
o
n
(
S
Z
D
i
n
s
t
r
u
c
t
i
o
n
)
C
L
D
i
n
s
t
r
u
c
t
i
o
n(
N
o
t
e
1
)(
N
o
t
e
2
)
D
6
/S
CK
S
R
FR2
2
J1
3
J1
2
J
1
1
J
1
0
Q
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
o
u
t
p
u
t
)
f
o
r
s
e
r
i
a
l
d
a
t
a
t
r
a
n
s
f
e
r
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
S
D
i
n
s
t
r
u
c
t
i
o
n
R
D
i
n
s
t
r
u
c
t
i
o
n
Skip decision
(SZD instruction)
CLD
instruction (
N
o
t
e
1
)
(
N
o
t
e
2
)
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
i
n
p
u
t
)
f
o
r
s
e
r
i
a
l
d
a
t
a
t
r
a
n
s
f
e
r
Rev.2.00 Jul 27, 2004 page 11 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (3)
W11
W10
S
RQ
F
R
23
W60
0
1
D7/C
N
T
R
0
S
RQ
D8/INT0
S
RQ
D9/
I
N
T
1
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
S
D
i
n
s
t
r
u
c
t
i
o
n
R
D
i
n
s
t
r
u
c
t
i
o
n
S
k
i
p
d
e
c
i
s
i
o
n
(
S
Z
D
i
n
s
t
r
u
c
t
i
o
n
)
C
L
D
i
n
s
t
r
u
c
t
i
o
n(
N
o
t
e
1
)
(
N
o
t
e
2
)
C
l
o
c
k
(
i
n
p
u
t
)
f
o
r
t
i
m
e
r
1
e
v
e
n
t
c
o
u
n
t
U
n
d
e
r
f
l
o
w
s
i
g
n
a
l
d
i
v
i
d
e
d
b
y
2
o
f
t
i
m
e
r
1
o
r
t
i
m
e
r
2
(
N
o
t
e
1
)
(
N
o
t
e
2
)
R
e
g
i
s
t
e
r
YDecoder
S
D
i
n
s
t
r
u
c
t
i
o
n
RD instruction
CLD
instruction
(Note 3)
External 0 interrupt
circuit
E
x
t
e
r
n
a
l
0
i
n
t
e
r
r
u
p
t
K
e
y
-
o
n
w
a
k
e
u
p
Timer 1 count start synchronous circuit input
(
N
o
t
e
1
)
(
N
o
t
e
2
)
R
e
g
i
s
t
e
r
YD
e
c
o
d
e
r
SD instruction
R
D
i
n
s
t
r
u
c
t
i
o
n
CLD
instruction
(Note 3)
External 1 interrupt
circuit
External 1 interrupt
Key-on wakeup
T
i
m
e
r
3
c
o
u
n
t
s
t
a
r
t
s
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
i
n
p
u
t
T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
o
n
t
h
e
p
o
r
t
.
2
:
A
p
p
l
i
e
d
p
o
t
e
n
t
i
a
l
t
o
t
h
e
s
e
p
o
r
t
s
m
u
s
t
b
e
VD
D
o
r
l
e
s
s
.
3
:
A
s
f
o
r
d
e
t
a
i
l
s
,
r
e
f
e
r
t
o
t
h
e
d
e
s
c
r
i
p
t
i
o
n
o
f
e
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
c
i
r
c
u
i
t
.
Notes 1:
Rev.2.00 Jul 27, 2004 page 12 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (4)
P00
K00
O
P
0
A
i
n
s
t
r
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
A0
A0
D
K
e
y
-
o
n
w
a
k
e
u
p
(Note 2)
(
N
o
t
e
1
)
FR00
IAP0 instruction PU00
P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
T Q
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
P
01
K01
A1
A1
D
F
R
00
PU01
T Q
P
02
K02
A2
A2
D
F
R
01
PU02
T Q
P03
K03
A3
A3
D
FR01
PU03
T Q
O
P
0
A
i
n
s
t
r
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
(
N
o
t
e
2
)
(
N
o
t
e
1
)
IAP0 instruction P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“L” level
detection circuit
OP0A instruction
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
(
N
o
t
e
2
)
(
N
o
t
e
1
)
IAP0 instruction P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“L” level
detection circuit
O
P
0
A
i
n
s
t
r
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
(
N
o
t
e
2
)
(Note 1)
IAP0 instruction P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
o
n
t
h
e
p
o
r
t
.
2
:
A
p
p
l
i
e
d
p
o
t
e
n
t
i
a
l
t
o
t
h
e
s
e
p
o
r
t
s
m
u
s
t
b
e
VD
D
o
r
l
e
s
s
.
N
o
t
e
s
1
:
Rev.2.00 Jul 27, 2004 page 13 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (5)
P
10
K
10
O
P
1
A
i
n
s
t
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
A0
A0
D
K
e
y
-
o
n
w
a
k
e
u
p
(
N
o
t
e
2
)
(
N
o
t
e
1
)
F
R
02
I
A
P
1
i
n
s
t
r
u
c
t
i
o
nP
U
10
P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
T Q
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
P
11
K
11
A1
A1
D
F
R
02
P
U
11
T Q
P
12
K
12
A2
A2
D
F
R
03
P
U
12
T Q
P
13
K
13
A3
A3
D
F
R
03
P
U
13
T Q
O
P
1
A
i
n
s
t
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
I
A
P
1
i
n
s
t
r
u
c
t
i
o
nP
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
(
N
o
t
e
2
)
(
N
o
t
e
1
)
O
P
1
A
i
n
s
t
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
I
A
P
1
i
n
s
t
r
u
c
t
i
o
nP
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
(
N
o
t
e
2
)
(
N
o
t
e
1
)
O
P
1
A
i
n
s
t
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
K
e
y
-
o
n
w
a
k
e
u
p
I
A
P
1
i
n
s
t
r
u
c
t
i
o
nP
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
“
L
”
l
e
v
e
l
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
(
N
o
t
e
2
)
(
N
o
t
e
1
)
T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
o
n
t
h
e
p
o
r
t
.
2
:
A
p
p
l
i
e
d
p
o
t
e
n
t
i
a
l
t
o
t
h
e
s
e
p
o
r
t
s
m
u
s
t
b
e
VD
D
o
r
l
e
s
s
.
N
o
t
e
s
1
:
Rev.2.00 Jul 27, 2004 page 14 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (6)
P20/AIN0–P23/AIN3
D
e
c
o
d
e
r
O
P
2
A
i
n
s
t
r
u
c
t
i
o
n
R
e
g
i
s
t
e
r
A
Ai
Ai
D
A
n
a
l
o
g
i
n
p
u
t
T Q
0
1
Q2i
IAP2 instruction
Q
2i
Q
1
(
N
o
t
e
3
)(Note 3)
P30/AIN4–P33/AIN7
OP3A instruction
Ai
Ai
D
T Q
0
1
Q3i
I
A
P
3
i
n
s
t
r
u
c
t
i
o
n
Q3i
Q
1
P40–P43
O
P
4
A
i
n
s
t
r
u
c
t
i
o
n
Ai
Ai
D
FR3i
I
A
P
4
i
n
s
t
r
u
c
t
i
o
n
T Q
(Note 3) (
N
o
t
e
1
)
(Note 2)
(Note 3)
(
N
o
t
e
3
)(
N
o
t
e
1
)
(Note 2)
R
e
g
i
s
t
e
r
A
(Note 3)
D
e
c
o
d
e
r
A
n
a
l
o
g
i
n
p
u
t
Register A
(
N
o
t
e
3
)(Note 3) (
N
o
t
e
1
)
(Note 2)
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: i represents bits 0 to 3.
N
o
t
e
s
1
:
Rev.2.00 Jul 27, 2004 page 15 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (7)
(
VL
C
3/
VD
D)
VL
C
3/
S
E
G0
L23
(
VL
C2)
VL
C
2/
S
E
G1
L
22
(
VL
C
1)
VLC1/SEG2
L
21
L13
L
20
L12
L
11
VDD
R
e
s
e
t
s
i
g
n
a
l
E
P
O
F
+
P
O
F
2
i
n
s
t
r
u
c
t
i
o
n
(
C
o
n
t
i
n
u
o
u
s
e
x
e
c
u
t
i
o
n
)
(
N
o
t
e
1
)
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
C
o
n
n
e
c
t
i
n
g
t
o
•
w
h
e
n
S
E
G
i
s
s
e
l
e
c
t
e
d
.
LCD power supply
L
C
D
p
o
w
e
r
s
u
p
p
l
y
(
N
o
t
e
s
2
a
n
d
3
)
L
C
D
p
o
w
e
r
s
u
p
p
l
y
(Note 1)
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
C
o
n
n
e
c
t
i
n
g
t
o
•
w
h
e
n
S
E
G
i
s
s
e
l
e
c
t
e
d
.
L
C
D
p
o
w
e
r
s
u
p
p
l
y
L
C
D
p
o
w
e
r
s
u
p
p
l
y
(
N
o
t
e
2
)
LCD power supply
LCD power supply
LCD power
supply
LCD power
supply
LCD control
signal (Note 1)
(Note 2)
Connecting to •
when SEG is selected.
T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
o
n
t
h
e
p
o
r
t
.
2
:
A
p
p
l
i
e
d
p
o
t
e
n
t
i
a
l
w
h
e
n
V
L
C
i
s
s
e
l
e
c
t
e
d
m
u
s
t
b
e
a
s
f
o
l
l
o
w
s
;
•
VD
D
≥
VL
C
3
≥
VL
C
2
≥
VL
C
1
3
:
VL
C
3
=
VD
D
w
h
e
n
S
E
G
i
s
s
e
l
e
c
t
e
d
.
N
o
t
e
s
1
:
Rev.2.00 Jul 27, 2004 page 16 of 159
REJ03B0091-0200Z
4524 Group
Port block diagram (8)
COM0–COM3
Pch
S
E
G3–
S
E
G1
9
Pch
N
c
h
Nch
Pch
N
c
h
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
LCD power supply
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
L
C
D
p
o
w
e
r
s
u
p
p
l
y
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
LCD power supply
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
L
C
D
p
o
w
e
r
s
u
p
p
l
y
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
LCD power supply
L
C
D
c
o
n
t
r
o
l
s
i
g
n
a
l
Rev.2.00 Jul 27, 2004 page 17 of 159
REJ03B0091-0200Z
4524 Group
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-
bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, ex-
change, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig-
ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
Fig. 1 AMC instruction execution example
Fig. 2 RAR instruction execution example
Fig. 3 Registers A, B and register E
Fig. 4 TABP p instruction execution example
(
C
Y
)
(
M
(
D
P
)
)
(
A
)
Addition A
L
U
<Carry>
<
R
e
s
u
l
t
>
CY A3A2A1A0
A0C
YA3A2A1
<
R
o
t
a
t
i
o
n
>
R
A
R
i
n
s
t
r
u
c
t
i
o
n
<Set>
SC instruction <Clear>
RC instruction
A3A2A1A0B3B2B1B0
E7E6E5E4E3E2E1E0
A3A2A1A0
B3B2B1B0
TAB instruction
T
E
A
B
i
n
s
t
r
u
c
t
i
o
n
T
A
B
E
i
n
s
t
r
u
c
t
i
o
n
TBA instruction
R
e
g
i
s
t
e
r
BR
e
g
i
s
t
e
r
A
Register B Register A
Register E
S
p
e
c
i
f
y
i
n
g
a
d
d
r
e
s
s
TABP p instruction
p
6
p
5
p
4
p
3
p
2
p
1
p
0
P
C
H
DR
2
D
R
1
D
R
0
A
3
A
2
A
1
A
0
P
C
L
I
m
m
e
d
i
a
t
e
f
i
e
l
d
v
a
l
u
e
pT
h
e
c
o
n
t
e
n
t
s
o
f
r
e
g
i
s
t
e
r
D
ROM
840
Middle-order 4 bits
L
o
w
-
o
r
d
e
r
4
b
i
t
sRegister A (4)
Register B (4)
T
h
e
c
o
n
t
e
n
t
s
o
f
r
e
g
i
s
t
e
r
A
Rev.2.00 Jul 27, 2004 page 18 of 159
REJ03B0091-0200Z
4524 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an inter-
rupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be care-
ful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 lev-
els are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an inter-
rupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and regis-
ter B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table refer-
ence instruction.
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt oc-
curs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
Fig. 5 Stack registers (SKs) structure
Fig. 6 Example of operation at subroutine call
S
K0
S
K1
S
K2
S
K3
S
K4
S
K5
S
K6
S
K7
(
S
P
)
=
0
(
S
P
)
=
1
(
S
P
)
=
2
(
S
P
)
=
3
(
S
P
)
=
4
(
S
P
)
=
5
(
S
P
)
=
6
(
S
P
)
=
7
Program counter (PC)
E
x
e
c
u
t
i
n
g
R
T
i
n
s
t
r
u
c
t
i
o
n
Executing BM
instruction
Stack pointer (SP) points “7” at reset o
r
returning from RAM back-up mode. It points “0
”
by executing the first BM instruction, and th
e
contents of program counter is stored in SK0.
When the BM instruction is executed after eigh
t
stack registers are used ((SP) = 7), (SP) =
0
and the contents of SK0 is destroyed.
Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
(SP) ← 0
(SK
0
) ← 0001
16
(PC) ← SUB1
Main program
000216 NOP
A
d
d
r
e
s
s
0
0
0
01
6
N
O
P
000116 BM SUB1
Subroutine
S
U
B
1
:
NOP
RT
(
P
C
)
←
(
S
K
0
)
(
S
P
)
←
7
·
·
·
Note :
Rev.2.00 Jul 27, 2004 page 19 of 159
REJ03B0091-0200Z
4524 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer-
ence instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci-
fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg-
ister X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Fig. 7 Program counter (PC) structure
Fig. 8 Data pointer (DP) structure
Fig. 9 SD instruction execution example
p
5
p
4
p
3
p
2
p
1
p
0
a
6
a
5
a
4
a
3
a
2
a
1
a
0
P
r
o
g
r
a
m
c
o
u
n
t
e
r
P
C
H
S
p
e
c
i
f
y
i
n
g
p
a
g
eP
C
L
S
p
e
c
i
f
y
i
n
g
a
d
d
r
e
s
s
p
6
Z
1
Z
0
X
3
X
2
X
1
X
0
Y
3
Y
2
Y
1
Y
0
D
a
t
a
p
o
i
n
t
e
r
(
D
P
)
Register Z (2)
R
e
g
i
s
t
e
r
X
(
4
)
Register Y (4) S
p
e
c
i
f
y
i
n
g
R
A
M
d
i
g
i
t
S
p
e
c
i
f
y
i
n
g
R
A
M
f
i
l
e
Specifying RAM file group
001 1
Set
S
p
e
c
i
f
y
i
n
g
b
i
t
p
o
s
i
t
i
o
n
Port D output latch
Register Y (4)
D
2
D
3
D
1
D
0
0
Rev.2.00 Jul 27, 2004 page 20 of 159
REJ03B0091-0200Z
4524 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Fig-
ure 10 shows the ROM map of M34524ED.
Table 1 ROM size and pages
Part number
M34524M8
M34524MC
M34524ED
ROM (PROM) size
(✕ 10 bits)
8192 words
12288 words
16384 words
Pages
64 (0 to 63)
96 (0 to 95)
128 (0 to 127)
Note: Data in pages 64 to 127 can be referred with the TABP p in-
struction after the SBK instruction is executed.
Data in pages 0 to 63 can be referred with the TABP p in-
struction after the RBK instruction is executed.
A part of page 1 (addresses 008016 to 00FF16) is reserved for in-
terrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the in-
struction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for sub-
routine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM in-
struction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data ar-
eas with the TABP p instruction.
Fig. 10 ROM map of M34524ED
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
9087654321
I
n
t
e
r
r
u
p
t
a
d
d
r
e
s
s
p
a
g
e
0
0
0
01
6
0
0
8
01
6
0
1
7F1
6S
u
b
r
o
u
t
i
n
e
s
p
e
c
i
a
l
p
a
g
e
0
0
7F1
6
0
0F
F1
6
0
1
0
01
6
3F
F
F1
6
0
1
8
01
6
P
a
g
e
1
P
a
g
e
2
P
a
g
e
0
P
a
g
e
3
P
a
g
e
1
2
7
9087654321
External 0 interrupt address0
0
8
0
1
6
0082
16
0
0
8
4
1
6
Timer 1 interrupt address
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
a
d
d
r
e
s
s
0
0
8
6
1
6
0
0
8
8
1
6
0
0
8
A
1
6
008C
16
0
0
8
E
1
6
00FF
16
A/D interrupt address
External 1 interrupt address
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
a
d
d
r
e
s
s
Timer 5 interrupt address
T
i
m
e
r
4
,
S
e
r
i
a
l
I
/
O
i
n
t
e
r
r
u
p
t
a
d
d
r
e
s
s
Rev.2.00 Jul 27, 2004 page 21 of 159
REJ03B0091-0200Z
4524 Group
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM (also, set a value after system returns from RAM back-up).
RAM includes the area for LCD.
When writing “1” to a bit corresponding to displayed segment, the
segment is turned on.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Fig. 12 RAM map
Table 2 RAM size
Part number
M34524M8
M34524MC
M34524ED
RAM size
512 words ✕ 4 bits (2048 bits)
512 words ✕ 4 bits (2048 bits)
512 words ✕ 4 bits (2048 bits)
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Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Rev.2.00 Jul 27, 2004 page 22 of 159
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4524 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every inter-
rupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the cor-
responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set to “1” when the activated condi-
tion is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag retains
set until it is cleared to “0” by the interrupt occurrence or the skip
instruction.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set to “1” when the inter-
rupt disable state is released, the interrupt priority level is as
follows shown in Table 3.
Table 3 Interrupt sources
Activated condition
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Timer 5 underflow
Completion of
A/D conversion
Timer 4 underflow
or completion of
serial I/O transmit/
receive
Priority
level
1
2
3
4
5
6
7
8
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 5 interrupt
A/D interrupt
Timer 4 interrupt or
Serial I/O interrupt
(Note)
Interrupt
request flag
EXF0
EXF1
T1F
T2F
T3F
T5F
ADF
T4F
SIOF
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 5 interrupt
A/D interrupt
Timer 4 interrupt
Serial I/O interrupt
Table 5 Interrupt enable bit function
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
Interrupt enable bit
1
0
Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction Skip instruction
SNZ0
SNZ1
SNZT1
SNZT2
SNZT3
SNZT5
SNZAD
SNZT4
SNZSI
Interrupt
nable bit
V10
V11
V12
V13
V20
V21
V22
V23
V23
Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4,
serial I/O interrupt source selection bit (I30).
Rev.2.00 Jul 27, 2004 page 23 of 159
REJ03B0091-0200Z
4524 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Fig. 13 Program example of interrupt processing
• Program counter (PC)
............................................................... Each interrupt address
• Stack register (SK)
....................................................................................................
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source)................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
The address of main routine to be
executed when returning
Fig. 15 Interrupt system diagram
Fig. 14 Internal state when interrupt occurs
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Rev.2.00 Jul 27, 2004 page 24 of 159
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4524 Group
(6) Interrupt control registers
•Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
•Interrupt control register V2
The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable
bit is assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the ma-
chine cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles when the interrupt conditions are
satisfied on execution of two-cycle instructions or three-cycle in-
structions. (Refer to Figure 16).
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 2)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 2)
V13
V12
V11
V10
V23
V22
V21
V20
Timer 4, serial I/O interrupt enable bit (Note 3)
A/D interrupt enable bit
Timer 5 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2 at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
0
1
0
1
0
1
0
1
at power down : 00002
at reset : 00002R/W
TAV1/TV1A
R/W
TAV2/TV2A
I30Timer 4, serial I/O interrupt source selection
bit
Interrupt control register I3 R/W
TAI3/TI3A
at power down : state retainedat reset : 02
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
0
1
•Interrupt control register I3
The timer 4, serial I/O interrupt source selection bit is assigned to
register I3. Set the contents of this register through register A
with the TI3A instruction. The TAI3 instruction can be used to
transfer the contents of register I3 to register A.
Rev.2.00 Jul 27, 2004 page 25 of 159
REJ03B0091-0200Z
4524 Group
Fig. 16 Interrupt sequence
T1F,T2F,T3F,T4F
T5F,ADF,SIOF
INT0,INT1
EXF0,EXF1
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● When an interrupt request flag is set after its interrupt is enabled (Note 1)
System clock
(STCK)
The program starts
from the interrupt
address.
Interrupt enabled state
1 machine cycle
EI instruction execution cycle
Interrupt enable
flag (INTE)
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
External
interrupt
Timer 1,
Timer 2,
Timer 3,
Timer 4,
Timer 5,
A/D and
Serial I/O
interrupts
Interrupt activated
condition is satisfied.
Notes 1: The address to be executed when returning to the main routine is stacked to the last machine cycle.
2: The cycles are as follows according to the executed instruction at the time when each interrupt activated condition is satisfied.
On execution of one-cycle instruction: Interrupt occurs after 2 machine cycles.
On execution of two-cycle instruction: Interrupt occurs after 3 machine cycles.
On execution of three-cycle instruction: Interrupt occurs after 3 machine cycles.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
Rev.2.00 Jul 27, 2004 page 26 of 159
REJ03B0091-0200Z
4524 Group
Table 7 External interrupt activated conditions
Name
External 0 interrupt
External 1 interrupt
Input pin
D8/INT0
D9/INT1
Activated condition
When the next waveform is input to D8/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
When the next waveform is input to D9/INT1 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
I21
I22
Fig. 17 External interrupt circuit structure
EXTERNAL INTERRUPTS
The 4524 Group has the external 0 interrupt and external 1 inter-
rupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
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Level detection circuit
Edge detection circuit
Skip decision
(SNZI1 instruction)
Both edges
detection circuit
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EXF1
I2
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Key-on wakeup
0
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EXF0 External 0
interrupt
I1
1
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0
K2
0
Timer 1 count start
synchronous circuit
I1
3
(Note 1)
Level detection circuit
Edge detection circuit
0
1
K2
1
Skip decision
(SNZI0 instruction)
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(Note 3)
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Rev.2.00 Jul 27, 2004 page 27 of 159
REJ03B0091-0200Z
4524 Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to D8/INT0 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to D8/INT0 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the in-
put enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the D8/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to D9/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 1 interrupt activated condition
External 1 interrupt activated condition is satisfied when a valid
waveform is input to D9/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the in-
put enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I2.
➂ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➄ Set both the external 1 interrupt enable bit (V11) and the INTE
flag to “1.”
The external 1 interrupt is now enabled. Now when a valid wave-
form is input to the D9/INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
Rev.2.00 Jul 27, 2004 page 28 of 159
REJ03B0091-0200Z
4524 Group
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
Table 8 External interrupt control register
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 inter-
rupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set.
I13
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
Interrupt control register I1 R/W
TAI1/TI1A
at power down : state retained
at reset : 00002
INT0 pin input disabled
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
0
1
0
1
0
1
0
1
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
Interrupt control register I2 R/W
TAI2/TI2A
at power down : state retained
at reset : 00002
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
0
1
0
1
0
1
0
1
Rev.2.00 Jul 27, 2004 page 29 of 159
REJ03B0091-0200Z
4524 Group
(4) Notes on External 0 interrupts
➀ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of reg-
ister I1 in software, be careful about the following notes.
• Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
18➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18➂).
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid...........➀
LA 8 ; (1✕✕✕2)
TI1A ; Control of INT0 pin input is changed
NOP ........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the power down function
is selected and the input of INT0 pin is disabled, be careful about
the following notes.
• When the input of INT0 pin is disabled, invalidate the key-on
wakeup function of INT0 pin (register K20 = “0”) before system
goes into the power down mode. (refer to Figure 19➀).
•••
•••
LA 0 ; (✕✕✕02)
TK2A ; INT0 key-on wakeup invalid ........... ➀
DI
EPOF
POF2 ; RAM back-up
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
•••
•••
➂ Note on bit 2 of register I1
When the interrupt valid waveform of the D8/INT0 pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
• Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
20➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20➂).
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid...........➀
LA 12 ; (✕1✕✕2)
TI1A ; Interrupt valid waveform is changed
NOP ........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 20 External 0 interrupt program example-3
•••
•••
Rev.2.00 Jul 27, 2004 page 30 of 159
REJ03B0091-0200Z
4524 Group
(5) Notes on External 1 interrupts
➀ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in software, be careful about the following notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
21➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 21➂).
LA 4 ; (✕✕0✕2)
TV1A ; The SNZ1 instruction is valid...........➀
LA 8 ; (1✕✕✕2)
TI2A ; Control of INT1 pin input is changed
NOP ........................................................... ➁
SNZ1 ; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 21 External 1 interrupt program example-1
➁ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared, the power down function
is selected and the input of INT1 pin is disabled, be careful about
the following notes.
• When the input of INT1 pin is disabled, invalidate the key-on
wakeup function of INT1 pin (register K22 = “0”) before system
goes into the power down mode. (refer to Figure 22➀).
•••
•••
LA 0 ; (✕0✕✕2)
TK2A ; INT1 key-on wakeup invalid ........... ➀
DI
EPOF
POF2 ; RAM back-up
✕ : these bits are not used here.
Fig. 22 External 1 interrupt program example-2
•••
•••
➂ Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the fol-
lowing notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
23➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 23➂).
LA 4 ; (✕✕0✕2)
TV1A ; The SNZ1 instruction is valid...........➀
LA 12 ; (✕1✕✕2)
TI2A ; Interrupt valid waveform is changed
NOP ........................................................... ➁
SNZ1 ; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 23 External 1 interrupt program example-3
•••
•••
Rev.2.00 Jul 27, 2004 page 31 of 159
REJ03B0091-0200Z
4524 Group
TIMERS
The 4524 Group has the following timers.
•Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set-
ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload reg-
ister, and count continues (auto-reload function).
•Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
Fig. 24 Auto-reload function
The 4524 Group timer consists of the following circuits.
•Prescaler : 8-bit programmable timer
•Timer 1 : 8-bit programmable timer
•Timer 2 : 8-bit programmable timer
•Timer 3 : 8-bit programmable timer
•Timer 4 : 8-bit programmable timer
•Timer 5 : 16-bit fixed dividing frequency timer
•Timer LC : 4-bit programmable timer
•Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the
timer control registers PA, W1 to W6. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
FF
16
n
00
16
n : Counter initia l value
C
o
u
n
t
s
t
a
r
t
sR
e
l
o
a
dReload
1
s
t
u
n
d
e
r
f
l
o
w 2
n
d
u
n
d
e
r
f
l
o
w
n
+
1
c
o
u
n
t
n
+
1
c
o
u
n
t
T
i
m
e
An interrupt occurs or
a skip instruction is executed.
T
i
m
e
r
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
f
l
a
g
T
h
e
c
o
n
t
e
n
t
s
o
f
c
o
u
n
t
e
r
“
1
”
“
0
”
Rev.2.00 Jul 27, 2004 page 32 of 159
REJ03B0091-0200Z
4524 Group
Count source
• Instruction clock (INSTCK)
• Instruction clock (INSTCK)
• Prescaler output (ORCLK)
• Timer 5 underflow
(T5UDF)
• CNTR0 input
• System clock (STCK)
• Prescaler output (ORCLK)
• Timer 1 underflow
(T1UDF)
• PWM output (PWMOUT)
• PWM output (PWMOUT)
• Prescaler output (ORCLK)
• Timer 2 underflow
(T2UDF)
• CNTR1 input
• XIN input
• Prescaler output (ORCLK)
• XCIN input
• Bit 4 of timer 5
• Prescaler output (ORCLK)
• Instruction clock (INSTCK)
Structure
8-bit programmable
binary down counter
8-bit programmable
binary down counter
(link to INT0 input)
8-bit programmable
binary down counter
8-bit programmable
binary down counter
(link to INT1 input)
8-bit programmable
binary down counter
(PWM output function)
16-bit fixed dividing
frequency
4-bit programmable
binary down counter
16-bit fixed dividing
frequency
Circuit
Prescaler
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer LC
Watchdog
timer
Use of output signal
• Timer 1, 2, 3, 4 and LC count sources
• Timer 2 count source
• CNTR0 output
• Timer 1 interrupt
• Timer 3 count source
• CNTR0 output
• Timer 2 interrupt
• CNTR1 output control
• Timer 3 interrupt
• Timer 2, 3 count source
• CNTR1 output
• Timer 4 interrupt
• Timer 1, LC count source
• Timer 5 interrupt
• LCD clock
• System reset (count twice)
• WDF flag decision
Frequency
dividing ratio
1 to 256
1 to 256
1 to 256
1 to 256
1 to 256
8192
16384
32768
65536
1 to 16
65534
Control
register
PA
W1
W2
W2
W3
W4
W5
W6
Table 9 Function related timers
Rev.2.00 Jul 27, 2004 page 33 of 159
REJ03B0091-0200Z
4524 Group
Fig. 25 Timer structure (1)
S
T
C
K
1
W2
2
0
W
2
1
,
W
2
0
1
0
1
1
01
0
0
O
R
C
L
K
T
1
U
D
F
P
W
M
O
U
T
T2F
(TAB2) (TAB2)
(T2AB)
(
T
2
A
B
)(T2AB)
T
1
U
D
F
1
W2
3
01/2
T
2
U
D
F
1/2
1
W
6
0
0P
o
r
t
D
7
o
u
t
p
u
t
D7/CNTR0
Division circuit
Divided by 8
Divided by4
Divided by 2
S
y
s
t
e
m
c
l
o
c
k
(
S
T
C
K
)
XC
I
N
I
n
s
t
r
u
c
t
i
o
n
c
l
o
c
k
(
I
N
S
T
C
K
)
M
u
l
t
i
-
p
l
e
x
e
r
(
C
M
C
K
/
C
R
C
K
)
Q
u
a
r
t
z
-
c
r
y
s
t
a
l
o
s
c
i
l
l
a
t
i
o
n
1
MR
0
0
ORCLK
Reload register RPS (8)
Prescaler (8)
R
e
g
i
s
t
e
r
B R
e
g
i
s
t
e
r
A
(TABPS) (TABPS)
(
T
P
S
A
B
)
1
P
A
0
0
MR
3
, MR
2
0
1
0
0
10
1
1
I
N
S
T
C
K
0
1
Q
R
S
0
1
I
1
2
0
1
D8/
I
N
T
0
W
1
3
T
1
U
D
F
I1
0
I
1
3
I1
1
I1
0
1
W1
2
0
W1
1
, W1
0
10
1
1
01
00
ORCLK
T5UDF
D7/CNTR0
T
1
F
(TAB1)(TAB1) (T1AB)
(T1AB) (T1AB)
(TR1AB)
(TPSAB)
(
T
P
S
A
B
)
P
W
M
O
U
T
0
1
Q
R
S
0
1
I
2
2
0
1
D9/
I
N
T
1
W
3
3
T
3
U
D
F
I2
0
I2
3
I2
1
I2
0
1
W3
2
0
W3
1
, W3
0
10
11
01
0
0
O
R
C
L
K
T
2
U
D
F
C/CNTR1
T
3
F
(TAB3)(TAB3) (T3AB)
(T3AB) (T3AB)
(
T
R
3
A
B
)
T
5
U
D
F
:
P
W
M
O
U
T
:T
i
m
e
r
5
u
n
d
e
r
f
l
o
w
s
i
g
n
a
l
(
f
r
o
m
t
i
m
e
r
5
)
P
W
M
o
u
t
p
u
t
s
i
g
n
a
l
(
f
r
o
m
t
i
m
e
r
4
o
u
t
p
u
t
u
n
i
t
)
(Note 1)
(Note 2)
(Note 4)
(
N
o
t
e
4
)
(
N
o
t
e
3
)
(Note 4)
On-chip oscillator
XIN C
e
r
a
m
i
c
r
e
s
o
n
a
n
c
e
(
C
M
C
K
)
R
C
o
s
c
i
l
l
a
t
i
o
n
(CRCK)
Timer 1 (8)
Timer 1
interrupt
Reload register R1 (8)
Register B R
e
g
i
s
t
e
r
AT
i
m
e
r
1
u
n
d
e
r
f
l
o
w
s
i
g
n
a
l
(
T
1
U
D
F
)
O
ne-s
id
e
d
e
d
ge
detection circui t
B
ot
h
e
d
ges
detection circui t
F
a
l
l
i
n
g
R
i
s
i
n
g
(
N
o
t
e
4
)
O
n
e
-
s
i
d
e
d
e
d
g
e
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
B
ot
h
e
d
ges
detection circui t
Falling
R
i
s
i
n
g
Timer 2
interrupt
T
i
m
e
r
2
u
n
d
e
r
f
l
o
w
s
i
g
n
a
l
(
T
2
U
D
F
)
Timer 2 (8)
R
e
l
o
a
d
r
e
g
i
s
t
e
r
R
2
(
8
)
Register B Register A
Timer 3
interrupt
Timer 3 underflow signal (T3UDF)
T
i
m
e
r
3
(
8
)
Reload register R3 (8)
Register B Register A
I
n
t
e
r
n
a
l
c
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
(
d
i
v
i
d
e
d
b
y
3
)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 1: When CMCK instruction is executed, ceramic resonance is selected.
When CRCK instruction is executed, RC oscillation is selected.
When any instructions are not executed, on-chip oscillator clock
(internal oscillation) is selected.
2: Timer 1 count start synchronous circuit is set
by the valid edge of D
8
/INT0 pin selected by bits 1 (I1
1
) and 2 (I1
2
)
of register I1.
3: Timer 3 count start synchronous circuit is set
by the valid edge of D
9
/INT1 pin selected by bits 1 (I2
1
) and 2 (I2
2
)
of register I2.
4: Count source is stopped by clearing to “0.”
Rev.2.00 Jul 27, 2004 page 34 of 159
REJ03B0091-0200Z
4524 Group
Fig. 26 Timer structure (2)
R
e
g
i
s
t
e
r
A
R
e
l
o
a
d
c
o
n
t
r
o
l
c
i
r
c
u
i
t
(
T
A
B
4
)
W4
3
Q
R
T
(
T
4
A
B
)
Timer 4 (8)
R
e
g
i
s
t
e
r
B
R
e
l
o
a
d
r
e
g
i
s
t
e
r
R
4
H
(
8
)
(
T
A
B
4
)
(
T
4
A
B
)
P
W
M
O
D
(T4R4L)
T
4
F
O
R
C
L
K
XI
N1
W4
1
0
Timer 4,
Serial I/O
interrupt
1
W4
0
0
(
T
4
H
A
B
)
T
3
U
D
F
P
W
M
O
D
P
o
r
t
C
o
u
t
p
u
t
Q
C
/
C
N
T
R
1
W
3
1
W
3
0
R
D
T
W3
2
W
6
1
1
W5
2
0T
i
m
e
r
5
(
1
6
)
1 - - 4 - - - - - - - -13 14 15 16 W5
1
, W5
0
01
00
10
11
T5F T
i
m
e
r
5
i
n
t
e
r
r
u
p
t
Timer 5 underflow signal (T5UDF)
XC
I
N
1
W
6
3
01
/
2L
C
D
c
l
o
c
k
Reload register RLC (4)
Timer LC (4)
Register A
(TLCA) (
T
L
C
A
)
1
W6
2
0
ORCLK
Watchdog
reset signal
W
a
t
c
h
d
o
g
t
i
m
e
r
(
1
6
)
QS
Q
T
D
W
D
F
2
Reset signal
R
Q
R
SWEF
Reset signal
R
WDF1
W
R
S
T
i
n
s
t
r
u
c
t
i
o
n
I
N
S
T
C
K
+
D
W
D
T
i
n
s
t
r
u
c
t
i
o
n
W
R
S
T
i
n
s
t
r
u
c
t
i
o
n
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
6
INSTCK :
ORCLK : Instruction clock (system clock divided by 3)
Prescaler output (instruction clock divided by 1 to 256)
(
N
o
t
e
4
)
(
N
o
t
e
5
)
PWMOUT
(To timer 2 and timer 3)
0
W
4
2
1
“H” interval
expansion
(Note 4)
(
N
o
t
e
6
)
(Note 4)
(
N
o
t
e
8
)
(Note 7)
1
/
2
R
e
g
i
s
t
e
r
AR
e
g
i
s
t
e
r
B
Reload register R4L (8)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 4: Count source is stopped by clearing to “0.”
5: XIN cannot be used as count source when bit 1 (MR1) of register MR
is set to “1” and f(XIN) oscillation is stopped.
6: This timer is initialized (initial value = FFFF16) by stop of count
source (W52 = “0”).
7: Flag WDF1 is cleared to “0” and the next instruction is skipped when
the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction
is executed while flag WDF1 = “0”.
8: Flag WEF is cleared to “0” and watchdog timer reset does not occur
when the DWDT instruction and WRST instruction are executed
continuously.
9: The WEF flag is set to “1” at system reset or RAM back-up mode.
1
I3
0
0
S
I
O
F
(
F
r
o
m
S
e
r
i
a
l
I
/
O
)
(
N
o
t
e
9
)
Rev.2.00 Jul 27, 2004 page 35 of 159
REJ03B0091-0200Z
4524 Group
W21
0
0
1
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating Count source
System clock (STCK)
Prescaler output (ORCLK)
Timer 1 underflow signal (T1UDF)
PWM signal (PWMOUT)
CNTR0 output control bit
Timer 2 control bit
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
Timer control register W2 at power down : state retained
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
W23
W22
W21
W20
0
1Stop (state initialized)
Operating
Prescaler control bit
Timer control register PA W
TPAA
at power down : 02at reset : 02
PA0
W11
0
0
1
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
Timer 5 underflow signal (T5UDF)
CNTR0 input
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 1 control bit
Timer 1 count source selection bits
0
1
0
1
W10
0
1
0
1
Timer control register W1 R/W
TAW1/TW1A
at power down : state retainedat reset : 00002
W13
W12
W11
W10
W31
0
0
1
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Timer 3 count auto-stop circuit selection
bit (Note 3)
Timer 3 control bit
Timer 3 count source selection bits
(Note 4)
0
1
0
1
W30
0
1
0
1
Timer control register W3 at power down : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW2/TW2A
R/W
TAW3/TW3A
Table 10 Timer related registers
Rev.2.00 Jul 27, 2004 page 36 of 159
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4524 Group
Stop (state retained)
Operating
Bit 4 (T54) of timer 5
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D7(I/O)/CNTR0 input
CNTR0 input/output/D7 (input)
Timer LC control bit
Timer LC count source selection bit
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
0
1
0
1
0
1
0
1
Timer control register W6 at power down : state retained
at reset : 00002
W63
W62
W61
W60
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
CNTR1 output control bit
PWM signal
“H” interval expansion function control bit
Timer 4 control bit
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
W43
W42
W41
W40
W51
0
0
1
1
Not used
Timer 5 control bit
Timer 5 count value selection bits
0
1
0
1
W50
0
1
0
1
Timer control register W5 at power down : state retained
at reset : 00002
W53
W52
W51
W50
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
This bit has no function, but read/write is enabled.
Stop (state initialized)
Operating Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
R/W
TAW4/TW4A
Timer control register W4 at power down : 00002
at reset : 00002
R/W
TAW5/TW5A
R/W
TAW6/TW6A
Rev.2.00 Jul 27, 2004 page 37 of 159
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4524 Group
(1) Timer control registers
•Timer control register PA
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA instruc-
tion.
•Timer control register W1
Register W1 controls the selection of timer 1 count auto-stop cir-
cuit, and the count operation and count source of timer 1. Set the
contents of this register through register A with the TW1A instruc-
tion. The TAW1 instruction can be used to transfer the contents
of register W1 to register A.
•Timer control register W2
Register W2 controls the selection of CNTR0 output, and the
count operation and count source of timer 2. Set the contents of
this register through register A with the TW2A instruction. The
TAW2 instruction can be used to transfer the contents of register
W2 to register A.
•Timer control register W3
Register W3 controls the selection of timer 3 count auto-stop cir-
cuit, and the count operation and count source of timer 3. Set the
contents of this register through register A with the TW3A instruc-
tion. The TAW3 instruction can be used to transfer the contents
of register W3 to register A.
•Timer control register W4
Register W4 controls the CNTR1 output, the expansion of “H” in-
terval of PWM output, and the count operation and count source
of timer 4. Set the contents of this register through register A with
the TW4A instruction. The TAW4 instruction can be used to trans-
fer the contents of register W4 to register A.
•Timer control register W5
Register W5 controls the count operation and count source of
timer 5. Set the contents of this register through register A with
the TW5A instruction. The TAW5 instruction can be used to trans-
fer the contents of register W5 to register A.
•Timer control register W6
Register W6 controls the operation and count source of timer LC,
the selection of CNTR1 output auto-control circuit and the D7/
CNTR0 pin function. Set the contents of this register through reg-
ister A with the TW6A instruction. The TAW6 instruction can be
used to transfer the contents of register W6 to register A..
(2) Prescaler (interrupt function)
Prescaler is an 8-bit binary down counter with the prescaler reload
register PRS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction
to read or set prescaler data.
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1, 2,
3, 4 and LC count sources.
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload reg-
ister (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to re-
load register (R1) with the TR1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload regis-
ter R1 while timer 1 is operating, avoid a timing when timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1
➁ set count source by bits 0 and 1 of register W1, and
➂ set the bit 2 of register W1 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
INT0 pin input can be used as the start trigger for timer 1 count op-
eration by setting the bit 0 of register I1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 3 of register W1 to “1.”
Timer 1 underflow signal divided by 2 can be output from CNTR0
pin by clearing bit 3 of register W2 to “0” and setting bit 0 of regis-
ter W6 to “1”.
Rev.2.00 Jul 27, 2004 page 38 of 159
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(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload reg-
ister (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction. Data can be read from
timer 2 with the TAB2 instruction. Stop counting and then execute
the T2AB or TAB2 instruction to read or set timer 2 data.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 2 of register W2 to “1.”
When a value set in reload register R2 is n, timer 2 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Timer 2 underflow signal divided by 2 can be output from CNTR0
pin by setting bit 3 of register W2 to “1” and setting bit 0 of register
W6 to “1”.
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload reg-
ister (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to re-
load register (R3) with the TR3AB instruction. Data can be read
from timer 3 with the TAB3 instruction.
Stop counting and then execute the T3AB or TAB3 instruction to
read or set timer 3 data.
When executing the TR3AB instruction to set data to reload regis-
ter R3 while timer 3 is operating, avoid a timing when timer 3
underflows.
Timer 3 starts counting after the following process;
➀ set data in timer 3
➁ set count source by bits 0 and 1 of register W3, and
➂ set the bit 2 of register W3 to “1.”
When a value set in reload register R3 is n, timer 3 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
INT1 pin input can be used as the start trigger for timer 3 count op-
eration by setting the bit 0 of register I2 to “1.”
Also, in this time, the auto-stop function by timer 3 underflow can
be performed by setting the bit 3 of register W3 to “1.”
(6) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with two timer 4 reload reg-
isters (R4L, R4H). Data can be set simultaneously in timer 4 and
the reload register R4L with the T4AB instruction. Data can be set
in the reload register R4H with the T4HAB instruction. The contents
of reload register R4L set with the T4AB instruction can be set to
timer 4 again with the T4R4L instruction. Data can be read from
timer 4 with the TAB4 instruction.
Stop counting and then execute the T4AB or TAB4 instruction to
read or set timer 4 data.
When executing the T4HAB instruction to set data to reload regis-
ter R4H while timer 4 is operating, avoid a timing when timer 4
underflows.
Timer 4 starts counting after the following process;
➀ set data in timer 4
➁ set count source by bit 0 of register W4, and
➂ set the bit 1 of register W4 to “1.”
When a value set in reload register R4L is n, timer 4 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4L, and count continues (auto-reload function).
When bit 3 of register W4 is set to “1”, timer 4 reloads data from re-
load register R4L and R4H alternately each underflow.
Timer 4 generates the PWM signal (PWMOUT) of the “L” interval
set as reload register R4L, and the “H” interval set as reload regis-
ter R4H. The PWM signal (PWMOUT) is output from CNTR1 pin.
When bit 2 of register W4 is set to “1” at this time, the interval
(PWM signal “H” interval) set to reload register R4H for the counter
of timer 4 is extended for a half period of count source.
In this case, when a value set in reload register R4H is n, timer 4
divides the count source signal by n + 1.5 (n = 1 to 255).
When this function is used, set “1” or more to reload register R4H.
When bit 1 of register W6 is set to “1”, the PWM signal output to
CNTR1 pin is switched to valid/invalid each timer 3 underflow.
However, when timer 3 is stopped (bit 2 of register W3 is cleared to
“0”), this function is canceled.
Even when bit 1 of a register W4 is cleared to “0” in the “H” interval
of PWM signal, timer 4 does not stop until it next timer 4 underflow.
When clearing bit 1 of register W4 to “0” to stop timer 4, avoid a
timing when timer 4 underflows.
Rev.2.00 Jul 27, 2004 page 39 of 159
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4524 Group
(7) Timer 5 (interrupt function)
Timer 5 is a 16-bit binary down counter.
Timer 5 starts counting after the following process;
➀ set count value by bits 0 and 1 of register W5, and
➁ set the bit 2 of register W5 to “1.”
Count source for timer 5 is the sub-clock input (XCIN).
Once count is started, when timer 5 underflows (the set count
value is counted), the timer 5 interrupt request flag (T5F) is set to
“1,” and count continues.
Bit 4 of timer 5 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W5 is cleared to “0”, timer 5 is initialized to
“FFFF16” and count is stopped.
Timer 5 can be used as the counter for clock because it can be op-
erated at clock operating mode (POF instruction execution). When
timer 5 underflow occurs at clock operating mode, system returns
from the power down state.
(8) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload
register (RLC). Data can be set simultaneously in timer LC and the
reload register (RLC) with the TLCA instruction. Data cannot be
read from timer LC. Stop counting and then execute the TLCA in-
struction to set timer LC data.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 2 of register W6, and
➂ set the bit 3 of register W6 to “1.”
When a value set in reload register RLC is n, timer LC divides the
count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new data
is loaded from reload register RLC, and count continues (auto-re-
load function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
(9) Timer input/output pin
(D7/CNTR0 pin, C/CNTR1 pin)
CNTR0 pin is used to input the timer 1 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
CNTR1 pin is used to input the timer 3 count source and output the
PWM signal generated by timer 4. When the PWM signal is output
from C/CNTR1 pin, set “0” to the output latch of port C.
The D7/CNTR0 pin function can be selected by bit 0 of register W6.
The selection of CNTR1 output signal can be controlled by bit 3 of
register W4.
When the CNTR0 input is selected for timer 1 count source, timer
1 counts the rising waveform of CNTR0 input.
When the CNTR1 input is selected for timer 3 count source, timer
3 counts the rising waveform of CNTR1 input. Also, when the
CNTR1 input is selected, the output of port C is invalid (high-im-
pedance state).
(10) Timer interrupt request flags
(T1F, T2F, T3F, T4F, T5F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
Rev.2.00 Jul 27, 2004 page 40 of 159
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4524 Group
(11) Count start synchronization circuit (timer 1,
timer 3)
Timer 1 and timer 3 have the count start synchronous circuit which
synchronizes the input of INT0 pin and INT1 pin, and can start the
timer count operation.
Timer 1 count start synchronous circuit function is selected by set-
ting the bit 0 of register I1 to “1” and the control by INT0 pin input
can be performed.
Timer 3 count start synchronous circuit function is selected by set-
ting the bit 0 of register I2 to “1” and the control by INT1 pin input
can be performed.
When timer 1 or timer 3 count start synchronous circuit is used, the
count start synchronous circuit is set, the count source is input to
each timer by inputting valid waveform to INT0 pin or INT1 pin.
The valid waveform of INT0 pin or INT1 pin to set the count start
synchronous circuit is the same as the external interrupt activated
condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 or I20 to “0” or reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1 or
timer 3 underflow.
(12) Count auto-stop circuit (timer 1, timer 3)
Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start syn-
chronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W1
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
Timer 3 has the count auto-stop circuit which is used to stop timer
3 automatically by the timer 3 underflow when the count start syn-
chronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W3
to “1”. It is cleared by the timer 3 underflow and the count source to
timer 3 is stopped.
This function is valid only when the timer 3 count start synchronous
circuit is selected.
(13) Precautions
Note the following for the use of timers.
•Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
•Timer count source
Stop timer 1, 2, 3, 4 and LC counting to change its count source.
•Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
•Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the data
write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its
data.
•Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or re-
load regiser R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
•Timer 4
Avoid a timing when timer 4 underflows to stop timer 4.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
•Timer 5
Stop timer 5 counting to change its count source.
•Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
Rev.2.00 Jul 27, 2004 page 41 of 159
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4524 Group
Fig. 27 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”)
● CNTR1 output: invalid (W4
3
= “0”)
Timer 4 count source
Timer 4 count value
(Reload register)
02
16
01
16
00
16
03
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
03
16
(R4L)
Timer 4 underflow signal
PWM signal (output invalid)
Timer 4 start PWM signal “L” fixed
02
16
03
16
01
16
00
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
02
16
01
16
(R4H)
PWM period 7 clock PWM period 7 clock
03
16
01
16
00
16
02
16
02
16
01
16
00
16
02
16
01
16
00
16
03
16
02
16
01
16
00
16
02
16
01
16
00
16
03
16
02
16
(R4L) (R4H) (R4L) (R4H) (R4L) (R4H)
PWM period 7.5 clock PWM period 7.5 clock
● CNTR1 output: valid (W4
3
= “1”)
PWM signal “H” interval extension function: invalid (W4
2
= “0”)
Timer 4 count source
Timer 4 count value
(Reload register)
Timer 4 underflow signal
PWM signal
Timer 4 count source
Timer 4 count value
(Reload register)
Timer 4 underflow signal
PWM signal
Timer 4 start
Timer 4 start
● CNTR1 output: valid (W4
3
= “1”)
PWM signal “H” interval extension function: valid (W4
2
= “1”) (Note)
Note: At PWM signal “H” interval extension function: valid, set “01
16
” or more to reload register R4H.
(R4L) (R4H) (R4L) (R4H) (R4L)
(R4L)
(R4L) (R4L)
(R4L)
3 clock 3 clock
3.5 clock3.5 clock
Rev.2.00 Jul 27, 2004 page 42 of 159
REJ03B0091-0200Z
4524 Group
Fig. 28 CNTR1 output auto-control function by timer 3
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● CNTR1 output auto-control function
CNTR1 output
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e
r
3
u
n
d
e
r
f
l
o
w
s
i
g
n
a
l
PWM signal
T
i
m
e
r
3
s
t
a
r
t
C
N
T
R
1
o
u
t
p
u
t
s
t
a
r
t
Timer 3 stop
C
N
T
R
1
o
u
t
p
u
t
s
t
o
p
➂
➀➁
➂
➀
➁
Rev.2.00 Jul 27, 2004 page 43 of 159
REJ03B0091-0200Z
4524 Group
Fig. 29 Timer 4 count start/stop timing
(R4L) (R4H) (R4L)
Timer 4 count start timing
Waveform extension function of CNTR1 output “H” interval: Invalid (W4
2
= “0”),
CNTR1 output: valid (W4
3
= “1”),
Count source: X
IN
input selected (W4
0
= “0”),
Reload register R4L: “03
16
”
Reload register R4H: “02
16
”
Timer 4 count start timing
TW4A instruction execution cycle (W4
1
) ¨ 1
02
16
01
16
00
16
02
16
03
16
02
16
01
16
00
16
03
16
02
16
00
16
00
16
02
16
01
16
00
16
03
16
02
16
01
16
02
16
(R4H)(R4L)
01
16
(R4H)
(Note 1)
Notes 1: In order to stop timer 4 at CNTR1 output valid (W4
3
= “1”), avoid a timing when timer 4 underflows.
If these timings overlap, a hazard may occur in a CNTR1 output waveform.
2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output.
Mi Mi+1 Mi+2
Mi Mi+1 Mi+2
01
16
Timer 4 count value
(Reload register)
Timer 4
underflow signal
PWM signal
Machine cycle
X
IN
input
(count source selected)
System clock
f(STCK)=f(X
IN
)/4
Register W4
1
●
Timer 4 count stop timing
TW4A instruction execution cycle (W4
1
) ¨ 0
Timer 4 count stop timing
Timer 4 count value
(Reload register)
Timer 4
underflow signal
PWM signal
Machine cycle
X
IN
input
(count source selected)
System clock
f(STCK)=f(X
IN
)/4
Register W4
1
Rev.2.00 Jul 27, 2004 page 44 of 159
REJ03B0091-0200Z
4524 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a pro-
gram run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT un-
derflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of less than 65534
machine cycle by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are ex-
ecuted continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST in-
struction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
Fig. 30 Watchdog timer function
6
5
5
3
4
c
o
u
n
t
(
N
o
t
e
)
V
a
l
u
e
o
f
1
6
-
b
i
t
t
i
m
e
r
(
W
D
T
)
W
D
F
1
f
l
a
g
➂
W
R
S
T
i
n
s
t
r
u
c
t
i
o
n
e
x
e
c
u
t
e
d
(
s
k
i
p
e
x
e
c
u
t
e
d
)
R
E
S
E
T
p
i
n
o
u
t
p
u
t
WDF2 flag
➄ System reset➀ Reset
released
➀
A
f
t
e
r
s
y
s
t
e
m
i
s
r
e
l
e
a
s
e
d
f
r
o
m
r
e
s
e
t
(
=
a
f
t
e
r
p
r
o
g
r
a
m
i
s
s
t
a
r
t
e
d
)
,
t
i
m
e
r
W
D
T
s
t
a
r
t
s
c
o
u
n
t
d
o
w
n
.
➁
W
h
e
n
t
i
m
e
r
W
D
T
u
n
d
e
r
f
l
o
w
o
c
c
u
r
s
,
W
D
F
1
f
l
a
g
i
s
s
e
t
t
o
“
1
.
”
➂
W
h
e
n
t
h
e
W
R
S
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
,
W
D
F
1
f
l
a
g
i
s
c
l
e
a
r
e
d
t
o
“
0
,
”
t
h
e
n
e
x
t
i
n
s
t
r
u
c
t
i
o
n
i
s
s
k
i
p
p
e
d
.
➃
W
h
e
n
t
i
m
e
r
W
D
T
u
n
d
e
r
f
l
o
w
o
c
c
u
r
s
w
h
i
l
e
W
D
F
1
f
l
a
g
i
s
“
1
,
”
W
D
F
2
f
l
a
g
i
s
s
e
t
t
o
“
1
”
a
n
d
t
h
e
w
a
t
c
h
d
o
g
r
e
s
e
t
s
i
g
n
a
l
i
s
o
u
t
p
u
t
.
➄
T
h
e
o
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
o
f
R
E
S
E
T
p
i
n
i
s
t
u
r
n
e
d
“
O
N
”
b
y
t
h
e
w
a
t
c
h
d
o
g
r
e
s
e
t
s
i
g
n
a
l
a
n
d
s
y
s
t
e
m
r
e
s
e
t
i
s
e
x
e
c
u
t
e
d
.
N
o
t
e
:
T
h
e
n
u
m
b
e
r
o
f
c
o
u
n
t
i
s
e
q
u
a
l
t
o
t
h
e
n
u
m
b
e
r
o
f
c
y
c
l
e
b
e
c
a
u
s
e
t
h
e
c
o
u
n
t
s
o
u
r
c
e
o
f
w
a
t
c
h
d
o
g
t
i
m
e
r
i
s
t
h
e
i
n
s
t
r
u
c
t
i
o
n
c
l
o
c
k
.
F
F
F
F
1
6
0
0
0
0
1
6
➁➁
➃
Rev.2.00 Jul 27, 2004 page 45 of 159
REJ03B0091-0200Z
4524 Group
Fig. 31 Program example to start/stop watchdog timer
Fig. 32 Program example to enter the mode when using the
watchdog timer
WRST ; WDF1 flag cleared
NOP
DI ; Interrupt disabled
EPOF ; POF instruction enabled
POF
↓
Oscillation stop
•••
•••
When the watchdog timer is used, clear the WDF1 flag at a cycle of
less than 65534 machine cycles with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruc-
tion and the WRST instruction continuously (refer to Figure 31).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
power down mode.
When using the watchdog timer and the power down mode, initial-
ize the WDF1 flag with the WRST instruction just before the system
enters the power down state (refer to Figure 32).
The watchdog timer function is valid after system is returned from
the power down. When not using the watchdog timer function, stop
the watchdog timer function with the DWDT instruction and the
WRST instruction continuously every system is returned from the
power down.
WRST ; WDF1 flag cleared
DI
DWDT ; Watchdog timer function enabled/disabled
WRST ; WEF and WDF1 flags cleared
•••
••• •••
Rev.2.00 Jul 27, 2004 page 46 of 159
REJ03B0091-0200Z
4524 Group
V
S
S
V
DD
I
A
P
2
(
P
2
0
–
P
2
3
)
I
A
P
3
(
P
3
0
–
P
3
3
)
O
P
2
A
(
P
2
0
–
P
2
3
)
O
P
3
A
(
P
3
0
–
P
3
3
)
T
A
B
A
D
1/6
Q1
3
Q2
1
Q
2
0
Q
2
2
T
A
D
A
B
Q1
2
Q1
1
Q1
0
0
1
4444
8 8
8
01 1
8
10
Q1
3
Q1
3
0
1
Q1
3
8
8
2
T
A
L
A
Q1
3
Q
2
3
TAQ2
TQ2A
T
A
Q
1
T
Q
1
A
A
D
F
(
1
)
P
2
0
/
A
I
N
0
P
3
0
/
A
I
N
4
P
3
1
/
A
I
N
5
P
3
2
/
A
I
N
6
P
3
3
/
A
I
N
7
3
10
10
P
2
1
/
A
I
N
1
P2
2
/A
IN2
P
2
3
/
A
I
N
3
4 4
Q3
1
Q3
0
Q3
2
Q3
3
T
A
Q
3
T
Q
3
A
4
D
A
c
o
n
v
e
r
t
e
r
(
N
o
t
e
1
)
R
e
g
i
s
t
e
r
A
(
4
)
Register B (4)
DAC
operation
signal
C
o
m
p
a
r
a
t
o
r
8
-
c
h
a
n
n
el
m
u
l
t
i
-
p
l
e
x
e
d
an
a
l
o
g
s
w
i
t
c
h
I
n
s
t
r
u
c
t
i
o
n
c
l
o
c
k
A/D control ci r c uit
Successive comparison
register (AD) (10)
A/D
interrupt
C
o
m
p
a
r
a
t
o
r
r
e
g
i
s
t
e
r
(
8
)
N
o
t
e
s
1
:
T
h
i
s
s
w
i
t
c
h
i
s
t
u
r
n
e
d
O
N
o
n
l
y
w
h
e
n
A
/
D
c
o
n
v
e
r
t
e
r
i
s
o
p
e
r
a
t
i
n
g
a
n
d
g
e
n
e
r
a
t
e
s
t
h
e
c
o
m
p
a
r
i
s
o
n
v
o
l
t
a
g
e
.
2
:
W
r
i
t
i
n
g
/
r
e
a
d
i
n
g
d
a
t
a
t
o
t
h
e
c
o
m
p
a
r
a
t
o
r
r
e
g
i
s
t
e
r
i
s
p
o
s
s
i
b
l
e
o
n
l
y
i
n
t
h
e
c
o
m
p
a
r
a
t
o
r
m
o
d
e
(
Q
1
3
=
1
)
.
T
h
e
v
a
l
u
e
o
f
t
h
e
c
o
m
p
a
r
a
t
o
r
r
e
g
i
s
t
e
r
i
s
r
e
t
a
i
n
e
d
e
v
e
n
w
h
e
n
t
h
e
m
o
d
e
i
s
s
w
i
t
c
h
e
d
t
o
t
h
e
A
/
D
c
o
n
v
e
r
s
i
o
n
m
o
d
e
(
Q
1
3
=
0
)
b
e
c
a
u
s
e
i
t
i
s
s
e
p
a
r
a
t
e
d
f
r
o
m
t
h
e
s
u
c
c
e
s
s
i
v
e
c
o
m
p
a
r
i
s
o
n
r
e
g
i
s
t
e
r
(
A
D
)
.
A
l
s
o
,
t
h
e
r
e
s
o
l
u
t
i
o
n
i
n
t
h
e
c
o
m
p
a
r
a
t
o
r
m
o
d
e
i
s
8
b
i
t
s
b
e
c
a
u
s
e
t
h
e
c
o
m
p
a
r
a
t
o
r
r
e
g
i
s
t
e
r
c
o
n
s
i
s
t
s
o
f
8
b
i
t
s
.
(
N
o
t
e
2
)
A/D CONVERTER (Comparator)
The 4524 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog volt-
ages input from the analog input pin with preset values.
Table 11 A/D converter characteristics
Characteristics
Successive comparison method
10 bits
Linearity error: ±2LSB
Differential non-linearity error: ±0.9LSB
31
µ
s (High-speed through-mode at 6.0
MHz oscillation frequency)
8
Parameter
Conversion format
Resolution
Relative accuracy
Conversion speed
Analog input pin
Fig. 33 A/D conversion circuit structure
Rev.2.00 Jul 27, 2004 page 47 of 159
REJ03B0091-0200Z
4524 Group
Table 12 A/D control registers
Q12
0
0
0
0
1
1
1
1
A/D operation mode selection bit
Analog input pin selection bits
Q11
0
0
1
1
0
0
1
1
A/D control register Q1 at power down : state retained
at reset : 00002
Q13A/D conversion mode
Comparator mode
R/W
TAQ1/TQ1A
Q10
0
1
0
1
0
1
0
1
Q12
Q11
Q10
Analog input pins
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
P23
AIN3
P22
AIN2
P21
AIN1
P20
AIN0
P23/AIN3 pin function selection bit
P22/AIN2 pin function selection bit
P21/AIN1 pin function selection bit
P20/AIN0 pin function selection bit
0
1
0
1
0
1
0
1
Q23
Q22
Q21
Q20
R/W
TAQ2/TQ2A
A/D control register Q2 at power down : state retained
at reset : 00002
P33
AIN7
P32
AIN6
P31
AIN5
P30
AIN4
P33/AIN7 pin function selection bit
P32/AIN6 pin function selection bit
P31/AIN5 pin function selection bit
P30/AIN4 pin function selection bit
0
1
0
1
0
1
0
1
Q33
Q32
Q31
Q30
R/W
TAQ3/TQ3A
A/D control register Q3 at power down : state retained
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Jul 27, 2004 page 48 of 159
REJ03B0091-0200Z
4524 Group
(1) A/D control register
•A/D control register Q1
Register Q1 controls the selection of A/D operation mode and the
selection of analog input pins. Set the contents of this register
through register A with the TQ1A instruction. The TAQ1 instruc-
tion can be used to transfer the contents of register Q1 to register
A.
•A/D control register Q2
Register Q2 controls the selection of P20/AIN0–P23/AIN3. Set the
contents of this register through register A with the TQ2A instruc-
tion. The TAQ2 instruction can be used to transfer the contents of
register Q2 to register A.
•A/D control register Q3
Register Q3 controls the selection of P30/AIN4–P33/AIN7. Set the
contents of this register through register A with the TQ3A instruc-
tion. The TAQ3 instruction can be used to transfer the contents of
register Q3 to register A.
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this reg-
ister can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute these instructions dur-
ing A/D conversion.
When the contents of register AD is n, the logic value of the com-
parison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following for-
mula:
Logic value of comparison voltage Vref
Vref = ✕ n
n: The value of register AD (n = 0 to 1023)
VDD
1024
(4) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to “1” when A/D con-
version completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(6) Operation description
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the com-
parison voltage Vref is compared with the analog input voltage
VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is Vref
> VIN, it is cleared to “0.”
The 4524 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D con-
version stops after 62 machine cycles (31
µ
s when f(XIN) = 6.0
MHz in high-speed through mode) from the start, and the conver-
sion result is stored in the register AD. An A/D interrupt activated
condition is satisfied and the ADF flag is set to “1” as soon as A/D
conversion completes (Figure 34).
Table 13 Change of successive comparison register AD during A/D conversion
Comparison voltage (Vref) value
Change of successive comparison register ADAt starting conversion
±
±
±
±
±
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
1
✼1
✼1
✼1
-----
-----
-----
-----
0
1
✼2
✼2
0
0
1
✼3
0
0
0
✼8
0
0
0
✼9
0
0
0
✼A
A/D conversion result
VDD
2
VDD
2
VDD
2
VDD
2
VDD
4
VDD
4VDD
8
VDD
1024
○○○○
-------------
-------------
-------------
-------------
-------------
-------------
-------------
-------------
Rev.2.00 Jul 27, 2004 page 49 of 159
REJ03B0091-0200Z
4524 Group
Fig. 35 Setting registers
A/D control register Q2
AIN4 pin function selected
✕✕✕1
(Bit 3) (Bit 0)
(7) A/D conversion timing chart
Figure 34 shows the A/D conversion timing chart.
Fig. 34 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P30/AIN4 pin is A/D converted, and the high-
order 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
➀ Select the AIN4 pin function with the bit 0 of the register Q3. Se-
lect the AIN4 pin function and A/D conversion mode with the
register Q1 (refer to Figure 35).
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
A
D
S
T
i
n
s
t
r
u
c
t
i
o
n
A
/
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
A
D
F
)
6
2
m
a
c
h
i
n
e
c
y
c
l
e
s
D
A
C
o
p
e
r
a
t
i
o
n
s
i
g
n
a
l
A/D control register Q1
AIN4 pin selected
A/D conversion mode
0100
(Bit 3) (Bit 0)
✕: Set an arbitrary value.
Rev.2.00 Jul 27, 2004 page 50 of 159
REJ03B0091-0200Z
4524 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison volt-
ages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in
the low-order 4 bits of the comparator register with the TADAB in-
struction.
When changing from A/D conversion mode to comparator mode,
the result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from regis-
ter AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of com-
parison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input volt-
age with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the inter-
rupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator oper-
ating.
The comparator stops 8 machine cycles after it has started (4
µ
s at
f(XIN) = 6.0 MHz in high-speed through mode). When the analog
input voltage is lower than the comparison voltage, the ADF flag is
set to “1.”
(13) Notes for the use of A/D conversion
•TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
• Operation mode of A/D converter
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conver-
sion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
Logic value of comparison voltage Vref
Vref = ✕n
n: The value of register AD (n = 0 to 255)
Fig. 36 Comparator operation timing chart
VDD
256
ADST instruction
C
o
m
p
a
r
i
s
o
n
r
e
s
u
l
t
s
t
o
r
e
f
l
a
g
(
A
D
F
)
8
m
a
c
h
i
n
e
c
y
c
l
e
s
D
A
C
o
p
e
r
a
t
i
o
n
s
i
g
n
a
l
C
o
m
p
a
r
a
t
o
r
o
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r
a
t
i
o
n
c
o
m
p
l
e
t
e
d
.
(
T
h
e
v
a
l
u
e
o
f
A
D
F
i
s
d
e
t
e
r
m
i
n
e
d
)
→
Rev.2.00 Jul 27, 2004 page 51 of 159
REJ03B0091-0200Z
4524 Group
(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 37).
•Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D con-
version output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D con-
version output data changes from “1023” to “1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference re-
quired to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Fig. 37 Definition of A/D conversion accuracy
VFST–V0T
1022
VDD
1024
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
• 1LSB at relative accuracy →(V)
• 1LSB at absolute accuracy →(V)
V
DD
V
1022
V
n
V
1
V
0
V
n
+
1
n
+
1
n
1022
1023
1
0
b
a
c
Output data
Differential non-linearity error =
Linearity error =
[LSB]
c
a
b–a
a
[
L
S
B
]
Actual A/D conversion
characteristics
a
:
1
L
S
B
b
y
r
e
l
a
t
i
v
e
a
c
c
u
r
a
c
y
b
:
V
n
+
1
–
V
n
c
:
D
i
f
f
e
r
e
n
c
e
b
e
t
w
e
e
n
i
d
e
a
l
V
n
a
n
d
a
c
t
u
a
l
V
n
Zero transition voltage (V
0T
)A
n
a
l
o
g
v
o
l
t
a
g
e
Full-scale transition voltage (V
FST
)
I
d
e
a
l
l
i
n
e
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
b
e
t
w
e
e
n
V
0
–
V
1
0
2
2
Rev.2.00 Jul 27, 2004 page 52 of 159
REJ03B0091-0200Z
4524 Group
SERIAL I/O
The 4524 Group has a built-in clock synchronous serial I/O which
can serially transmit or receive 8-bit data.
Serial I/O consists of;
• serial I/O register SI
• serial I/O control register J1
• serial I/O transmit/receive completion flag (SIOF)
• serial I/O counter
Registers A and B are used to perform data transfer with internal
CPU, and the serial I/O pins are used for external data transfer.
The pin functions of the serial I/O pins can be set with the register
J1.
Table 14 Serial I/O pins
Pin
D6/SCK
D5/SOUT
D4/SIN
Pin function when selecting serial I/O
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
Fig. 38 Serial I/O structure
Table 15 Serial I/O control register
Note: “R” represents read enabled, and “W” represents write enabled.
J13
0
0
1
1
J11
0
0
1
1
Serial I/O synchronous clock selection bits
Serial I/O port function selection bits
J12
0
1
0
1
J10
0
1
0
1
Serial I/O control register J1 at power down : state retained
at reset : 00002
J13
J12
J11
J10
Synchronous clock
Instruction clock (INSTCK) divided by 8
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (SCK input) Port function
D6, D5, D4 selected/SCK, SOUT, SIN not selected
SCK, SOUT, D4 selected/D6, D5, SIN not selected
SCK, D5, SIN selected/D6, SOUT, D4 not selected
SCK, SOUT, SIN selected/D6, D5, D4 not selected
R/W
TAJ1/TJ1A
1/8
1/4
1/2
00
01
10
11
Synchronous
circuit Serial I/O counter (3) SIOF Serial I/O
interrupt
INSTCK
D6/SCK SCK QS
R
MSB Serial I/O register (8) LSB
SIN
J11J10
J13J12
Register B (4) Register A (4)
TSIAB TABSITABSI
SOUT
D5/SOUT
D4/SIN
SST
instruction
Internal reset signal
Note: Even when the SCK, SOUT, SIN pin functions are used, the input of
D6, D5, D4 are valid.
Rev.2.00 Jul 27, 2004 page 53 of 159
REJ03B0091-0200Z
4524 Group
Fig. 39 Serial I/O register state when transfer
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conver-
sion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmit-
ted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
do not select the SCK pin.
(2) Serial I/O transmit/receive completion flag
(SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when
serial data transmit or receive operation completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O control register J1
Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and
D4/SIN pin function. Set the contents of this register through regis-
ter A with the TJ1A instruction. The TAJ1 instruction can be used to
transfer the contents of register J1 to register A.
D7D6D5D4D3D2D1D0
A
t
t
r
a
n
s
m
i
t
(
D7–
D0:
t
r
a
n
s
f
e
r
d
a
t
a
)A
t
r
e
c
e
i
v
e
D7D6D5D4D3D2D1D0
SI
N
p
i
n
SO
U
T
p
i
n
SO
U
T
p
i
n
SI
N
p
i
nS
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
(
S
I
)Serial I/O register (SI)
D7D6D5D4D3D2D1D0
*
D7D6D5D4D3D2D1
D7D6D5D4D3D2
D0
D1D0
Transfer data set
T
r
a
n
s
f
e
r
s
t
a
r
t
Transfer complete
*
*
*
*******
********
********
*******
******
Rev.2.00 Jul 27, 2004 page 54 of 159
REJ03B0091-0200Z
4524 Group
(5) How to use serial I/O
Figure 40 shows the serial I/O connection example. Serial I/O inter-
rupt is not used in this example. In the actual wiring, pull up the
wiring between each pin with a resistor. Figure 40 shows the data
transfer timing and Table 16 shows the data transfer sequence.
Fig. 40 Serial I/O connection example
SOUT
SRDY signal
SCK
SIN
D3
SC
K
SO
U
T
SI
N
D3
M
a
s
t
e
r
(
c
l
o
c
k
c
o
n
t
r
o
l
)
Serial I/O interrupt
enable bit
(
S
N
Z
S
I
i
n
s
t
r
u
c
t
i
o
n
v
a
l
i
d
)
Interrupt control
register V2
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
Instruction clock/8 selected
as synchronou s clock
Slave (external clock)
Serial I/O interrupt
enable bit
(
S
N
Z
S
I
i
n
s
t
r
u
c
t
i
o
n
v
a
l
i
d
)
✕0
1
(Bit 3) (
B
i
t
0
)
100
✕0✕✕
11
✕✕
11
✕: Set an arbitrary value.
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
(
B
i
t
3
)(Bit 0)
(Bit 3) (Bit 0) I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
V
2
(
B
i
t
3
)(Bit 0)
External clock sele cted
as synchronou s clock
Rev.2.00 Jul 27, 2004 page 55 of 159
REJ03B0091-0200Z
4524 Group
Fig. 41 Timing of serial I/O data transfer
M
0
–
M
7
:
C
o
n
t
e
n
t
s
o
f
m
a
s
t
e
r
s
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
S
0
–
S
7
:
C
o
n
t
e
n
t
s
o
f
s
l
a
v
e
s
e
r
i
a
l
I
/
O
r
e
g
i
s
t
e
r
R
i
s
i
n
g
o
f
S
C
K
:
S
e
r
i
a
l
i
n
p
u
t
F
a
l
l
i
n
g
o
f
S
C
K
:
S
e
r
i
a
l
o
u
t
p
u
t
S
I
N
SOUT
M
a
s
t
e
r
S
l
a
v
e
S
CK
S
S
T
i
n
s
t
r
u
c
t
i
o
n
SO
U
T
SI
N
S
0
S
7
’S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
S
T
i
n
s
t
r
u
c
t
i
o
n
SR
D
Y
s
i
g
n
a
l
S
0
S
7
’S
1
S
3
S
4
S
5
S
6
S
7
M
0
M
7
’M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
0
M
7
’M
1
M
2
M
3
M
4
M
5
M
6
M
7
S
2
Rev.2.00 Jul 27, 2004 page 56 of 159
REJ03B0091-0200Z
4524 Group
Table 16 Processing sequence of data transfer from master to slave
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transmit/receive is performed as long as clock is
externally input. (Unlike an internal clock, an external clock is not
stopped when serial transfer is completed.) However, the SIOF flag
is set to “1” when the clock is counted 8 times after executing the
SST instruction. Be sure to set the initial level of the external clock
to “H.”
Master (transmission)
[Initial setting]
• Setting the serial I/O mode register J1 and inter-
rupt control register V2 shown in Figure 40.
TJ1A and TV2A instructions
• Setting the port received the reception enable
signal (SRDY) to the input mode.
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial I/O register SI.
TSIAB instruction
[Transmission]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
SNZSI instruction
•Wait (timing when continuously transferring)
Slave (reception)
[Initial setting]
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 40. TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
(Port D3 is used in this example)
SD instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Reception]
• Check reception completes. SNZSI instruction
• “H” level is output from port D3.SD instruction
[Data processing]
Rev.2.00 Jul 27, 2004 page 57 of 159
REJ03B0091-0200Z
4524 Group
LCD FUNCTION
The 4524 Group has an LCD (Liquid Crystal Display) controller/
driver. When the proper voltage is applied to LCD power supply in-
put pins (VLC1–VLC3) and data are set in timer control register
(W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the
LCD controller/driver automatically reads the display data and con-
trols the LCD display by setting duty and bias.
4 common signal output pins and 20 segment signal output pins
can be used to drive the LCD. By using these pins, up to 80 seg-
ments (when 1/4 duty and 1/3 bias are selected) can be controlled
to display. The LCD power input pins (VLC1–VLC3) are also used as
pins SEG0–SEG2. When SEG0–SEG2. The internal power (VDD) is
used for the LCD power.
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select the
proper display method for the LCD panel being used.
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
Table 17 Duty and maximum number of displayed pixels
(2) LCD clock control
The LCD clock is determined by the timer LC count source selec-
tion bit (W62), timer LC control bit (W63), and timer LC.
Accordingly, the LCD clock frequency (F) is obtained by the follow-
ing formula. Numbers (➀ to ➂) shown below the formula
correspond to numbers in Figure 42, respectively.
• When using the prescaler output (ORCLK) as timer LC count
source (W62=“1”)
F = ORCLK ✕✕
• When using the bit 4 of timer 5 as timer LC count source (W6
2
=“0”)
F = T54✕✕
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
Frame frequency = (Hz)
Frame period = (s) F: LCD clock frequency
1/n: Duty
Fig. 42 LCD clock control circuit structure
Duty
1/2
1/3
1/4
Used COM pins
COM0, COM1 (Note)
COM0–COM2 (Note)
COM0–COM3
Maximum number of displayed pixels
40 segments
60 segments
80 segments
Note: Leave unused COM pins open.
1
LC + 1 1
2
➀➁ ➂
1
LC + 1
➀➁ ➂
F
n
n
F
Note: Count source is sto
pp
ed b
y
settin
g
“0” to this bit.
Timer LC 1/2
W63
0
1
(Note)
T54
W62
0
1
ORCLK
LCD clock
(4)
Reload register RLC (4)
Register A
(TLCA) (TLCA)
➀
➁➂
1
2
Rev.2.00 Jul 27, 2004 page 58 of 159
REJ03B0091-0200Z
4524 Group
Fig. 43 LCD controller/driver
C
o
m
m
o
n
d
r
i
v
e
rBias control
Multiplexer
Selector
RAM
Segment
driver
Selector
RAM
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
D
e
c
o
d
e
r
S
E
G
1
9
1
/
2
,
1
/
3
,
1
/
4
c
o
u
n
t
e
rLCD clock
(from timer block)
L1
0
L1
1
L1
2
L1
3
R
e
g
i
s
t
e
r
A
LCD
ON/OFF
control
Control
signal
V
L
C
3
/
S
E
G
0
S
E
G
3
.
.
.
.
.
.
.
.
.
...
...
Segment
driver
.
.
.
V
LC2
/
SEG
1
V
LC1
/SEG
2
S
E
G
0
t
o
S
E
G
2
o
u
t
p
u
t
L2
0
L2
1
L2
2
L2
3
r
r
r
r
r
r
t
o
Rev.2.00 Jul 27, 2004 page 59 of 159
REJ03B0091-0200Z
4524 Group
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel correspond-
ing to the bit is automatically displayed.
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage differ-
ence between common pin and segment pin which correspond to
the bit automatically becomes lVLC3l and the display pixel at the
cross section turns on.
When returning from reset, and in the RAM back-up mode, a dis-
play pixel turns off because every segment output pin and common
output pin becomes VLC3 level.
Fig. 44 LCD RAM map
Table 18 LCD control registers
Z
X
YB
i
t
s
8
9
1
0
1
1
1
2
1
3
14
15
COM
114
321032103210
S
E
G1
S
E
G2
S
E
G3
S
E
G4
S
E
G5
SEG6
SEG7
C
O
M3
S
E
G1
S
E
G2
S
E
G3
S
E
G4
S
E
G5
SEG6
SEG7
C
O
M2
S
E
G1
S
E
G2
S
E
G3
S
E
G4
S
E
G5
SEG6
SEG7
COM1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
S
E
G9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3C
O
M2COM1COM0COM3COM2COM1COM0
S
E
G9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG9
S
E
G1
0
S
E
G1
1
S
E
G1
2
S
E
G1
3
SEG14
SEG15
S
E
G0S
E
G0S
E
G0SEG0S
E
G8S
E
G1
7
S
E
G1
8
S
E
G1
9
S
E
G1
6S
E
G8SEG8SEG8
SEG9
S
E
G1
0
S
E
G1
1
S
E
G1
2
S
E
G1
3
SEG14
SEG15
SEG17
SEG18
SEG19
SEG16 S
E
G1
7
S
E
G1
8
S
E
G1
9
S
E
G1
6S
E
G1
7
S
E
G1
8
S
E
G1
9
S
E
G1
6
1
213
Note: The area marked “ ” is not the LCD display RAM.
Internal dividing resistor for LCD power
supply selection bit (Note 2)
LCD control bit
LCD control register L1
L13
L12
L11
L10
at reset : 00002at power down : state retained
0
1
0
1
L11
0
0
1
1
L10
0
1
0
1
Duty
1/2
1/3
1/4
Bias
1/2
1/3
1/3
LCD control register L2 at reset : 11112at power down : state retained W
TL2A
0
1
0
1
0
1
0
1
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
L23
L22
L21
L20
VLC3/SEG0 pin function switch bit (Note 3)
VLC2/SEG1 pin function switch bit (Note 4)
VLC1/SEG2 pin function switch bit (Note 4)
Internal dividing resistor for LCD power
supply control bit
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Off
On
Not available
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
R/W
TAL1/TL1A
LCD duty and bias selection bits
Rev.2.00 Jul 27, 2004 page 60 of 159
REJ03B0091-0200Z
4524 Group
Fig. 45 LCD controller/driver structure
C
O
M
1
C
O
M
0
S
E
G
1
6
VL
C
3
VL
C
1
=
VL
C
2
VS
S
VL
C
3
VL
C
1
=
VL
C
2
VS
S
1 flame (2/F)
1/F
O
NO
F
F
V
o
l
t
a
g
e
l
e
v
e
l
(
b
i
t
0
)
C
O
M
0
C
O
M
1
S
E
G
1
6
0
1
X
X
(
b
i
t
3
)
M
(
1
,
1
4
,
8
)
COM
1
SEG
16
C
O
M
0
S
E
G
1
6
1 flame (3/F)
1/F
ON OFF ON
COM
2
VL
C
3
VL
C
2
VLC
1
VS
S
C
O
M
1
COM
0
S
E
G
1
6
VLC
3
VLC
2
VL
C
1
VSS
V
o
l
t
a
g
e
l
e
v
e
l
(bit 0)
COM
0
C
O
M
1
C
O
M
2
S
E
G
1
6
1
0
1
X
(
b
i
t
3
)
M
(
1
,
1
4
,
8
)
COM
2
SEG
16
COM
1
SEG
16
COM
0
SEG
16
1
f
l
a
m
e
(
4
/
F
)
1
/
F
O
NO
F
F
C
O
M
3
C
O
M
2
C
O
M
1
COM
0
S
E
G
1
6
VLC
3
VLC
2
VLC
1
VSS
VLC
3
VLC
2
VLC
1
VSS
V
o
l
tage
l
eve
l
(bit 0)
C
O
M
0
COM
1
C
O
M
2
COM
3
SEG
16
0
1
0
1
(bit 3)
M
(
1
,
1
4
,
8
)
COM
3
S
E
G
1
6
COM
2
SEG
16
COM
1
SEG
16
COM
0
SEG
16
F
:
L
C
D
c
l
o
c
k
f
r
e
q
u
e
n
c
y
X:
S
e
t
a
n
a
r
b
i
t
r
a
r
y
v
a
l
u
e
.
(
T
h
e
s
e
b
i
t
s
a
r
e
n
o
t
r
e
l
a
t
e
d
t
o
se
t
t
h
e
d
r
i
v
e
w
a
v
e
f
o
r
m
a
t
e
a
c
h
d
u
t
y
.
)O
NOFF
1
/
2
D
u
t
y
,
1
/
2
B
i
a
s
:
W
h
e
n
w
r
i
t
i
n
g
(
X
X
1
0
)2
t
o
a
d
d
r
e
s
s
M
(
1
,
1
4
,
8
)
i
n
R
A
M
.
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM.
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM.
Rev.2.00 Jul 27, 2004 page 61 of 159
REJ03B0091-0200Z
4524 Group
(5) LCD power supply circuit
Select the LCD power circuit suitable for the LCD panel.
The LCD control circuit structure is fixed by the following setting.
➀
Set the control of internal dividing resistor by bit 0 of register L2.
➁ Select the internal dividing resistor by bit 3 of register L1.
➂ Select the bias condition by bits 0 and 1 of register L1.
• Internal dividing resistor
The 4524 Group has the internal dividing resistor for LCD power
supply.
When bit 0 of register L2 is set to “0”, the internal dividing resis-
tor is valid. However, when the LCD is turned off by setting bit 2
of register L1 to “0”, the internal dividing resistor is turned off.
The same six resistor (r) is prepared for the internal dividing re-
sistor. According to the setting value of bit 3 of register L1 and
using bias condition, the resistor is prepared as follows;
• L13 = “0”, 1/3 bias used: 2r ✕ 3 = 6r
• L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r
• L13 = “1”, 1/3 bias used: r ✕ 3 = 3r
• L13 = “1”, 1/2 bias used: r ✕ 2 = 2r
•VLC3/SEG0 pin
The selection of VLC3/SEG0 pin function is controlled with the bit 3
of register L2.
When the VLC3 pin function is selected, apply voltage of VLC3 <
VDD to the pin externally.
When the SEG0 pin function is selected, VLC3 is connected to VDD
internally.
• VLC2/SEG1, VLC1/SEG2 pin
The selection of VLC2/SEG1 pin function is controlled with the bit 2
of register L2.
The selection of VLC1/SEG2 pin function is controlled with the bit 1
of register L2.
When the VLC2 pin and VLC1 pin functions are selected and the in-
ternal dividing resistor is not used, apply voltage of
0<VLC1<VLC2<VLC3 to these pins. Short the VLC2 pin and VLC1 pin
at 1/2 bias.
When the VLC2 pin and VLC1 pin functions are selected and the in-
ternal dividing resistor is used, the dividing voltage value
generated internally is output from the VLC1 pin and VLC2 pin. The
VLC2 pin and VLC1 pin has the same electric potential at 1/2 bias.
When SEG1 and SEG2 pin function is selected, use the internal di-
viding resistor. In this time, VLC2 and VLC1 are connected to the
generated dividingg voltage.
Fig. 46 LCD power source circuit example (1/3 bias condition selected)
V
LC3
V
LC2
V
LC1
SEG
0
SEG
1
SEG
2
V
LC3
V
LC2
V
LC1
V
LC3
SEG
1
SEG
2
a) Register L2 = (0000)
2
b) Register L2 = (1000)
2
V
LC3
V
LC2
V
LC1
V
LC3
V
LC2
V
LC1
V
LC3
V
LC2
V
LC1
c) Register L2 = (1110)
2
d) Register L2 = (1111)
2
V
LC3
V
LC2
V
LC1
Rev.2.00 Jul 27, 2004 page 62 of 159
REJ03B0091-0200Z
4524 Group
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, program starts from
address 0 in page 0.
Fig. 47 Reset release timing
Fig. 48 RESET pin input waveform and reset operation
f(XIN)
R
E
S
E
TProgram starts
(address 0 in page 0)
On-chip oscillator (internal oscillator)
is counted 5400 to 5424 times.
N
o
t
e
:
T
h
e
n
u
m
b
e
r
o
f
c
l
o
c
k
c
y
c
l
e
s
d
e
p
e
n
d
s
o
n
t
h
e
i
n
t
e
r
n
a
l
s
t
a
t
e
o
f
t
h
e
m
i
c
r
o
c
o
m
p
u
t
e
r
w
h
e
n
r
e
s
e
t
i
s
p
e
r
f
o
r
m
e
d
.
R
E
S
E
T
0
.
3
V
D
D
0.85V
DD
(N
o
t
e)
N
o
t
e
:
K
e
e
p
t
h
e
v
a
l
u
e
o
f
s
u
p
p
l
y
v
o
l
t
a
g
e
t
o
t
h
e
m
i
n
i
m
u
m
v
a
l
u
e
o
r
m
o
r
e
o
f
t
h
e
r
e
c
o
m
m
e
n
d
e
d
o
p
e
r
a
t
i
n
g
c
o
n
d
i
t
i
o
n
s
.
Reset input
1 machine cycle or more
=
Program starts
(address 0 in page 0)
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
(
i
n
t
e
r
n
a
l
o
s
c
i
l
l
a
t
o
r
)
i
s
c
o
u
n
t
e
d
5
4
0
0
t
o
5
4
2
4
t
i
m
e
s
.
Rev.2.00 Jul 27, 2004 page 63 of 159
REJ03B0091-0200Z
4524 Group
Fig. 49 Structure of reset pin and its peripherals,, and power-on reset operation
Name
D0–D3
D4/SIN, D5/SOUT, D6/SCK
D7/CNTR0
D8/INT0, D9/INT1
P00–P03
P10–P13
P20/AIN0–P23/AIN3
P30/AIN4–P33/AIN7
P40–P43
C/CNTR1
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
Function
D0–D3
D4–D6
D7
D8, D9
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
C
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Note 1)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Note 1)
High-impedance (Note 1)
High-impedance (Notes 1, 2)
“L” (VSS) level
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V must be set to 100 µs or less. If the rising time ex-
ceeds 100 µs, connect a capacitor between the RESET pin and
VSS at the shortest distance, and input “L” level to RESET pin until
the value of supply voltage reaches the minimum operating volt-
age.
Table 19 Port state at reset
R
E
S
E
T
p
i
n
W
E
F
Watchdog reset signal
(
N
o
t
e
1
)
P
u
l
l
-
u
p
t
r
a
n
s
i
s
t
o
r
(
N
o
t
e
1
)
P
o
w
e
r
-
o
n
r
e
s
e
t
c
i
r
c
u
i
t
Voltage drop detection circuit
VDD (Note 3)
1
0
0
µs
o
r
l
e
s
s
(
N
o
t
e
2
)
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
P
o
w
e
r
-
o
nReset released
Internal reset signal
R
e
s
e
t
s
t
a
t
e
Notes 1: T
h
i
s
s
y
m
b
o
l
r
e
p
r
e
s
e
n
t
s
a
p
a
r
a
s
i
t
i
c
d
i
o
d
e
.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
P
o
w
e
r
-
o
n
r
e
s
e
t
c
i
r
c
u
i
t
o
u
t
p
u
t
Rev.2.00 Jul 27, 2004 page 64 of 159
REJ03B0091-0200Z
4524 Group
• Program counter (PC) ..........................................................................................................
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE)..................................................................................................
• Power down flag (P) .............................................................................................................
• External 0 interrupt request flag (EXF0) ..............................................................................
• External 1 interrupt request flag (EXF1) ..............................................................................
• Interrupt control register V1..................................................................................................
• Interrupt control register V2..................................................................................................
• Interrupt control register I1 ...................................................................................................
• Interrupt control register I2 ...................................................................................................
• Interrupt control register I3 ...................................................................................................
• Timer 1 interrupt request flag (T1F) .....................................................................................
• Timer 2 interrupt request flag (T2F) .....................................................................................
• Timer 3 interrupt request flag (T3F) .....................................................................................
• Timer 4 interrupt request flag (T4F) .....................................................................................
• Timer 5 interrupt request flag (T5F) .....................................................................................
• Watchdog timer flags (WDF1, WDF2)..................................................................................
• Watchdog timer enable flag (WEF) ......................................................................................
• Timer control register PA ......................................................................................................
• Timer control register W1 .....................................................................................................
• Timer control register W2 .....................................................................................................
• Timer control register W3 .....................................................................................................
• Timer control register W4 .....................................................................................................
• Timer control register W5 .....................................................................................................
• Timer control register W6 .....................................................................................................
• Clock control register MR .....................................................................................................
• Serial I/O transmit/receive complation flag (SIOF) ..............................................................
• Serial I/O mode register J1 ..................................................................................................
• Serial I/O register SI .............................................................................................................
• A/D conversion completion flag (ADF) .................................................................................
• A/D control register Q1 .........................................................................................................
• A/D control register Q2 .........................................................................................................
• A/D control register Q3 .........................................................................................................
• Successive approximation register AD ................................................................................
• Comparator register..............................................................................................................
• LCD control register L1 ........................................................................................................
• LCD control register L2 ........................................................................................................
“✕” represents undefined.
Fig. 50 Internal state at reset
(2) Internal state at reset
Figure 50 and 51 show internal state at reset (they are the same af-
ter system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure 50 are undefined, so set the
initial value to them.
00000000000000
0 (Interrupt disabled)
0
0
0
0 0 0 0 (Interrupt disabled)
0 0 0 0 (Interrupt disabled)
0000
0000
0
0
0
0
0
0
0
1
0 (Prescaler stopped)
0 0 0 0 (Timer 1 stopped)
0 0 0 0 (Timer 2 stopped)
0 0 0 0 (Timer 3 stopped)
0 0 0 0 (Timer 4 stopped)
0 0 0 0 (Timer 5 stopped)
0 0 0 0 (Timer LC stopped)
1100
0
0 0 0 0 (External clock selected,
serial I/O port not selected)
✕✕✕✕✕✕
0
0000
0000
0000
✕✕✕✕✕✕
✕✕✕✕✕✕
0000
1111
✕✕
✕ ✕✕✕
✕✕
Rev.2.00 Jul 27, 2004 page 65 of 159
REJ03B0091-0200Z
4524 Group
• Key-on wakeup control register K0 ......................................................................................
• Key-on wakeup control register K1 ......................................................................................
• Key-on wakeup control register K2 ......................................................................................
• Pull-up control register PU0 .................................................................................................
• Pull-up control register PU1 .................................................................................................
• Port output structure control register FR0 ...........................................................................
• Port output structure control register FR1 ...........................................................................
• Port output structure control register FR2 ...........................................................................
• Port output structure control register FR3 ...........................................................................
• Carry flag (CY)......................................................................................................................
• Register A .............................................................................................................................
• Register B .............................................................................................................................
• Register D .............................................................................................................................
• Register E .............................................................................................................................
• Register X .............................................................................................................................
• Register Y .............................................................................................................................
• Register Z .............................................................................................................................
• Stack pointer (SP) ................................................................................................................
• Operation source clock.......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ......................................................................................................Stop
• Quartz-crystal oscillator........................................................................................ Operating
“✕” represents undefined.
Fig. 51 Internal state at reset
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0000
0000
✕✕✕
✕✕✕✕✕✕
0000
0000
✕✕
111
✕✕
Rev.2.00 Jul 27, 2004 page 66 of 159
REJ03B0091-0200Z
4524 Group
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
Fig. 52 Voltage drop detection reset circuit
Fig. 53 Voltage drop detection circuit operation waveform
E
P
O
F
i
n
s
t
r
u
c
t
i
o
n
+
P
O
F
i
n
s
t
r
u
c
t
i
o
n
E
P
O
F
i
n
s
t
r
u
c
t
i
o
n
+
P
O
F
2
i
n
s
t
r
u
c
t
i
o
n
Q
S
R
S
V
D
E
i
n
s
t
r
u
c
t
i
o
n
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
Voltage drop detection circuit
Reset signal
–
V
R
S
T
V
o
l
t
a
g
e
d
r
o
p
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
V
D
C
E
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
T
5
F
f
l
a
g
K
e
y
-
o
n
w
a
k
e
u
p
s
i
g
n
a
l
Q S
R
+
V
DD
V
o
l
t
a
g
e
d
r
o
p
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
R
e
s
e
t
s
i
g
n
a
l
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 5400 to 5424 times.
V
RST
(detection
voltage)
R
E
S
E
T
p
i
n
Note: Detection voltage of voltage drop detection circuit does not have hysteresis.
The voltage drop detection circuit is valid when CPU is active while
the VDCE pin is “H”.
Even after system goes into the power down mode, the voltage
drop detection circuit is also valid with the SVDE instruction.
Execution of SVDE instruction is valid only at once.
In order to release the execution of the SVDE instruction, system
reset is not required.
Table 20 Voltage drop detection circuit operation state
VDCE pin
“L”
“H”
At CPU operating
Invalid
Valid
At power down
(SVDE instruction is not executed)
Invalid
Invalid
At power down
(SVDE instruction is executed)
Invalid
Valid
■ Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 54);
supply voltage does not fall below to VRST, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST and re-goes up after that. Fig. 54 VDD and VRST
VDD
Recommended
operatng condition
min.value
No reset
Program failure may occur.
VRST
VDD
Recommended
operatng condition
min.value
VRST
→ Normal operation
Reset
Rev.2.00 Jul 27, 2004 page 67 of 159
REJ03B0091-0200Z
4524 Group
Table 21 Functions and states retained at power down
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control registers I1 to I3
Selected oscillation circuit
Clock control register MR
Timer 1 to timer 4 functions
Timer 5 function
Timer LC function
Watchdog timer function
Timer control registers PA, W4
Timer control registers W1 to W3, W5, W6
Serial I/O function
Serial I/O control register J1
A/D function
A/D control registers Q1 to Q3
LCD display function
LCD control registers L1, L2
Voltage drop detection circuit
Port level
Pull-up control registers PU0, PU1
Key-on wakeup control registers K0 to K2
Port output format control registers
FR0 to FR3
External interrupt request flags
(EXF0, EXF1)
Timer interrupt request flags (T1F to T4F)
Timer interrupt request flag (T5F)
A/D conversion completion flag (ADF)
Serial I/O transmit/receive completion flag
SIOF
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
✕
O
✕
O
O
O
(Note 3)
O
(Note 3)
✕ (Note 4)
✕
O
✕
O
✕
O
(Note 5)
O
(Note 6)
(Note 7)
O
O
O
✕
(Note 3)
O
✕
✕
✕
✕ (Note 4)
✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at power
down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at power down.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed and “H” level is applied to
the VDCE pin, this function is valid at power down.
7: In the power down mode, C/CNTR1 pin outputs “L” level.
However, when the CNTR input is selected (W11, W10=“11”), C/
CNTR1 pin is in an input enabled state (output=high-impedance).
Other ports retain their respective output levels.
Power down mode
✕
O
✕
O
O
O
(Note 3)
O
O
✕ (Note 4)
✕
O
✕
O
✕
O
O
O
(Note 6)
(Note 7)
O
O
O
✕
(Note 3)
O
✕
✕
✕
✕ (Note 4)
✕ (Note 4)
POWER DOWN FUNCTION
The 4524 Group has 2-type power down functions.
System enters into each power down state by executing the follow-
ing instructions.
• Clock operating mode ......................EPOF and POF instructions
• RAM back-up mode .......................EPOF and POF2 instructions
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
(1) Clock operating mode
The following functions and states are retained.
• RAM
• Reset circuit
• XCIN–XCOUT oscillation
• LCD display
• T imer 5
(2) RAM back-up mode
The following functions and states are retained.
• RAM
• Reset circuit
(3) Warm start condition
The system returns from the power down state when;
• External wakeup signal is input
• Timer 5 underflow occurs
in the power down mode.
In either case, the CPU starts executing the program from address
0 in page 0. In this case, the P flag is “1.”
(4) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin,
• reset by watchdog timer is performed, or
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of
the power down flag (P) with the SNZP instruction. The warm start
condition from the clock operating mode can be identified by exam-
ining the state of T5F flag.
Clock
operating RAM
back-up
Rev.2.00 Jul 27, 2004 page 68 of 159
REJ03B0091-0200Z
4524 Group
(6) Return signal
An external wakeup signal or timer 5 interrupt request flag (T5F) is
used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped.
Table 22 shows the return condition for each return source.
(7) Control registers
•Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruc-
tion. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
•Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruc-
tion. In addition, the TAK1 instruction can be used to transfer the
contents of register K0 to register A.
•Key-on wakeup control register K2
Register K2 controls the INT0 and INT1 pin key-on wakeup func-
tion. Set the contents of this register through register A with the
TK2A instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
Table 22 Return source and return condition Remarks
Return condition
External wakeup signal
Return source
Ports P00–P03
Ports P10–P13
INT0 pin
INT1 pin
•Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transis-
tor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
•Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transis-
tor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be
used to transfer the contents of register PU1 to register A.
•External interrupt control register I1
Register I1 controls the valid waveform of the external 0 inter-
rupt, the input control of INT0 pin and the return input level. Set
the contents of this register through register A with the TI1A in-
struction. In addition, the TAI1 instruction can be used to transfer
the contents of register I1 to register A.
•External interrupt control register I2
Register I2 controls the valid waveform of the external 1 inter-
rupt, the input control of INT1 pin and the return input level. Set
the contents of this register through register A with the TI2A in-
struction. In addition, the TAI2 instruction can be used to transfer
the contents of register I2 to register A.
Return by an external “L” level in-
put.
Return by an external “H” level or
“L” level input, or rising edge
(“L”→“H”) or falling edge
(“H”→“L”).
When the return signal is input, the
interrupt request flag (EXF0,
EXF1) is not set to “1”.
Return by timer 5 underflow or by
setting T5F to “1”.
It can be used in the clock operat-
ing mode.
The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the power
down state.
Select the return level (“L” level or “H” level) with register I1 (I2) and return
condition (return by level or edge) with register K2 according to the external
state before going into the power down state.
Clear T5F with the SNZT5 instruction before system enters into the power
down state.
When system enters into the power down state while T5F is “1”, system re-
turns from the state immediately because it is recognized as return condition.
Timer 5 interrupt
request flag (T5F)
Rev.2.00 Jul 27, 2004 page 69 of 159
REJ03B0091-0200Z
4524 Group
Fig. 55 State transition
Fig. 56 Set source and clear source of the P flag
Fig. 57 Start condition identified example using the SNZP instruction
S
R
Q
Power down flag
P
P
O
F
o
r
P
O
F
2
i
n
s
t
r
u
c
t
i
o
n
Reset inpu
t
● Set source
● Clear source Reset input
• • • • • • •
• • • • • •
EPOF instruction +
POF or
POF2
instruction
E
P
O
F
i
n
s
t
r
u
c
t
i
o
n
+
P
r
o
g
r
a
m
s
t
a
r
t
P = “1”
?
Yes W
a
r
m
s
t
a
r
t
C
o
l
d
s
t
a
r
t
No T
5
F
=
“
1
”
?
Yes
N
o
Return from
timer 5 underflow R
e
t
u
r
n
f
r
o
m
e
x
t
e
r
n
a
l
w
a
k
e
u
p
s
i
g
n
a
l
Reset
B
Operation state
• Operation source clock: f(X
IN
)
• Oscillation circuit:
Ceramic resonator
• On-chip oscillator: Stop
• RC oscillation circuit: Stop
A
C
E
Clock operating mode
Main clock: stop
Sub-clock: operating
Wakeup
(Stabilizing time c )
POF2 instruction
execution
F
RAM back-up mode
POF2 instruction
execution
High-speed mode
D
• Operation clock: f(X
CIN
)
• Oscillation circuit:
Quartz-crystal oscillation
MR
0
←0
(Note 4)
MR
0
←1
(Note 4)
Low-speed
mode
Wakeup
(Stabilizing time b )
POF2 instruction
execution
Wakeup
(Stabilizing time d )
POF2 instruction
execution
Wakeup
(Stabilizing time e )
POF instruction
execution
Wakeup
(Stabilizing time e )
POF instruction
execution
Wakeup
(Stabilizing time d )
POF instruction
execution
Wakeup
(Stabilizing time b )
(Stabilizing time a )
POF instruction
execution
Wakeup
(Stabilizing time c )
Main clock: stop
Sub-clock: stop
CMCK instruction
execution (Note 3)
Operation state
• Operation source clock:
f(RING)
• Oscillation circuit:
On-chip oscillator
• Ceramic resonator:
Operating (Note 2)
• RC oscillation circuit: Stop
CRCK instruction
execution (Note 3)
Operation state
• Operation source clock: f(X
IN
)
• Oscillation circuit:
RC oscillation
• On-chip oscillator: Stop
• Ceramic resontor: Stop
Operation state
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times.
Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times.
Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(X
IN
) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(X
IN
) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(X
IN
) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(X
IN
) 5400 times.
Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(X
IN
) 21 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(X
IN
) 42 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(X
IN
) 84 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(X
IN
) 168 times.
Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(X
CIN
) 675 times.
In low-speed/2 mode, microcomputer starts its operation after counting the f(X
CIN
) 1350 times.
In low-speed/4 mode, microcomputer starts its operation after counting the f(X
CIN
) 2700 times.
In low-speed/8 mode, microcomputer starts its operation after counting the f(X
CIN
) 5400 times.
Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock.
3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped.
4: The main clock (f(X
IN
) or f(RING)) or sub-clock (f(X
CIN
)) is selected for operation source clock by the bit 0 of clock control register MR.
5: The sub-clock (quartz-crystal oscillation) is operating except in state F.
T5F
T5F
T5F
T5F
Rev.2.00 Jul 27, 2004 page 70 of 159
REJ03B0091-0200Z
4524 Group
Table 23 Key-on wakeup control register, pull-up control register and interrupt control register
K03
K02
K01
K00
Key-on wakeup control register K0
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P03 key-on wakeup
control bit
Port P02 key-on wakeup
control bit
Port P01 key-on wakeup
control bit
Port P00 key-on wakeup
control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
K13
K12
K11
K10
Key-on wakeup control register K1
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P13 key-on wakeup
control bit
Port P12 key-on wakeup
control bit
Port P11 key-on wakeup
control bit
Port P10 key-on wakeup
control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
K23
K22
K21
K20
Key-on wakeup control register K2
Return by level
Return by edge
Key-on wakeup not used
Key-on wakeup used
Return by level
Return by edge
Key-on wakeup not used
Key-on wakeup used
INT1 pin
return condition selection bit
INT1 pin
key-on wakeup control bit
INT0 pin
return condition selection bit
INT0 pin
key-on wakeup control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
R/W
TAK0/
TK0A
R/W
TAK1/
TK1A
R/W
TAK2/
TK2A
Rev.2.00 Jul 27, 2004 page 71 of 159
REJ03B0091-0200Z
4524 Group
PU03
PU02
PU01
PU00
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P03 pull-up transistor
control bit
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
Pull-up control register PU0 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
PU13
PU12
PU11
PU10
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
Pull-up control register PU1 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
I13
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
Interrupt control register I1 R/W
TAI1/TI1A
at power down : state retained
at reset : 00002
INT0 pin input disabled
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
0
1
0
1
0
1
0
1
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
Interrupt control register I2 R/W
TAI2/TI2A
at power down : state retained
at reset : 00002
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
R/W
TAPU0/
TPU0A
R/W
TAPU1/
TPU1A
Rev.2.00 Jul 27, 2004 page 72 of 159
REJ03B0091-0200Z
4524 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
•On-chip oscillator (internal oscillator)
•Ceramic resonator
•RC oscillation circuit
•Quartz-crystal oscillation circuit
•Multi-plexer (clock selection circuit)
•Frequency divider
•Internal clock generating circuit
Fig. 58 Clock control circuit structure
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 58 shows the structure of the clock control circuit.
The 4524 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the main clock (f(XIN)) of the 4524 Group. The CMCK instruction or
CRCK instruction is executed to select the ceramic resonator or
RC oscillator, respectively.
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
MR3, MR2
00
01
10
11
QS
QR
QS
R
CRCK instruction
QS
R
CMCK instruction
QS
R
Internal reset signal
XOUT
XIN
Wait time
control circuit
(Note 2)
Program start
signal
Key-on wakeup signal
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed
after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from power down.
EPOF instruction POF2 instruction
+
XCOUT
XCIN
QS
R
EPOF instruction POF instruction
+
T5F flag
MR1
1
MR0
0
System clock (STCK)
Instruction clock
(INSTCK)
Multi-plexer
Quartz-crystal
oscillation circuit
On-chip oscillator
(internal oscillator)
(Note 1)
Ceramic
oscillation circuit
RC oscillation
circuit
Internal clock
generating circuit
(divided by 3)
Divided by 2
Divided by 4
Divided by 8
Division circuit
Rev.2.00 Jul 27, 2004 page 73 of 159
REJ03B0091-0200Z
4524 Group
Fig. 59 Switch to ceramic oscillation/RC oscillation
Fig. 60 Handling of XIN and XOUT when operating on-chip oscillator
Fig. 61 Ceramic resonator external circuit
Fig. 62 External RC oscillation circuit
Execute the CMCK instruc-
tion in program.
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
(A feedback resistor is built-in.)
Use the resonator manu-
facturer’s recommended value
because constants such as ca-
pacitance depend on the
resonator.
(1) Main clock generating circuit (f(XIN))
The ceramic resonator or RC oscillation can be used for the main
clock of this MCU.
After system is released from reset, the MCU starts operation by
the clock output from the on-chip oscillator which is the internal os-
cillator.
When the ceramic resonator is used, execute the CMCK instruc-
tion. When the RC oscillation is used, execute the CRCK
instruction. The oscillation circuit by the CMCK or CRCK instruction
is valid only at once. The oscillation circuit corresponding to the first
executed one of these two instructions is valid. Other oscillation cir-
cuit and the on-chip oscillator stop.
Execute the CMCK or the CRCK instruction in the initial setting routine
of program (executing it in address 0 in page 0 is recommended).
Also, when the CMCK or the CRCK instruction is not executed in pro-
gram, this MCU operates by the on-chip oscillator.
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the main clock
(f(XIN)) without using the ceramic resonator or the RC oscillation,
connect XIN pin to VSS and leave XOUT pin open (Figure 60).
The clock frequency of the on-chip oscillator depends on the supply
voltage and the operation temperature range.
Be careful that margin of frequencies when designing application
products.
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), con-
nect the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. Then, execute the CMCK instruction.
A feedback resistor is built in between pins XIN and XOUT (Figure
61).
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C
at the shortest distance and leave XOUT pin open. Then, execute
the CRCK instruction (Figure 62).
The frequency is affected by a capacitor, a resistor and a micro-
computer. So, set the constants within the range of the frequency
limits.
*
Reset
On-chip oscillator
operation
C
M
C
K
i
n
s
t
r
u
c
t
i
o
nCRCK instruction
• Ceramic resonator valid
• On-chip oscillator stop
• RC oscillation stop
•
R
C
o
s
c
i
l
l
a
t
i
o
n
v
a
l
i
d
•
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
s
t
o
p
•
C
e
r
a
m
i
c
r
e
s
o
n
a
t
o
r
s
t
o
p
M34524
XI
NXO
U
T*
Do not use the CMCK instruction
and CRCK instruction in program.
M34524
X
IN
X
OUT
Rd
C
I
N
C
O
U
T
M
3
4
5
2
4
XI
NXO
U
T
R
C
*E
x
e
c
u
t
e
t
h
e
C
R
C
K
i
n
s
t
r
u
c
t
i
o
n
i
n
p
r
o
g
r
a
m
.
Rev.2.00 Jul 27, 2004 page 74 of 159
REJ03B0091-0200Z
4524 Group
(5) External clock
When the external clock signal is used as the main clock (f(XIN)),
connect the XIN pin to the clock source and leave XOUT pin open.
Then, execute the CMCK instruction (Figure 63).
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using the
ceramic resonator (refer to the recommended operating condition).
Also, note that the power down function (POF or POF2 instruction)
cannot be used when using the external clock.
(6) Sub-clock generating circuit f(XCIN)
The quartz-crystal oscillator can be used for the sub-clock signal
f(XCIN). Connect a quartz-crystal oscillator and this external circuit
to pins XCIN and XCOUT at the shortest distance. A feedback resis-
tor is built in between pins XCIN and XCOUT (Figure 64).
(7) Clock control register MR
Register MR controls system clock. Set the contents of this register
through register A with the TMRA instruction. In addition, the TAMR
instruction can be used to transfer the contents of register MR to
register A.
Table 24 Clock control register MR
Fig. 63 External clock input circuit
Note : “R” represents read enabled, and “W” represents write enabled.
M
3
4
5
2
4
XIN XO
U
T
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
VD
D
VS
S
E
x
e
c
u
t
e
t
h
e
C
M
C
K
i
n
s
t
r
u
c
t
i
o
n
i
n
p
r
o
g
r
a
m
.
*
Fig. 64 External quartz-crystal circuit
M
3
4
5
2
4
XC
IN XC
OU
T
Rd
CI
NCO
U
T
MR3
Clock control register MR
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock oscillation enabled
Main clock oscillation stop
Main clock (f(XIN) or f(RING))
Sub-clock (f(XCIN))
at reset : 11002at power down : state retained
MR3
0
0
1
1
R/W
TAMR/
TMRA
Main clock oscillation circuit control bit
System clock selection bit
Operation mode selection bits
0
1
0
1
MR2
0
1
0
1
MR1
MR0
MR2
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
(A feedback resistor is built-in.)
Use the quartz-crystal manu-
facturer’s recommended value
because constants such as ca-
pacitance depend on the
resonator.
Rev.2.00 Jul 27, 2004 page 75 of 159
REJ03B0091-0200Z
4524 Group
➈Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or re-
load regiser R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
Timer 4
Avoid a timing when timer 4 underflows to stop timer 4.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
Timer 5
Stop timer 5 counting to change its count source.
Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
Watchdog timer
•The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, stop the
watchdog timer function and execute the DWDT instruction, the
WRST instruction continuously, and clear the WEF flag to “0”.
•The watchdog timer function is valid after system is returned from
the power down state. When not using the watchdog timer func-
tion, stop the watchdog timer function and execute the DWDT
instruction and the WRST instruction continuously every system
is returned from the power down state.
• When the watchdog timer function and power down function are
used at the same time, initialize the flag WDF1 with the WRST
instruction before system enters into the power down state.
Multifunction
•Be careful that the output of ports D8 and D9 can be used even
when INT0 and INT1 pins are selected.
•Be careful that the input of ports D4–D6 can be used even when
SIN, SOUT and SCK pins are selected.
•Be careful that the input/output of port D7 can be used even
when input of CNTR0 pin are selected.
•Be careful that the input of port D7 can be used even when out-
put of CNTR0 pin are selected.
•Be careful that the “H” output of port C can be used even when
output of CNTR1 pin are selected.
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1
µ
F) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁Register initial values 1
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂Register initial values 2
The initial value of the following registers are undefined at power
down. After system is returned from power down, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accord-
ingly, be careful not to over the stack when performing these
operations together.
➄Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
➅Timer count source
Stop timer 1, 2, 3, 4 and LC counting to change its count source.
➆Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
➇Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the data
write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its
data.
10
13
11
12
14
15
Rev.2.00 Jul 27, 2004 page 76 of 159
REJ03B0091-0200Z
4524 Group
D8/INT0 pin
❶ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of reg-
ister I1 in program, be careful about the following notes.
• Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 65➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
65➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 65➂).
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid...........➀
LA 8 ; (1✕✕✕2)
TI1A ; Control of INT0 pin input is changed
NOP ........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 65 External 0 interrupt program example-1
❷ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the power down function
is selected and the input of INT0 pin is disabled, be careful about
the following notes.
• When the input of INT0 pin is disabled, invalidate the key-on
wakeup function of INT0 pin (register K20 = “0”) before system
goes into the power down mode. (refer to Figure 66➀).
•••
•••
LA 0 ; (✕✕✕02)
TK2A ; INT0 key-on wakeup invalid ........... ➀
DI
EPOF
POF2 ; RAM back-up
✕ : these bits are not used here.
Fig. 66 External 0 interrupt program example-2
•••
•••
❸ Note on bit 2 of register I1
When the interrupt valid waveform of the D8/INT0 pin is changed
with the bit 2 of register I1 in program, be careful about the fol-
lowing notes.
• Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 67➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
67➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 67➂).
LA 4 ; (✕✕✕02)
TV1A ; The SNZ0 instruction is valid...........➀
LA 12 ; (✕1✕✕2)
TI1A ; Interrupt valid waveform is changed
NOP ........................................................... ➁
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 67 External 0 interrupt program example-3
•••
•••
16
Rev.2.00 Jul 27, 2004 page 77 of 159
REJ03B0091-0200Z
4524 Group
D9/INT1 pin
❶ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in program, be careful about the following notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 68➀)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
68➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 68➂).
LA 4 ; (✕✕0✕2)
TV1A ; The SNZ1 instruction is valid...........➀
LA 8 ; (1✕✕✕2)
TI2A ; Control of INT1 pin input is changed
NOP ........................................................... ➁
SNZ1 ; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 68 External 1 interrupt program example-1
❷ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared, the power down function
is selected and the input of INT1 pin is disabled, be careful about
the following notes.
• When the input of INT1 pin is disabled, invalidate the key-on
wakeup function of INT1 pin (register K22 = “0”) before system
goes into the power down mode. (refer to Figure 69➀).
•••
•••
LA 0 ; (✕0✕✕2)
TK2A ; INT1 key-on wakeup invalid ........... ➀
DI
EPOF
POF2 ; RAM back-up
✕ : these bits are not used here.
Fig. 69 External 1 interrupt program example-2
•••
•••
❸ Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in program, be careful about the fol-
lowing notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 70➀)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
70➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 70➂).
LA 4 ; (✕✕0✕2)
TV1A ; The SNZ1 instruction is valid...........➀
LA 12 ; (✕1✕✕2)
TI2A ; Interrupt valid waveform is changed
NOP ........................................................... ➁
SNZ1 ; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP ........................................................... ➂
✕ : these bits are not used here.
Fig. 70 External 1 interrupt program example-3
•••
•••
17
A/D converter-1
• When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
•Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conver-
sion mode.
•The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
LA 8 ; (✕0✕✕2)
TV2A ; The SNZAD instruction is valid........➀
LA 0 ; (0✕✕✕2)
TQ1A ; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
SNZAD
NOP
✕ : these bits are not used here.
Fig. 71 A/D converter program example-3
•••
•••
18
Rev.2.00 Jul 27, 2004 page 78 of 159
REJ03B0091-0200Z
4524 Group
23
25
21
22
24
Fig. 72 Analog input external circuit example-1
A/D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog volt-
age is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may
not be obtained. Therefore, reduce the impedance or, connect a
capacitor (0.01 µF to 1 µF) to analog input pins (Figure 72).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 73. In addition, test
the application products sufficiently.
S
e
n
s
o
rA
I
N
Apply the voltage withiin the specifications
to an analog input pin.
Sensor A
I
N
A
b
o
u
t
1
kΩ
19
Fig. 73 Analog input external circuit example-2
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor
added to the power supply pin, the following case may cause
program failure (Figure 74);
supply voltage does not fall below to VRST, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage
is once reduced below to VRST and re-goes up after that.
POF and POF2 instructions
When the POF or POF2 instruction is executed continuously af-
ter the EPOF instruction, system enters the power down state.
Note that system cannot enter the power down state when ex-
ecuting only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction and the POF or POF2
instruction continuously.
Power-on reset
When the built-in power-on reset circuit is used, the time for the supply
voltage to rise from 0 V to 2.0 V must be set to 100 µs or less. If the ris-
ing time exceeds 100 µs, connect a capacitor between the RESET pin
and VSS at the shortest distance, and input “L” level to RESET pin until
the value of supply voltage reaches the minimum operating voltage.
Clock control
Execute the CMCK or the CRCK instruction in the initial setting routine
of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be
selected only at once. The oscillation circuit corresponding to the
first executed one of these two instruction is valid. Other oscilla-
tion circuits and the on-chip oscillator stop.
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that margin of frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released from re-
set is generated by the on-chip oscillator clock. When considering the
oscillation stabilize wait time after system is released from reset, be
careful that the margin of frequency of the on-chip oscillator clock.
External clock
When the external clock signal is used as the main clock (f(XIN)), note
that the power down mode (POF or POF2 instruction) cannot be used.
Difference between Mask ROM version and One Time PROM version
Mask ROM version and One Ti me PROM version have some dif-
ference of the following characteristics within the limits of an
electrical property by difference of a manufacture process, built-
in ROM, and a layout pattern.
• a characteristic value • the amount of noise-proof
• a margin of operation • noise radiation, etc.,
Accordingly, be careful of them when swithcing.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
Fig. 74 VDD and VRST
V
DD
Recommended
operatng condition
min.value
No reset
Program failure may occur.
V
RST
V
DD
Recommended
operatng condition
min.value
V
RST
→ Normal operation
Reset
20
26
27
Rev.2.00 Jul 27, 2004 page 79 of 159
REJ03B0091-0200Z
4524 Group
CONTROL REGISTERS
I13
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
Interrupt control register I1 R/W
TAI1/TI1A
at power down : state retained
at reset : 00002
INT0 pin input disabled
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V13
V12
V11
V10
V23
V22
V21
V20
Timer 4, serial I/O interrupt enable bit
A/D interrupt enable bit
Timer 5 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2 at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
at power down : 00002at reset : 00002R/W
TAV1/TV1A
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
Interrupt control register I2 R/W
TAI2/TI2A
at power down : state retained
at reset : 00002
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to “1”.
R/W
TAV2/TV2A
I30Timer 4, serial I/O interrupt source selection
bit
Interrupt control register I3 R/W
TAI3/TI3A
at power down : state retained
at reset : 02
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
0
1
Rev.2.00 Jul 27, 2004 page 80 of 159
REJ03B0091-0200Z
4524 Group
W21
0
0
1
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating Count source
System clock (STCK)
Prescaler output (ORCLK)
Timer 1 underflow signal (T1UDF)
PWM signal (PWMOUT)
CNTR0 output control bit
Timer 2 control bit
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
Timer control register W2 at power down : state retained
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
W23
W22
W21
W20
MR3
Clock control register MR
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock oscillation enabled
Main clock oscillation stop
Main clock (f(XIN) or f(RING))
Sub-clock (f(XCIN))
at reset : 11002at power down : state retained
MR3
0
0
1
1
R/W
TAMR/
TMRA
Main clock oscillation circuit control bit
System clock selection bit
Operation mode selection bits
0
1
0
1
MR2
0
1
0
1
MR1
MR0
MR2
0
1Stop (state initialized)
Operating
Prescaler control bit
Timer control register PA W
TPAA
at power down : 02
at reset : 02
PA0
W11
0
0
1
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
Timer 5 underflow signal (T5UDF)
CNTR0 input
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 1 control bit
Timer 1 count source selection bits
0
1
0
1
W10
0
1
0
1
Timer control register W1 R/W
TAW1/TW1A
at power down : state retained
at reset : 00002
W13
W12
W11
W10
W31
0
0
1
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Timer 3 count auto-stop circuit selection
bit (Note 3)
Timer 3 control bit
Timer 3 count source selection bits
(Note 4)
0
1
0
1
W30
0
1
0
1
Timer control register W3 at power down : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW2/TW2A
R/W
TAW3/TW3A
Rev.2.00 Jul 27, 2004 page 81 of 159
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4524 Group
Stop (state retained)
Operating
Bit 4 (T54) of timer 5
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D7(I/O)/CNTR0 input
CNTR0 input/output/D7 (input)
Timer LC control bit
Timer LC count source selection bit
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
0
1
0
1
0
1
0
1
Timer control register W6 at power down : state retained
at reset : 00002
W63
W62
W61
W60
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
CNTR1 output control bit
PWM signal
“H” interval expansion function control bit
Timer 4 control bit
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
W43
W42
W41
W40
W51
0
0
1
1
Not used
Timer 5 control bit
Timer 5 count value selection bits
0
1
0
1
W50
0
1
0
1
Timer control register W5 at power down : state retained
at reset : 00002
W53
W52
W51
W50
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
This bit has no function, but read/write is enabled.
Stop (state initialized)
Operating Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
R/W
TAW4/TW4A
Timer control register W4 at power down : 00002
at reset : 00002
R/W
TAW5/TW5A
R/W
TAW6/TW6A
Rev.2.00 Jul 27, 2004 page 82 of 159
REJ03B0091-0200Z
4524 Group
J13
0
0
1
1
J11
0
0
1
1
Serial I/O synchronous clock selection bits
Serial I/O port function selection bits
J12
0
1
0
1
J10
0
1
0
1
Serial I/O control register J1 at power down : state retained
at reset : 00002
J13
J12
J11
J10
Synchronous clock
Instruction clock (INSTCK) divided by 8
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (SCK input) Port function
D6, D5, D4 selected/SCK, SOUT, SIN not selected
SCK, SOUT, D4 selected/D6, D5, SIN not selected
SCK, D5, SIN selected/D6, SOUT, D4 not selected
SCK, SOUT, SIN selected/D6, D5, D4 not selected
R/W
TAJ1/TJ1A
Q12
0
0
0
0
1
1
1
1
A/D operation mode selection bit
Analog input pin selection bits
Q11
0
0
1
1
0
0
1
1
A/D control register Q1 at power down : state retained
at reset : 00002
Q13A/D conversion mode
Comparator mode
R/W
TAQ1/TQ1A
Q10
0
1
0
1
0
1
0
1
Q12
Q11
Q10
Analog input pins
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
P23
AIN3
P22
AIN2
P21
AIN1
P20
AIN0
P23/AIN3 pin function selection bit
P22/AIN2 pin function selection bit
P21/AIN1 pin function selection bit
P20/AIN0 pin function selection bit
0
1
0
1
0
1
0
1
Q23
Q22
Q21
Q20
R/W
TAQ2/TQ2A
A/D control register Q2 at power down : state retained
at reset : 00002
P33
AIN7
P32
AIN6
P31
AIN5
P30
AIN4
P33/AIN7 pin function selection bit
P32/AIN6 pin function selection bit
P31/AIN5 pin function selection bit
P30/AIN4 pin function selection bit
0
1
0
1
0
1
0
1
Q33
Q32
Q31
Q30
R/W
TAQ3/TQ3A
A/D control register Q3 at power down : state retained
at reset : 00002
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Jul 27, 2004 page 83 of 159
REJ03B0091-0200Z
4524 Group
Internal dividing resistor for LCD power
supply selection bit (Note 2)
LCD control bit
LCD control register L1
L13
L12
L11
L10
at reset : 00002at power down : state retained
0
1
0
1
L11
0
0
1
1
L10
0
1
0
1
Duty
1/2
1/3
1/4
Bias
1/2
1/3
1/3
LCD control register L2 at reset : 11112at power down : state retained W
TL2A
0
1
0
1
0
1
0
1
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
L23
L22
L21
L20
VLC3/SEG0 pin function switch bit (Note 3)
VLC2/SEG1 pin function switch bit (Note 4)
VLC1/SEG2 pin function switch bit (Note 4)
Internal dividing resistor for LCD power
supply control bit
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Off
On
Not available
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
R/W
TAL1/TL1A
PU03
PU02
PU01
PU00
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P03 pull-up transistor
control bit
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
Pull-up control register PU0 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
R/W
TAPU0/
TPU0A
PU13
PU12
PU11
PU10
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
Pull-up control register PU1 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
R/W
TAPU1/
TPU1A
LCD duty and bias selection bits
Rev.2.00 Jul 27, 2004 page 84 of 159
REJ03B0091-0200Z
4524 Group
FR03
FR02
FR01
FR00
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Ports P12, P13 output structure selection
bit
Ports P10, P11 output structure selection
bit
Ports P02, P03 output structure selection
bit
Ports P00, P01 output structure selection
bit
Port output structure control register FR0 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
FR13
FR12
FR11
FR10
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Port D3 output structure selection bit
Port D2 output structure selection bit
Port D1 output structure selection bit
Port D0 output structure selection bit
Port output structure control register FR1 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
FR23
FR22
FR21
FR20
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Port D7/CNTR0 output structure selection bit
Port D6/SCK output structure selection bit
Port D
5
/S
OUT
output structure selection bit
Port D4/SIN output structure selection bit
Port output structure control register FR2 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.
W
TFR0A
W
TFR1A
W
TFR2A
FR33
FR32
FR31
FR30
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Port P43 output structure selection bit
Port P42 output structure selection bit
Port P41 output structure selection bit
Port P40 output structure selection bit
Port output structure control register FR3 at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
W
TFR3A
Rev.2.00 Jul 27, 2004 page 85 of 159
REJ03B0091-0200Z
4524 Group
K03
K02
K01
K00
Key-on wakeup control register K0
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P03 key-on wakeup control bit
Port P02 key-on wakeup control bit
Port P01 key-on wakeup control bit
Port P00 key-on wakeup control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
R/W
TAK0/
TK0A
Note: “R” represents read enabled, and “W” represents write enabled.
K13
K12
K11
K10
Key-on wakeup control register K1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P13 key-on wakeup control bit
Port P12 key-on wakeup control bit
Port P11 key-on wakeup control bit
Port P10 key-on wakeup control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
K23
K22
K21
K20
Key-on wakeup control register K2
Returned by level
Returned by edge
Key-on wakeup invalid
Key-on wakeup valid
Returned by level
Returned by edge
Key-on wakeup invalid
Key-on wakeup valid
INT1 pin return condition selection bit
INT1 pin key-on wakeup control bit
INT0 pin return condition selection bit
INT0 pin key-on wakeup control bit
at reset : 00002at power down : state retained
0
1
0
1
0
1
0
1
R/W
TAK1/
TK1A
R/W
TAK2/
TK2A
Rev.2.00 Jul 27, 2004 page 86 of 159
REJ03B0091-0200Z
4524 Group
Symbol
A
B
DR
E
V1
V2
I1
I2
I3
MR
PA
W1
W2
W3
W4
W5
W6
J1
Q1
Q2
Q3
L1
L2
PU0
PU1
FR0
FR1
FR2
FR3
K0
K1
K2
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
RPS
R1
R2
R3
R4L
R4H
RLC
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Interrupt control register I3 (1 bit)
Clock control register MR (4 bits)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W5 (4 bits)
Timer control register W6 (4 bits)
Serial I/O control register J1 (4 bits)
A/D control register Q1 (4 bits)
A/D control register Q2 (4 bits)
A/D control register Q3 (4 bits)
LCD control register L1 (4 bits)
LCD control register L2 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Port output format control register FR0 (4 bits)
Port output format control register FR1 (4 bits)
Port output format control register FR2 (4 bits)
Port output format control register FR3 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 4 reload register (8 bits)
Timer 4 reload register (8 bits)
Timer LC reload register (4 bits)
Contents
Prescaler
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer LC
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Timer 4 interrupt request flag
Timer 5 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Power down flag
A/D conversion completion flag
Serial I/O transmit/receive completion flag
Port D (10 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Port P3 (4 bits)
Port P4 (4 bits)
Port C (1 bit)
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x
Symbol
PS
T1
T2
T3
T4
T5
TLC
T1F
T2F
T3F
T4F
T5F
WDF1
WEF
INTE
EXF0
EXF1
P
ADF
SIOF
D
P0
P1
P2
P3
P4
C
x
y
z
p
n
i
j
A3A2A1A0
←
↔
?
( )
—
M(DP)
a
p, a
C
+
x
INSTRUCTIONS
The 4524 Group has the 136 instructions. Each instruction is de-
scribed as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
Note :Some instructions of the 4524 Group has the skip function to unexecute the next described instruction. The 4524 Group just invalidates the next instruc-
tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
SYMBOL
The symbols shown below are used in the following list of instruc-
tion function and the machine instructions.
Rev.2.00 Jul 27, 2004 page 87 of 159
REJ03B0091-0200Z
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION
Group-
ing
RAM addresses
Mnemonic
XAMI j
TMA j
LA n
TABP p
AM
AMC
A n
AND
OR
SC
RC
SZC
CMA
RAR
Function
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← n
n = 0 to 15
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ← (A) + (M(DP))
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
(A) ← (A) + n
n = 0 to 15
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
(CY) ← 1
(CY) ← 0
(CY) = 0 ?
(A) ← (A)
→ CY → A3A2A1A0
Mnemonic
TAB
TBA
TAY
TYA
TEAB
TABE
TDA
TAD
TAZ
TAX
TASP
LXY x, y
LZ z
INY
DEY
TAM j
XAM j
XAMD j
Function
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
(E7–E4) ← (B)
(E3–E0) ← (A)
(B) ← (E7–E4)
(A) ← (E3–E0)
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
(A) ← (X)
(A2–A0) ← (SP2–SP0)
(A3) ← 0
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
(Z) ← z z = 0 to 3
(Y) ← (Y) + 1
(Y) ← (Y) – 1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
RAM to register transfer
Arithmetic operation
RAM to register transfer Register to register transfer
Group-
ing
Page
111, 132
121, 132
120, 132
130, 132
121, 132
112, 132
121, 132
113, 132
121, 132
120, 132
118, 132
98, 132
99, 132
98, 132
95, 132
116, 132
131, 132
131, 132
Page
131, 132
125, 132
98, 134
113, 134
92, 134
92, 134
92, 134
93, 134
100, 134
104, 134
102, 134
109, 134
95, 134
101, 134
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
Rev.2.00 Jul 27, 2004 page 88 of 159
REJ03B0091-0200Z
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Function
(Mj(DP)) ← 1
j = 0 to 3
(Mj(DP)) ← 0
j = 0 to 3
(Mj(DP)) = 0 ?
j = 0 to 3
(A) = (M(DP)) ?
(A) = n ?
n = 0 to 15
(PCL) ← a6–a0
(PCH) ← p
(PCL) ← a6–a0
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Comparison
operation
Subroutine operation Branch operation Bit operation
Return operation
Mnemonic
SB j
RB j
SZB j
SEAM
SEA n
B a
BL p, a
BLA p
BM a
BML p, a
BMLA p
RTI
RT
RTS
Group-
ing Page
103, 134
101, 134
109, 134
105, 134
105, 134
93, 136
93, 136
93, 136
94, 136
94, 136
94, 136
103, 136
103, 136
103, 136
Function
(INTE) ← 0
(INTE) ← 1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: NOP
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: NOP
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
(I1) ← (A)
(A) ← (I2)
(I2) ← (A)
(A0) ← (I30), (A3–A1) ← 0
(I30) ← (A0)
(PA0) ← (A0)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
Interrupt operation
Page
96, 138
96, 138
105, 138
105, 138
106, 138
106, 138
118, 138
128, 138
118, 138
128, 138
114, 138
123, 138
114, 138
123, 138
114, 138
123, 138
126, 138
119, 138
129, 138
119, 138
129, 138
119, 138
129, 138
Timer operation
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
Mnemonic
DI
EI
SNZ0
SNZ1
SNZI0
SNZI1
TAV1
TV1A
TAV2
TV2A
TAI1
TI1A
TAI2
TI2A
TAI3
TI3A
TPAA
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
Rev.2.00 Jul 27, 2004 page 89 of 159
REJ03B0091-0200Z
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing Function
(A) ← (W4)
(W4) ← (A)
(A) ← (W5)
(W5) ← (A)
(A) ← (W6)
(W6) ← (A)
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
(B) ← (T17–T14)
(A) ← (T13–T10)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
(B) ← (T27–T24)
(A) ← (T23–T20)
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
(B) ← (T37–T34)
(A) ← (T33–T30)
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
(B) ← (T47–T44)
(A) ← (T43–T40)
(R4L7–R4L4) ← (B)
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
Mnemonic
TAW4
TW4A
TAW5
TW5A
TAW6
TW6A
TABPS
TPSAB
TAB1
T1AB
TAB2
T2AB
TAB3
T3AB
TAB4
T4AB
Timer operation
Page
119, 138
129, 138
120, 140
130, 140
121, 140
130, 140
113, 140
126, 140
111, 140
109, 140
111, 140
110, 140
112, 140
110, 140
112, 140
110, 140
Page
110, 140
127, 140
128, 140
111, 140
125, 140
107, 142
107, 142
107, 142
108, 142
108, 142
97, 142
99, 142
97, 142
99, 142
97, 142
100, 142
97, 142
100, 142
98, 142
100, 142
Input/Output operation
Mnemonic
T4HAB
TR1AB
TR3AB
T4R4L
TLCA
SNZT1
SNZT2
SNZT3
SNZT4
SNZT5
IAP0
OP0A
IAP1
OP1A
IAP2
OP2A
IAP3
OP3A
IAP4
OP4A
Function
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
(R17–R14) ← (B)
(R13–R10) ← (A)
(R37–R34) ← (B)
(R33–R30) ← (A)
(T47–T44) ← (R4L7–R4L4)
(T43–T40) ← (R4L3–R4L0)
(LC) ← (A)
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V23 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0
V21 = 0: (T5F) = 1 ?
After skipping, (T5F) ← 0
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
(A) ← (P2)
(P2) ← (A)
(A) ← (P3)
(P3) ← (A)
(A) ← (P4)
(P4) ← (A)
Timer operation
Rev.2.00 Jul 27, 2004 page 90 of 159
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4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing Page
94, 142
102, 142
104, 142
109, 142
102, 142
104, 142
117, 142
126, 142
117, 142
126, 142
124, 144
115, 144
124, 144
115, 144
124, 144
115, 144
122, 144
122, 144
122, 144
122, 144
95, 144
95, 144
116, 144
125, 144
Page
116, 144
124, 144
124, 144
113, 144
128, 144
108, 144
107, 144
115, 144
123, 144
112, 146
116, 146
114, 146
92, 146
106, 146
117, 146
127, 146
117, 146
127, 146
118, 146
127, 146
A/D operation Serial I/O operation
Input/Output operation
Function
(D) ← 1
(D(Y)) ← 0
(Y) = 0 to 9
(D(Y)) ← 1
(Y) = 0 to 9
(D(Y)) = 0 ?
(Y) = 0 to 9
(C) ← 0
(C) ← 1
(A) ← (PU0)
(PU0) ← (A)
(A) ← (PU1)
(PU1) ← (A)
(A) ← (K0)
(K0) ← (A)
(A) ← (K1)
(K1) ← (A)
(A) ← (K2)
(K2) ← (A)
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
Ceramic resonator selected
RC oscillator selected
(A) ← (MR)
(MR) ← (A)
Mnemonic
CLD
RD
SD
SZD
RCP
SCP
TAPU0
TPU0A
TAPU1
TPU1A
TAK0
TK0A
TAK1
TK1A
TAK2
TK2A
TFR0A
TFR1A
TFR2A
TFR3A
CMCK
CRCK
TAMR
TMRA
Function
(A) ← (L1)
(L1) ← (A)
(L2) ← (A)
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
(SIOF) ← 0
Serial I/O starting
V23=0: (SIOF)=1?
After skipping, (SIOF) ← 0
(A) ← (J1)
(J1) ← (A)
In A/D conversion mode ,
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
(ADF) ← 0
A/D conversion starting
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
(A) ← (Q1)
(Q1) ← (A)
(A) ← (Q2)
(Q2) ← (A)
(A) ← (Q3)
(Q3) ← (A)
Mnemonic
TAL1
TL1A
TL2A
TABSI
TSIAB
SST
SNZSI
TAJ1
TJ1A
TABAD
TALA
TADAB
ADST
SNZAD
TAQ1
TQ1A
TAQ2
TQ2A
TAQ3
TQ3A
LCD operation
Clock operation
Rev.2.00 Jul 27, 2004 page 91 of 159
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4524 Group
Mnemonic
NOP
POF
POF2
EPOF
SNZP
DWDT
WRST
RBK*
SBK*
SVDE
Function
(PC) ← (PC) + 1
Transition to clock operating mode
Transition to RAM back-up mode
POF, POF2 instructions valid
(P) = 1 ?
Stop of watchdog timer function
enabled
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
When TABP p instruction is ex-
ecuted, P6 ← 0
When TABP p instruction is ex-
ecuted, P6 ← 1
At power down mode, voltage
drop detection circuit valid
Other operation
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing Page
99, 146
101, 146
101, 146
96, 146
106, 146
96, 146
130, 146
102, 146
104, 146
108, 146
Note: *(RBK, SBK) cannot be used in the M34524M8.
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
000110nnnn 06n 11
–Overflow = 0
Grouping: Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
Operation: (A) ← (A) + n
n = 0 to 15
ADST (A/D conversion STart)
1010011111 29F 11
––
Grouping: A/D conversion operation
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the compara-
tor operation at the comparator mode (Q13
= 1) is started.
Operation: (ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
AM (Add accumulator and Memory)
0000001010 00A 11
––
Grouping: Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
Operation: (A) ← (A) + (M(DP))
AMC (Add accumulator, Memory and Carry)
0000001011 00B 11
0/1 –
Grouping: Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in regis-
ter A and carry flag CY.
Operation: (A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
AND (logical AND between accumulator and memory)
0000011000 018 11
––
Grouping: Arithmetic operation
Description: Takes the AND operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.
Operation: (A) ← (A) AND (M(DP))
B a (Branch to address a)
011a6a5a4a3a2a1a01a 11
––
Grouping: Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note: Specify the branch address within the page
including this instruction.
Operation: (PCL) ← a6 to a0
BL p, a (Branch Long to address a in page p)
00111p4p3p2p1p00p 22
––
Grouping: Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
Operation: (PCH) ← p
(PCL) ← a6 to a0
BLA p (Branch Long to address (D) + (A) in page p)
0000010000 010 22
––
Grouping: Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers D and A in page p.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
8
+a
216
1p6p5a6a5a4a3a2a1a0a
E
+p
Operation: (PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
216
1p6p5p400p3p2p1p0pp
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
2
+p p
+a
2
+p
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
BM a (Branch and Mark to address a in page 2)
010a6a5a4a3a2a1a01aa 11
––
Grouping: Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note: Subroutine extending from page 2 to an-
other page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
Operation: (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a (Branch and Mark Long to address a in page p)
00110p4p3p2p1p00p 22
––
Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
Operation: (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
0000110000 030 22
––
Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci-
fied by registers D and A in page p.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for
M34524MC, and p is 0 to 127 for M34524ED.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
0000010001 011 11
––
Grouping: Input/Output operation
Description: Sets (1) to port D.
Operation: (D) ← 1
216
1p6p5a6a5a4a3a2a1a0a
C
+p
Operation: (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
216
1p6p5p400p3p2p1p0pp
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
2
+p p
+a
2
+p
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
CMA (CoMplement of Accumulator)
0000011100 01C 11
––
Grouping: Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
Operation: (A) ← (A)
CMCK (Clock select: ceraMic oscillation ClocK)
1010011010 29A 11
––
Grouping: Other operation
Description: Selects the ceramic oscillation circuit and
stops the on-chip oscillator.
Operation: Ceramic oscillation circuit selected
CRCK (Clock select: Rc oscillation ClocK)
1010011011 29B 11
––
Grouping: Other operation
Description: Selects the RC oscillation circuit and stops
the on-chip oscillator.
Operation: RC oscillation circuit selected
DEY (DEcrement register Y)
0000010111 017 11
–(Y) = 15
Grouping: RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
Operation: (Y) ← (Y) – 1
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
DI (Disable Interrupt)
0000000100 004 11
––
Grouping: Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note: Interrupt is disabled by executing the DI in-
struction after executing 1 machine cycle.
Operation: (INTE) ← 0
DWDT (Disable WatchDog Timer)
1010011100 29C 11
––
Grouping: Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
Operation: Stop of watchdog timer function enabled
EPOF (Enable POF instruction)
0001011011 05B 11
––
Grouping: Other operation
Description: Makes the immediate after POF or POF2
instruction valid by executing the EPOF in-
struction.
Operation: POF instruction, POF2 instruction valid
EI (Enable Interrupt)
0000000101 005 11
––
Grouping: Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note: Interrupt is enabled by executing the EI in-
struction after executing 1 machine cycle.
Operation: (INTE) ← 1
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
IAP0 (Input Accumulator from port P0)
1001100000 260 11
––
Grouping: Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
1001100001 261 11
––
Grouping: Input/Output operation
Description: Transfers the input of port P1 to register A.
Operation: (A) ← (P1)
IAP2 (Input Accumulator from port P2)
1001100010 262 11
––
Grouping: Input/Output operation
Description: Transfers the input of port P2 to register A.
Operation: (A) ← (P2)
Operation: (A) ← (P0)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP3 (Input Accumulator from port P3)
1001100011 263 11
––
Grouping: Input/Output operation
Description: Transfers the input of port P3 to register A.
Operation: (A) ← (P3)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
INY (INcrement register Y)
0000010011 013 11
–(Y) = 0
Grouping: RAM addresses
Description: Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
Operation: (Y) ← (Y) + 1
LA n (Load n in Accumulator)
000111nnnn 07n 11
–Continuous
description
Grouping: Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA in-
struction is executed and other LA
instructions coded continuously are
skipped.
Operation: (A) ← n
n = 0 to 15
LXY x, y (Load register X and Y with x and y)
11x3x2x1x0y3y2y1y03xy 11
–Continuous
description
Grouping: RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instruc-
tions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continu-
ously are skipped.
Operation: (X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
IAP4 (Input Accumulator from port P4)
1001100100 264 11
––
Grouping: Input/Output operation
Description: Transfers the input of port P4 to register A.
Operation: (A) ← (P4)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
LZ z (Load register Z with z)
00010010z1z004 11
––
Grouping: RAM addresses
Description: Loads the value z in the immediate field to
register Z.
Operation: (Z) ← z z = 0 to 3
8
+z
NOP (No OPeration)
0000000000 000 11
––
Grouping: Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
Operation: (PC) ← (PC) + 1
OP0A (Output port P0 from Accumulator)
1000100000 220 11
––
Grouping: Input/Output operation
Description: Outputs the contents of register A to port
P0.
Operation: (P0) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
1000100001 221 11
––
Grouping: Input/Output operation
Description: Outputs the contents of register A to port
P1.
Operation: (P1) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
OR (logical OR between accumulator and memory)
0000011001 019 11
––
Grouping: Arithmetic operation
Description: Takes the OR operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.
Operation: (A) ← (A) OR (M(DP))
OP4A (Output port P4 from Accumulator)
1000100100 224 11
––
Grouping: Input/Output operation
Description: Outputs the contents of register A to port
P4.
Operation: (P4) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
1000100010 222 11––
Grouping: Input/Output operation
Description: Outputs the contents of register A to port
P2.
Operation: (P2) ← (A)
OP3A (Output port P3 from Accumulator)
1000100011 223 11
––
Grouping: Input/Output operation
Description: Outputs the contents of register A to port
P3.
Operation: (P3) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
POF (Power OFf1)
0000000010 002 11
––
Grouping: Other operation
Description: Puts the system in clock operating state by
executing the POF instruction after execut-
ing the EPOF instruction.
Note: If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
POF2 (Power OFf2)
0000001000 008 11
––
Grouping: Other operation
Description: Puts the system in RAM back-up state by
executing the POF2 instruction after ex-
ecuting the EPOF instruction.
Note: If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
Operation: Transition to RAM back-up mode
Operation: Transition to clock operating mode
RAR (Rotate Accumulator Right)
0000011101 01D 11
0/1 –
Grouping: Arithmetic operation
Description: Rotates 1 bit of the contents of register A in-
cluding the contents of carry flag CY to the
right.
Operation: → CY → A3A2A1A0
RB j (Reset Bit)
00010011j j 04 11
––
Grouping: Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
Operation: (Mj(DP)) ← 0
j = 0 to 3
C
+j
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
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4524 Group
RD (Reset port D specified by register Y)
0000010100 014 11
––
Grouping: Input/Output operation
Description: Clears (0) to a bit of port D specified by reg-
ister Y.
Operation: (D(Y)) ← 0
However,
(Y) = 0 to 9
RC (Reset Carry flag)
0000000110 006 11
0–
Grouping: Arithmetic operation
Description: Clears (0) to carry flag CY.
Operation: (CY) ← 0
RCP (Reset Port C)
1010001100 28C 11
––
Grouping: Input/Output operation
Description: Clears (0) to port C.
Operation: (C) ← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RBK (Reset Bank flag)
0001000000 040 11
––
Grouping: Other operation
Description: Sets referring data area to pages 0 to 63
when the TABP p instruction is executed.
Note: This instruction cannot be used in M34524M8.
Operation: When TABP p instruction is executed, P6 ← 0
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 103 of 159
REJ03B0091-0200Z
4524 Group
RTI (ReTurn from Interrupt)
0001000110 046 11
––
Grouping: Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY in-
struction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
0001000101 045 12
–Skip at uncondition
Grouping: Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next in-
struction at uncondition.
Operation: (PC) ← (SK(SP))
(SP) ← (SP) – 1
Operation: (PC) ← (SK(SP))
(SP) ← (SP) – 1
SB j (Set Bit)
00010111j j 05 11
––
Grouping: Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
Operation: (Mj(DP)) ← 1
j = 0 to 3
C
+j
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
0001000100 044 12
––
Grouping: Return operation
Description: Returns from subroutine to the routine
called the subroutine.
Operation: (PC) ← (SK(SP))
(SP) ← (SP) – 1
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 104 of 159
REJ03B0091-0200Z
4524 Group
SCP (Set Port C)
1010001101 28D 11
––
Grouping: Input/Output operation
Description: Sets (1) to port C.
Operation: (C) ← 1
SD (Set port D specified by register Y)
0000010101 015 11
––
Grouping: Input/Output operation
Description: Sets (1) to a bit of port D specified by regis-
ter Y.
Operation: (D(Y)) ← 1
(Y) = 0 to 9
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SC (Set Carry flag)
0000000111 007 11
1–
Grouping: Arithmetic operation
Description: Sets (1) to carry flag CY.
Operation: (CY) ← 1
SBK (Set Bank flag)
0001000001 041 11
––
Grouping: Other operation
Description: Sets referring data area to pages 64 to 127
when the TABP p instruction is executed.
Note: This instruction cannot be used in M34524M8.
In M34524MC, referring data area is pages 64 to 95.
Operation: When TABP p instruction is executed, P6 ← 1
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 105 of 159
REJ03B0091-0200Z
4524 Group
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
0000111000 038 11
–V10 = 0: (EXF0) = 1
Grouping: Interrupt operation
Description: When V10 = 0 : Skips the next instruction
when external 0 interrupt request flag EXF0
is “1.” After skipping, clears (0) to the EXF0
flag. When the EXF0 flag is “0,” executes
the next instruction.
When V10 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEA n (Skip Equal, Accumulator with immediate data n)
0000100101 025 22
–(A) = n
Grouping: Comparison operation
Description: Skips the next instruction when the con-
tents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the con-
tents of register A is not equal to the value n
in the immediate field.
Operation: (A) = n ?
n = 0 to 15
216
000111nnnn 07n
SEAM (Skip Equal, Accumulator with Memory)
0000100110 026 11
–(A) = (M(DP))
Grouping: Comparison operation
Description: Skips the next instruction when the con-
tents of register A is equal to the contents of
M(DP).
Executes the next instruction when the con-
tents of register A is not equal to the
contents of M(DP).
Operation: (A) = (M(DP)) ?
SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag)
0000111001 039 11
–V11 = 0: (EXF1) = 1
Grouping: Interrupt operation
Description: When V11 = 0 : Skips the next instruction
when external 1 interrupt request flag EXF1
is “1.” After skipping, clears (0) to the EXF1
flag. When the EXF1 flag is “0,” executes
the next instruction.
When V11 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
(V11 : bit 1 of the interrupt control register V1)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 106 of 159
REJ03B0091-0200Z
4524 Group
SNZP (Skip if Non Zero condition of Power down flag)
0000000011 003 11
–(P) = 1
Grouping: Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains un-
changed.
Executes the next instruction when the P
flag is “0.”
Operation: (P) = 1 ?
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
1010000111 287 11
–V22 = 0: (ADF) = 1
Grouping: A/D conversion operation
Description: When V22 = 0 : Skips the next instruction
when A/D conversion completion flag ADF
is “1.” After skipping, clears (0) to the ADF
flag. When the ADF flag is “0,” executes the
next instruction.
When V22 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
0000111010 03A 11
–I12 = 0 : (INT0) = “L”
I12 = 1 : (INT0) = “H”
Grouping: Interrupt operation
Description: When I12 = 0 : Skips the next instruction
when the level of INT0 pin is “L.” Executes
the next instruction when the level of INT0
pin is “H.”
When I12 = 1 : Skips the next instruction
when the level of INT0 pin is “H.” Executes
the next instruction when the level of INT0
pin is “L.”
Operation: I12 = 0 : (INT0) = “L” ?
I12 = 1 : (INT0) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin)
0000111011 03B 11–I22 = 0 : (INT1) = “L”
I22 = 1 : (INT1) = “H”
Grouping: Interrupt operation
Description: When I22 = 0 : Skips the next instruction
when the level of INT1 pin is “L.” Executes
the next instruction when the level of INT1
pin is “H.”
When I22 = 1 : Skips the next instruction
when the level of INT1 pin is “H.” Executes
the next instruction when the level of INT1
pin is “L.”
Operation: I22 = 0 : (INT1) = “L” ?
I22 = 1 : (INT1) = “H” ?
(I22 : bit 2 of the interrupt control register I2)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 107 of 159
REJ03B0091-0200Z
4524 Group
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
1010000000 280 11
–V12 = 0: (T1F) = 1
Grouping: Timer operation
Description: When V12 = 0 : Skips the next instruction
when timer 1 interrupt request flag T1F is
“1.” After skipping, clears (0) to the T1F
flag. When the T1F flag is “0,” executes the
next instruction.
When V12 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
1010000001 281 11
–V13 = 0: (T2F) = 1
Grouping: Timer operation
Description: When V13 = 0 : Skips the next instruction
when timer 2 interrupt request flag T2F is
“1.” After skipping, clears (0) to the T2F
flag. When the T2F flag is “0,” executes the
next instruction.
When V13 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag)
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
1010000010 282 11
–V20 = 0: (T3F) = 1
Grouping: Timer operation
Description: When V20 = 0 : Skips the next instruction
when timer 3 interrupt request flag T3F is
“1.” After skipping, clears (0) to the T3F
flag. When the T3F flag is “0,” executes the
next instruction.
When V20 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1: SNZT3 = NOP
(V20 = bit 0 of interrupt control register V2)
1010001000 288 11
–V23 = 0: (SIOF) = 1
Grouping: Serial I/O operation
Description: When V23 = 0 : Skips the next instruction
when serial I/O interrupt request flag SIOF
is “1.” After skipping, clears (0) to the SIOF
flag. When the SIOF flag is “0,” executes
the next instruction.
When V23 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V23 = 0: (SIOF) = 1 ?
After skipping, (SIOF) ← 0
V23 = 1: SNZSI = NOP
(V23 = bit 3 of interrupt control register V2)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 108 of 159
REJ03B0091-0200Z
4524 Group
SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag)
SNZT5 (Skip if Non Zero condition of Timer 5 inerrupt request flag)
SST (Serial i/o transmission/reception STart)
SVDE (Set Voltage Detector Enable flag)
1010000011 283 11
–V23 = 0: (T4F) = 1
Grouping: Timer operation
Description: When V23 = 0 : Skips the next instruction
when timer 4 interrupt request flag T4F is
“1.” After skipping, clears (0) to the T4F
flag. When the T4F flag is “0,” executes the
next instruction.
When V23 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V23 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0
V23 = 1: SNZT4 = NOP
(V23 = bit 3 of interrupt control register V2)
1010000100 284 11
–V21 = 0: (T5F) = 1
Grouping: Timer operation
Description: When V21 = 0 : Skips the next instruction
when timer 5 interrupt request flag T5F is
“1.” After skipping, clears (0) to the T5F
flag. When the T5F flag is “0,” executes the
next instruction.
When V21 = 1 : This instruction is equiva-
lent to the NOP instruction.
Operation: V21 = 0: (T5F) = 1 ?
After skipping, (T5F) ← 0
V21 = 1: SNZT5 = NOP
(V21 = bit 1 of interrupt control register V2)
1010011110 29E 11
––
Grouping: Serial I/O operation
Description: Clears (0) to SIOF flag and starts serial I/O.
Operation: (SIOF) ← 0
Serial I/O transmission/reception start
1010010011 293 11
––
Grouping: Other operation
Description: Validates the voltage drop detection circuit
at power down (clock operating mode and
RAM back-up mode) when VDCE pin is “H”.
Operation: At power down mode, voltage drop detection circuit valid
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 109 of 159
REJ03B0091-0200Z
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
00001000j j 02j 11
–(Mj(DP)) = 0
j = 0 to 3
Grouping: Bit operation
Description: Skips the next instruction when the con-
tents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the con-
tents of bit j of M(DP) is “1.”
Operation: (Mj(DP)) = 0 ?
j = 0 to 3
SZC (Skip if Zero, Carry flag)
0000101111 02F 11
–(CY) = 0
Grouping: Arithmetic operation
Description: Skips the next instruction when the con-
tents of carry flag CY is “0.”
After skipping, the CY flag remains un-
changed.
Executes the next instruction when the con-
tents of the CY flag is “1.“
Operation: (CY) = 0 ?
SZD (Skip if Zero, port D specified by register Y)
0000100100 024 22
–(D(Y)) = 0
(Y) = 0 to 7
Grouping: Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
1000110000 230 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 re-
load register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
Operation: (T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
Operation: (D(Y)) = 0 ?
(Y) = 0 to 7
216
0000101011 02B
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 110 of 159
REJ03B0091-0200Z
4524 Group
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
1000110001 231 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
Operation: (T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
T4HAB (Transfer data to register R4H from Accumulator and register B)
1000110010 232 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 3 and timer 3 re-
load register R3. Transfers the contents of
register A to the low-order 4 bits of timer 3
and timer 3 reload register R3.
Operation: (T37–T34) ← (B)
(R37–R34) ← (B)
(T33–T30) ← (A)
(R33–R30) ← (A)
1000110011 233 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 re-
load register R4L. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4L.
Operation: (T47–T44) ← (B)
(R4L7–R4L4) ← (B)
(T43–T40) ← (A)
(R4L3–R4L0) ← (A)
1000110111 237 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 re-
load register R4H. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4H.
Operation: (R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 111 of 159
REJ03B0091-0200Z
4524 Group
TAB (Transfer data to Accumulator from register B)
0000011110 01E 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register B to reg-
ister A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
1001110000 270 11
––
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
Operation: (B) ← (T17–T14)
(A) ← (T13–T10)
TAB2 (Transfer data to Accumulator and register B from timer 2)
1001110001 271 11
––
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
Operation: (B) ← (T27–T24)
(A) ← (T23–T20)
Operation: (A) ← (B)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T4R4L (Transfer data to timer 4 from register R4L)
1010010111 297 11
––
Grouping: Timer operation
Description: Transfers the contents of reload register
R4L to timer 4.
Operation: (T47–T44) ← (R4L7–R4L4)
(T43–T40) ← (R4L3–R4L0)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 112 of 159
REJ03B0091-0200Z
4524 Group
TABE (Transfer data to Accumulator and register B from register E)
0000101010 02A 11
––
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
Operation: (B) ← (E7–E4)
(A) ← (E3–E0)
TABAD (Transfer data to Accumulator and register B from register AD)
1001111001 279 11
––
Grouping: A/D conversion operation
Description: In the A/D conversion mode (Q1
3
= 0), trans-
fers the high-order 4 bits (AD
9
–AD
6
) of
register AD to register B, and the middle-or-
der 4 bits (AD
5
–AD
2
) of register AD to
register A. In the comparator mode (Q1
3
= 1),
transfers the middle-order 4 bits (AD
7
–AD
4
)
of register AD to register B, and the low-order
4 bits (AD
3
–AD
0
) of register AD to register A.
Operation: In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TAB4 (Transfer data to Accumulator and register B from timer 4)
TAB3 (Transfer data to Accumulator and register B from timer 3)
1001110010 272 11
––
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T37–T34) of
timer 3 to register B.
Transfers the low-order 4 bits (T33–T30) of
timer 3 to register A.
Operation: (B) ← (T37–T34)
(A) ← (T33–T30)
1001110011 273 11
––
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
Operation: (B) ← (T47–T44)
(A) ← (T43–T40)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 113 of 159
REJ03B0091-0200Z
4524 Group
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
0010p5p4p3p2p1p00p 13
––
Grouping: Arithmetic operation
Operation: (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TAD (Transfer data to Accumulator from register D)
0001010001 051 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note: When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation: (A2–A0) ← (DR2–DR0)
(A3) ← 0
8
+p
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABPS (Transfer data to Accumulator and register B from PreScaler)
TABSI (Transfer data to Accumulator and register B from register SI)
1001111000 278 11
––
Grouping: Serial I/O operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
serial I/O register SI to register B, and
transfers the low-order 4 bits (SI3–SI0) of
serial I/O register SI to register A.
Operation: (B) ← (SI7–SI4)
(A) ← (SI3–SI0)
1001110101 275 11––
Grouping: Timer operation
Description: Transfers the high-order 4 bits (TPS7–
TPS4) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
Operation: (B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by reg-
isters A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
When this instruction is executed, be careful not to over the stack because 1 stage of
stack register is used.
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 114 of 159
REJ03B0091-0200Z
4524 Group
TADAB (Transfer data to register AD from Accumulator from register B)
1000111001 239 11
––
Grouping: A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), this in-
struction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), trans-
fers the contents of register B to the
high-order 4 bits (AD7–AD4) of comparator
register, and the contents of register A to
the low-order 4 bits (AD3–AD0) of compara-
tor register.
(Q13 = bit 3 of A/D control register Q1)
Operation: (AD7–AD4) ← (B)
(AD3–AD0) ← (A)
TAI1 (Transfer data to Accumulator from register I1)
1001010011 253 11
––
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
Operation: (A) ← (I1)
TAI2 (Transfer data to Accumulator from register I2)
TAI3 (Transfer data to Accumulator from register I3)
1001010100 254 11––
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control
register I2 to register A.
Operation: (A) ← (I2)
1001010101 255 11
––
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control
register I3 to the lowermost bit (A0) of regis-
ter A.
Note: When the TAI3 instruction is executed, “0” is stored
to the high-order 3 bits (A3–A1) of register A.
Operation: (A0) ← (I30)
(A3–A1) ← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 115 of 159
REJ03B0091-0200Z
4524 Group
TAK0 (Transfer data to Accumulator from register K0)
1001010110 256 11
––
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
Operation: (A) ← (K0)
TAK1 (Transfer data to Accumulator from register K1)
1001011001 259 11
––
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
Operation: (A) ← (K1)
TAK2 (Transfer data to Accumulator from register K2)
1001011010 25A 11
––
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
Operation: (A) ← (K2)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAJ1 (Transfer data to Accumulator from register J1)
1001000010 242 11
––
Grouping: Serial I/O operation
Description: Transfers the contents of serial I/O control
register J1 to register A.
Operation: (A) ← (J1)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 116 of 159
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4524 Group
TALA (Transfer data to Accumulator from register LA)
1001001001 249 11
––
Grouping: A/D conversion operation
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A.
Note: After this instruction is executed, “0” is
stored to the low-order 2 bits (A1, A0) of
register A.
Operation: (A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TAM j (Transfer data to Accumulator from Memory)
101100jjjj 2Cj 11
––
Grouping: RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the re-
sult in register X.
TAMR (Transfer data to Accumulator from register MR)
1001010010 252 11––
Grouping: Clock operation
Description: Transfers the contents of clock control reg-
ister MR to register A.
Operation: (A) ← (MR)
Operation: (A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAL1 (Transfer data to Accumulator from register L1)
1001001010 24A 11
––
Grouping: LCD control operation
Description: Transfers the LCD control register L1 to
register A.
Operation: (A) ← (L1)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 117 of 159
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4524 Group
TAQ1 (Transfer data to Accumulator from register Q1)
1001000100 244 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of A/D control regis-
ter Q1 to register A.
Operation: (A) ← (Q1)
TAPU1 (Transfer data to Accumulator from register PU1)
TAPU0 (Transfer data to Accumulator from register PU0)
TAQ2 (Transfer data to Accumulator from register Q2)
1001000101 245 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of A/D control regis-
ter Q2 to register A.
Operation: (A) ← (Q2)
1001010111 257 11
––
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control
register PU0 to register A.
Operation: (A) ← (PU0)
1001011110 25E 11
––
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control
register PU1 to register A.
Operation: (A) ← (PU1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 118 of 159
REJ03B0091-0200Z
4524 Group
TASP (Transfer data to Accumulator from Stack Pointer)
0001010000 050 11––
Grouping: Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
Note: After this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
0001010100 054 11
––
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
Operation: (A) ← (V1)
TAV2 (Transfer data to Accumulator from register V2)
0001010101 055 11
––
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
Operation: (A) ← (V2)
Operation: (A2–A0) ← (SP2–SP0)
(A3) ← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAQ3 (Transfer data to Accumulator from register Q3)
1001000110 246 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of A/D control regis-
ter Q3 to register A.
Operation: (A) ← (Q3)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 119 of 159
REJ03B0091-0200Z
4524 Group
TAW2 (Transfer data to Accumulator from register W2)
1001001100 24C 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W2 to register A.
Operation: (A) ← (W2)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
1001001011 24B 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W1 to register A.
Operation: (A) ← (W1)
TAW3 (Transfer data to Accumulator from register W3)
TAW4 (Transfer data to Accumulator from register W4)
1001001110 24E 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W4 to register A.
Operation: (A) ← (W4)
1001001101 24D 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W3 to register A.
Operation: (A) ← (W3)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 120 of 159
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4524 Group
TAW5 (Transfer data to Accumulator from register W5)
TAW6 (Transfer data to Accumulator from register W6)
1001010000 250 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W6 to register A.
TAX (Transfer data to Accumulator from register X)
0001010010 052 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register X to reg-
ister A.
Operation: (A) ← (X)
Operation: (A) ← (W6)
TAY (Transfer data to Accumulator from register Y)
0000011111 01F 11
––
Grouping: Register to register transfer
Description: T ransfers the contents of register Y to regis-
ter A.
Operation: (A) ← (Y)
1001001111 24F 11
––
Grouping: Timer operation
Description: Transfers the contents of timer control reg-
ister W5 to register A.
Operation: (A) ← (W5)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 121 of 159
REJ03B0091-0200Z
4524 Group
TBA (Transfer data to register B from Accumulator)
0000001110 00E 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register A to regis-
ter B.
TDA (Transfer data to register D from Accumulator)
0000101001 029 11
––
Grouping: Register to register transfer
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
Operation: (DR2–DR0) ← (A2–A0)
TEAB (Transfer data to register E from Accumulator and register B)
0000011010 01A 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E7–E4) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
Operation: (E7–E4) ← (B)
(E3–E0) ← (A)
Operation: (B) ← (A)
TAZ (Transfer data to Accumulator from register Z)
0001010011 053 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A.
Note: After this instruction is executed, “0” is
stored to the high-order 2 bits (A3, A2) of
register A.
Operation: (A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 122 of 159
REJ03B0091-0200Z
4524 Group
TFR3A (Transfer data to register FR3 from Accumulator)
TFR2A (Transfer data to register FR2 from Accumulator)
TFR1A (Transfer data to register FR1 from Accumulator)
TFR0A (Transfer data to register FR0 from Accumulator)
1000101000 228 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR0.
Operation: (FR0) ← (A)
1000101001 229 11––
Grouping: Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR1.
Operation: (FR1) ← (A)
1000101010 22A 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR2.
Operation: (FR2) ← (A)
1000101011 22B 11––
Grouping: Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR3.
Operation: (FR3) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 123 of 159
REJ03B0091-0200Z
4524 Group
TI1A (Transfer data to register I1 from Accumulator)
1000010111 217 11
––
Grouping: Interrupt operation
Description: Transfers the contents of register A to inter-
rupt control register I1.
Operation: (I1) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TI2A (Transfer data to register I2 from Accumulator)
TI3A (Transfer data to register I3 from Accumulator)
TJ1A (Transfer data to register J1 from Accumulator)
1000011000 218 11
––
Grouping: Interrupt operation
Description: Transfers the contents of register A to inter-
rupt control register I2.
Operation: (I2) ← (A)
1000011010 21A 11
––
Grouping: Interrupt operation
Description: Transfers the contents of the lowermost bit
(A0) of register A to interrupt control register
I1.
Operation: (I30) ← (A0)
1000000010 202 11
––
Grouping: Serial I/O operation
Description: Transfers the contents of register A to serial
I/O control register J1.
Operation: (J1) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 124 of 159
REJ03B0091-0200Z
4524 Group
TK0A (Transfer data to register K0 from Accumulator)
1000011011 21B 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-
on wakeup control register K0.
Operation: (K0) ← (A)
TK1A (Transfer data to register K1 from Accumulator)
1000010100 214 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-
on wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
1000010101 215 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-
on wakeup control register K2.
Operation: (K2) ← (A)
Operation: (K1) ← (A)
TL1A (Transfer data to register L1 from Accumulator)
1000001010 20A 11
––
Grouping: LCD operation
Description: Transfers the contents of register A to LCD
control register L1.
Operation: (L1) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 125 of 159
REJ03B0091-0200Z
4524 Group
TL2A (Transfer data to register L2 from Accumulator)
TLCA (Transfer data to timer LC and register RLC from Accumulator)
TMA j (Transfer data to Memory from Accumulator)
101011jjjj 2Bj 11
––
Grouping: RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is per-
formed between register X and the value j
in the immediate field, and stores the result
in register X.
Operation: (M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
TMRA (Transfer data to register MR from Accumulator)
1000010110 216 11––
Grouping: Other operation
Description: Transfers the contents of register A to clock
control register MR.
Operation: (MR) ← (A)
1000001011 20B 11
––
Grouping: LCD operation
Description: Transfers the contents of register A to LCD
control register L2.
Operation: (L2) ← (A)
1000001101 20D 11––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
LC and reload register RLC.
Operation: (LC) ← (A)
(RLC) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 126 of 159
REJ03B0091-0200Z
4524 Group
TPU0A (Transfer data to register PU0 from Accumulator)
1000101101 22D 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-
up control register PU0.
Operation: (PU0) ← (A)
TPU1A (Transfer data to register PU1 from Accumulator)
1000101110 22E 11
––
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-
up control register PU1.
Operation: (PU1) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
1010101010 2AA 11
––
Grouping: Timer operation
Description: Transfers the contents of lowermost bit (A0)
register A to timer control register PA.
Operation: (PA0) ← (A0)
1000110101 235 11––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS, and transfers the con-
tents of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
Operation: (RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 127 of 159
REJ03B0091-0200Z
4524 Group
TQ2A (Transfer data to register Q2 from Accumulator)
TR1AB (Transfer data to register R1 from Accumulator and register B)
1000111111 23F 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R17–R14) of reload regis-
ter R1, and the contents of register A to the
low-order 4 bits (R13–R10) of reload regis-
ter R1.
Operation: (R17–R14) ← (B)
(R13–R10) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TQ1A (Transfer data to register Q1 from Accumulator)
1000000100 204 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q1.
Operation: (Q1) ← (A)
TQ3A (Transfer data to register Q3 from Accumulator)
1000000101 205 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q2.
Operation: (Q2) ← (A)
1000000110 206 11
––
Grouping: A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q3.
Operation: (Q3) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 128 of 159
REJ03B0091-0200Z
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
0000111111 03F 11
––
Grouping: Interrupt operation
Description: Transfers the contents of register A to inter-
rupt control register V1.
Operation: (V1) ← (A)
TR3AB (Transfer data to register R3 from Accumulator and register B)
TSIAB (Transfer data to register SI from Accumulator and register B)
TV2A (Transfer data to register V2 from Accumulator)
0000111110 03E 11
––
Grouping: Interrupt operation
Description: Transfers the contents of register A to inter-
rupt control register V2.
Operation: (V2) ← (A)
1000111011 23B 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R37–R34) of reload regis-
ter R3, and the contents of register A to the
low-order 4 bits (R33–R30) of reload regis-
ter R3.
Operation: (R37–R34) ← (B)
(R33–R30) ← (A)
1000111000 238 11
––
Grouping: Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (SI7–SI4) of serial I/O reg-
ister SI, and transfers the contents of
register A to the low-order 4 bits (SI3–SI0) of
serial I/O register SI.
Operation: (SI7–SI4) ← (B)
(SI3–SI0) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 129 of 159
REJ03B0091-0200Z
4524 Group
TW3A (Transfer data to register W3 from Accumulator)
TW4A (Transfer data to register W4 from Accumulator)
TW1A (Transfer data to register W1 from Accumulator)
1000001110 20E 11––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W1.
Operation: (W1) ← (A)
TW2A (Transfer data to register W2 from Accumulator)
1000001111 20F 11
––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W2.
Operation: (W2) ← (A)
1000010000 210 11
––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W3.
Operation: (W3) ← (A)
1000010001 211 11
––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W4.
Operation: (W4) ← (A)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 130 of 159
REJ03B0091-0200Z
4524 Group
TYA (Transfer data to register Y from Accumulator)
0000001100 00C 11
––
Grouping: Register to register transfer
Description: Transfers the contents of register A to regis-
ter Y.
Operation: (Y) ← (A)
WRST (Watchdog timer ReSeT)
1010100000 2A0 11
–(WDF1) = 1
Grouping: Other operation
Description: Skips the next instruction when watchdog
timer flag WDF1 is “1.” After skipping, clears
(0) to the WDF1 flag. When the WDF1 flag
is “0,” executes the next instruction. Also,
stops the watchdog timer function when ex-
ecuting the WRST instruction immediately
after the DWDT instruction.
Operation: (WDF1) = 1 ?
After skipping, (WDF1) ← 0
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW5A (Transfer data to register W5 from Accumulator)
TW6A (Transfer data to register W6 from Accumulator)
1000010011 213 11
––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W6.
Operation: (W6) ← (A)
1000010010 212 11
––
Grouping: Timer operation
Description: Transfers the contents of register A to timer
control register W5.
Operation: (W5) ← (A)
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Skip condition
Number of
cycles
Number of
words
Instruction
code D9D0Flag CY
216
Rev.2.00 Jul 27, 2004 page 131 of 159
REJ03B0091-0200Z
4524 Group
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
101110jjjj 2Ej 11–(Y) = 0
Grouping: RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. when the contents of register Y is
not 0, the next instruction is executed.
Operation: (A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Instruction
code 216
XAM j (eXchange Accumulator and Memory data)
101101jjjj 2Dj 11
––
Grouping: RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
Operation: (A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
101111jjjj 2Fj 11
–(Y) = 15
Grouping: RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
Operation: (A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 132 of 159
REJ03B0091-0200Z
4524 Group
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
(E7–E4) ← (B)
(E3–E0) ← (A)
(B) ← (E7–E4)
(A) ← (E3–E0)
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
(A) ← (X)
(A2–A0) ← (SP2–SP0)
(A3) ← 0
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
(Z) ← z z = 0 to 3
(Y) ← (Y) + 1
(Y) ← (Y) – 1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
TAB
TBA
TAY
TYA
TEAB
TABE
TDA
TAD
TAZ
TAX
TASP
LXY x, y
LZ z
INY
DEY
TAM j
XAM j
XAMD j
XAMI j
TMA j
MACHINE INSTRUCTIONS (INDEX BY TYPES)
0000011110
0000001110
0000011111
0000001100
0000011010
0000101010
0000101001
0001010001
0001010011
0001010010
0001010000
11x3x2x1x0y3y2y1y0
00010010z1z0
0000010011
0000010111
101100jjjj
101101jjjj
101111jjjj
101110jjjj
101011jjjj
01E
00E
01F
00C
01A
02A
029
051
053
052
050
3xy
048
+z
013
017
2Cj
2Dj
2Fj
2Ej
2Bj
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RAM addresses
RAM to register transfer Register to register transfer
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 133 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
–
–
–
–
–
–
–
Continuous
description
–
(Y) = 0
(Y) = 15
–
–
(Y) = 15
(Y) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of register B to register A.
Transfers the contents of register A to register B.
Transfers the contents of register Y to register A.
Transfers the contents of register A to register Y.
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of regis-
ter A to the low-order 4 bits (E3–E0) of register E.
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E
to register A.
Transfers the contents of the low-order 3 bits (A 2–A0) of register A to register D.
Transfers the contents of register D to the low-order 3 bits (A 2–A0) of register A.
Transfers the contents of register Z to the low-order 2 bits (A 1, A0) of register A.
Transfers the contents of register X to register A.
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A 2–A0) of register A.
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
Loads the value z in the immediate field to register Z.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. When the contents of register Y is not 0, the next instruction is executed.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. When the contents of register Y is not 0, the next instruction is executed.
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 134 of 159
REJ03B0091-0200Z
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
07n
08p
+p
00A
00B
06n
018
019
007
006
02F
01C
01D
05C
+j
04C
+j
02j
026
025
07n
000111nnnn
0010p5p4p3p2p1p0
0000001010
0000001011
000110nnnn
0000011000
0000011001
0000000111
0000000110
0000101111
0000011100
0000011101
00010111j j
00010011j j
00001000j j
0000100110
0000100101
000111nnnn
LA n
TABP p
AM
AMC
A n
AND
OR
SC
RC
SZC
CMA
RAR
SB j
RB j
SZB j
SEAM
SEA n
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
Arithmetic operation
Comparison
operation Bit operation
(A) ← n
n = 0 to 15
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ← (A) + (M(DP))
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
(A) ← (A) + n
n = 0 to 15
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
(CY) ← 1
(CY) ← 0
(CY) = 0 ?
(A) ← (A)
→ CY → A3A2A1A0
(Mj(DP)) ← 1
j = 0 to 3
(Mj(DP)) ← 0
j = 0 to 3
(Mj(DP)) = 0 ?
j = 0 to 3
(A) = (M(DP)) ?
(A) = n ?
n = 0 to 15
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 135 of 159
REJ03B0091-0200Z
4524 Group
Continuous
description
–
–
–
Overflow = 0
–
–
–
–
(CY) = 0
–
–
–
–
(Mj(DP)) = 0
j = 0 to 3
(A) = (M(DP))
(A) = n
–
–
–
0/1
–
–
–
1
0
–
–
0/1
–
–
–
–
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re-
mains unchanged.
Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re-
sult in register A.
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
Sets (1) to carry flag CY.
Clears (0) to carry flag CY.
Skips the next instruction when the contents of carry flag CY is “0.”
Stores the one’s complement for register A’s contents in register A.
Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 136 of 159
REJ03B0091-0200Z
4524 Group
B a
BL p, a
BLA p
BM a
BML p, a
BMLA p
RTI
RT
RTS
011a6a5a4a3a2a1a0
00111p4p3p2p1p0
1p6p5a6a5a4a3a2a1a0
0000010000
1p6p5p400p3p2p1p0
010a6a5a4a3a2a1a0
00110p4p3p2p1p0
1p6p5a6a5a4a3a2a1a0
0000110000
1p6p5p400p3p2p1p0
0001000110
0001000100
0001000101
18a
+a
0Ep
+p
2pa
+p +a
010
2pp
+p
1aa
0Cp
+p
2pa
+p +a
030
2pp
+p
046
044
045
1
2
2
1
2
2
1
1
1
1
2
2
1
2
2
1
2
2
Subroutine operation
Return operation
MACHINE INSTRUCTIONS (continued)
(PCL) ← a6–a0
(PCH) ← p (Note)
(PCL) ← a6–a0
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Branch operation
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 137 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
–
–
–
–
Skip at uncondition
–
–
–
–
–
–
–
–
–
Branch within a page : Branches to address a in the identical page.
Branch out of a page : Branches to address a in page p.
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
Call the subroutine : Calls the subroutine at address a in page p.
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de-
scription of the LA/LXY instruction, register A and register B to the states just before interrupt.
Returns from subroutine to the routine called the subroutine.
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 138 of 159
REJ03B0091-0200Z
4524 Group
DI
EI
SNZ0
SNZ1
SNZI0
SNZI1
TAV1
TV1A
TAV2
TV2A
TAI1
TI1A
TAI2
TI2A
TAI3
TI3A
TPAA
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
TAW4
TW4A
(INTE) ← 0
(INTE) ← 1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
(I1) ← (A)
(A) ← (I2)
(I2) ← (A)
(A0) ← (I30), (A3–A1) ← 0
(I30) ← (A0)
(PA0) ← (A0)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
(A) ← (W4)
(W4) ← (A)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
004
005
038
039
03A
03B
054
03F
055
03E
253
217
254
218
255
21A
2AA
24B
20E
24C
20F
24D
210
24E
211
0000000100
0000000101
0000111000
0000111001
0000111010
0000111011
0001010100
0000111111
0001010101
0000111110
1001010011
1000010111
1001010100
1000011000
1001010101
1000011010
1010101010
1001001011
1000001110
1001001100
1000001111
1001001101
1000010000
1001001110
1000010001
Interrupt operation
Timer operation
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 139 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V10 = 0: (EXF0) = 1
V11 = 0: (EXF1) = 1
(INT0) = “H”
However, I12 = 1
(INT0) = “L”
However, I12 = 0
(INT1) = “H”
However, I22 = 1
(INT1) = “L”
However, I22 = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Skip condition Datailed description
Carry flag CY
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1)
When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping,
clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1)
When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control reg-
ister I1)
When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.”
When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control reg-
ister I2)
When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.”
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of interrupt control register I2 to register A.
Transfers the contents of register A to interrupt control register I2.
Transfers the contents of interrupt control register I3 to the lowermost bit (A0) of register A.
Transfers the contents of the lowermost bit (A0) of register A to interrupt control register I3.
Transfers the contents of register A to timer control register PA.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W3 to register A.
Transfers the contents of register A to timer control register W3.
Transfers the contents of timer control register W4 to register A.
Transfers the contents of register A to timer control register W4.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 140 of 159
REJ03B0091-0200Z
4524 Group
1001001111
1000010010
1001010000
1000010011
1001110101
1000110101
1001110000
1000110000
1001110001
1000110001
1001110010
1000110010
1001110011
1000110011
1000110111
1000111111
1000111011
1010010111
1000001101
24F
212
250
213
275
235
270
230
271
231
272
232
273
233
237
23F
23B
297
20D
(A) ← (W5)
(W5) ← (A)
(A) ← (W6)
(W6) ← (A)
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
(B) ← (T17–T14)
(A) ← (T13–T10)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
(B) ← (T27–T24)
(A) ← (T23–T20)
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
(B) ← (T37–T34)
(A) ← (T33–T30)
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
(B) ← (T47–T44)
(A) ← (T43–T40)
(R4L7–R4L4) ← (B)
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
(R17–R14) ← (B)
(R13–R10) ← (A)
(R37–R34) ← (B)
(R33–R30) ← (A)
(T47–T40) ← (R4L7–R4L0)
(LC) ← (A)
(RLC) ← (A)
TAW5
TW5A
TAW6
TW6A
TABPS
TPSAB
TAB1
T1AB
TAB2
T2AB
TAB3
T3AB
TAB4
T4AB
T4HAB
TR1AB
TR3AB
T4R4L
TLCA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Timer operation
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 141 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of timer control register W5 to register A.
Transfers the contents of register A to timer control register W5.
Transfers the contents of timer control register W6 to register A.
Transfers the contents of register A to timer control register W6.
Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to
register A.
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS,
and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register
RPS.
Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to regis-
ter A.
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and
transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to regis-
ter A.
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and
transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to regis-
ter A.
Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and
transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to regis-
ter A.
Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and
transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the
contents of register A to the low-order 4 bits of timer 4 reload register R4H.
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1.
Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the
contents of register A to the low-order 4 bits of timer 3 reload register R3.
Transfers the contents of timer 4 reload register R4L to timer 4.
Transfers the contents of register A to timer LC and timer LC reload register RLC.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 142 of 159
REJ03B0091-0200Z
4524 Group
1010000000
1010000001
1010000010
1010000011
1010000100
1001100000
1000100000
1001100001
1000100001
1001100010
1000100010
1001100011
1000100011
1001100100
1000100100
0000010001
0000010100
0000010101
0000100100
0000101011
1010001100
1010001101
1001010111
1000101101
1001011110
1000101110
280
281
282
283
284
260
220
261
221
262
222
263
223
264
224
011
014
015
024
02B
28C
28D
257
22D
25E
22E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SNZT1
SNZT2
SNZT3
SNZT4
SNZT5
IAP0
OP0A
IAP1
OP1A
IAP2
OP2A
IAP3
OP3A
IAP4
OP4A
CLD
RD
SD
SZD
RCP
SCP
TAPU0
TPU0A
TAPU1
TPU1A
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0 V12 = 1: NOP
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0 V13 = 1: NOP
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0 V20 = 1: NOP
V23 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0 V23 = 1: NOP
V21 = 0: (T5F) = 1 ?
After skipping, (T5F) ← 0 V21 = 1: NOP
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
(A) ← (P2)
(P2) ← (A)
(A) ← (P3)
(P3) ← (A)
(A) ← (P4)
(P4) ← (A)
(D) ← 1
(D(Y)) ← 0
(Y) = 0 to 9
(D(Y)) ← 1
(Y) = 0 to 9
(D(Y)) = 0 ?
(Y) = 0 to 7
(C) ← 0
(C) ← 1
(A) ← (PU0)
(PU0) ← (A)
(A) ← (PU1)
(PU1) ← (A)
Input/Output operation Timer operation
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 143 of 159
REJ03B0091-0200Z
4524 Group
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the con-
tents of T1F flag is “1.” After skipping, clears (0) to T1F flag.
Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the con-
tents of T2F flag is “1.” After skipping, clears (0) to T2F flag.
Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the con-
tents of T3F flag is “1.” After skipping, clears (0) to T3F flag.
Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and the con-
tents of T4F flag is “1.” After skipping, clears (0) to T4F flag.
Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the con-
tents of T5F flag is “1.” After skipping, clears (0) to T5F flag.
Transfers the input of port P0 to register A.
Outputs the contents of register A to port P0.
Transfers the input of port P1 to register A.
Outputs the contents of register A to port P1.
Transfers the input of port P2 to register A.
Outputs the contents of register A to port P2.
Transfers the input of port P3 to register A.
Outputs the contents of register A to port P3.
Transfers the input of port P4 to register A.
Outputs the contents of register A to port P4.
Sets (1) to all port D.
Clears (0) to a bit of port D specified by register Y.
Sets (1) to a bit of port D specified by register Y.
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
Clears (0) to port C.
Sets (1) to port C.
Transfers the contents of pull-up control register PU0 to register A.
Transfers the contents of register A to pull-up control register PU0.
Transfers the contents of pull-up control register PU1 to register A.
Transfers the contents of register A to pull-up control register PU1.
V12 = 0: (T1F) = 1
V13 = 0: (T2F) =1
V20 = 0: (T3F) = 1
V23 = 0: (T4F) =1
V21 = 0: (T5F) =1
–
–
–
–
–
–
–
–
–
–
–
–
–
(D(Y)) = 0
However, (Y)=0 to 7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 144 of 159
REJ03B0091-0200Z
4524 Group
TAK0
TK0A
TAK1
TK1A
TAK2
TK2A
TFR0A
TFR1A
TFR2A
TFR3A
TAL1
TL1A
TL2A
TABSI
TSIAB
SST
SNZSI
TAJ1
TJ1A
CMCK
CRCK
TAMR
TMRA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
256
21B
259
214
25A
215
228
229
22A
22B
24A
20A
20B
278
238
29E
288
242
202
29A
29B
252
216
1001010110
1000011011
1001011001
1000010100
1001011010
1000010101
1000101000
1000101001
1000101010
1000101011
1001001010
1000001010
1000001011
1001111000
1000111000
1010011110
1010001000
1001000010
1000000010
1010011010
1010011011
1001010010
1000010110
Input/Output operation
(A) ← (K0)
(K0) ← (A)
(A) ← (K1)
(K1) ← (A)
(A) ← (K2)
(K2) ← (A)
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
(A) ← (L1)
(L1) ← (A)
(L2) ← (A)
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
(SIOF) ← 0
Serial I/O starting
V23=0: (SIOF)=1?
After skipping, (SIOF) ← 0 V23 = 1: NOP
(A) ← (J1)
(J1) ← (A)
Ceramic resonator selected
RC oscillator selected
(A) ← (MR)
(MR) ← (A)
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
LCD operation
Serial I/O operation
Clock operation
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 145 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V23 = 0: (SIOF) = 1
–
–
–
–
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
Transfers the contents of register A to key-on wakeup control register K0 .
Transfers the contents of key-on wakeup control register K1 to register A.
Transfers the contents of register A to key-on wakeup control register K1.
Transfers the contents of key-on wakeup control register K2 to register A.
Transfers the contents of register A to key-on wakeup control register K2.
Transferts the contents of register A to port output format control register FR0.
Transferts the contents of register A to port output format control register FR1.
Transferts the contents of register A to port output format control register FR2.
Transferts the contents of register A to port output format control register FR3.
Transfers the contents of LCD control register L1 to register A.
Transfers the contents of register A to LCD control register L1.
Transfers the contents of register A to LCD control register L2.
Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of se-
rial I/O register SI to register A.
Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the con-
tents of register A to the low-order 4 bits of serial I/O register SI.
Clears (0) to SIOF flag and starts serial I/O.
Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents
of SIOF flag is “1.” After skipping, clears (0) to SIOF flag.
Transfers the contents of serial I/O control register J1 to register A.
Transfers the contents of register A to serial I/O control register J1.
Selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator).
Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator).
Transfers the contents of clock control regiser MR to register A.
Transfers the contents of register A to clock control register MR.
Parameter Instruction code
Function
Number of
cycles
Number of
words
Mnemonic
Type of
instructions D9D8D7D6D5D4D3D2D1D0Hexadecimal
notation
Rev.2.00 Jul 27, 2004 page 146 of 159
REJ03B0091-0200Z
4524 Group
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
279
249
239
29F
287
244
204
245
205
246
206
000
002
008
05B
003
2A0
29C
040
041
293
1001111001
1001001001
1000111001
1010011111
1010000111
1001000100
1000000100
1001000101
1000000101
1001000110
1000000110
0000000000
0000000010
0000001000
0001011011
0000000011
1010100000
1010011100
0001000000
0001000001
1010010011
A/D conversion operation
Other operation
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
TABAD
TALA
TADAB
ADST
SNZAD
TAQ1
TQ1A
TAQ2
TQ2A
TAQ3
TQ3A
NOP
POF
POF2
EPOF
SNZP
WRST
DWDT
RBK*
SBK*
SVDE
Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
(ADF) ← 0
A/D conversion starting
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0 V22 = 1: NOP
(A) ← (Q1)
(Q1) ← (A)
(A) ← (Q2)
(Q2) ← (A)
(A) ← (Q3)
(Q3) ← (A)
(PC) ← (PC) + 1
Transition to clock operating mode
Transition to RAM back-up mode
POF, POF2 instructions valid
(P) = 1 ?
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
Stop of watchdog timer function enabled
When TABP p instruction is executed, P6 ← 0
When TABP p instruction is executed, P6 ← 1
At power down mode, voltage drop detection
circuit valid
Note: * (SBK, RBK) cannot be used in the M34524M8.
The pages which can be referred by the TABP instruction after the SBK instruction is executed are
64 to 95 in the M34524MC.
Skip condition Datailed description
Carry flag CY
Rev.2.00 Jul 27, 2004 page 147 of 159
REJ03B0091-0200Z
4524 Group
–
–
–
–
V22 = 0: (ADF) = 1
–
–
–
–
–
–
–
–
–
–
(P) = 1
(WDF1) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
Transfers the low-order 2 bits (AD 1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD 3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction.
(V2
2
: bit 2 of interrupt con-
trol register V2)
Transfers the contents of A/D control register Q1 to register A.
Transfers the contents of register A to A/D control register Q1.
Transfers the contents of A/D control register Q2 to register A.
Transfers the contents of register A to A/D control register Q2.
Transfers the contents of A/D control register Q3 to register A.
Transfers the contents of register A to A/D control register Q3.
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruc-
tion.
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode)
when VDCE pin is “H”.
Rev.2.00 Jul 27, 2004 page 148 of 159
REJ03B0091-0200Z
4524 Group
INSTRUCTION CODE TABLE
D3–D0Hex.
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D9–D4
00
NOP
–
POF
SNZP
DI
EI
RC
SC
POF2
–
AM
AMC
TYA
–
TBA
–
000001
01
BLA
CLD
–
INY
RD
SD
–
DEY
AND
OR
TEAB
–
CMA
RAR
TAB
TAY
000010
02
SZB
0
SZB
1
SZB
2
SZB
3
SZD
SEAn
SEAM
–
–
TDA
TABE
–
–
–
–
SZC
000011
03
BMLA
–
–
–
–
–
–
–
SNZ0
SNZ1
SNZI0
SNZI1
–
–
TV2A
TV1A
000100
04
RBK**
SBK**
–
–
RT
RTS
RTI
–
LZ
0
LZ
1
LZ
2
LZ
3
RB
0
RB
1
RB
2
RB
3
000101
05
TASP
TAD
TAX
TAZ
TAV1
TAV2
–
–
–
–
–
EPOF
SB
0
SB
1
SB
2
SB
3
000110
06
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
000111
07
LA
0
LA
1
LA
2
LA
3
LA
4
LA
5
LA
6
LA
7
LA
8
LA
9
LA
10
LA
11
LA
12
LA
13
LA
14
LA
15
001000
08
TABP
0
TABP
1
TABP
2
TABP
3
TABP
4
TABP
5
TABP
6
TABP
7
TABP
8
TABP
9
TABP
10
TABP
11
TABP
12
TABP
13
TABP
14
TABP
15
001001
09
TABP
16
TABP
17
TABP
18
TABP
19
TABP
20
TABP
21
TABP
22
TABP
23
TABP
24
TABP
25
TABP
26
TABP
27
TABP
28
TABP
29
TABP
30
TABP
31
001010
TABP
32*
TABP
33*
TABP
34*
TABP
35*
TABP
36*
TABP
37*
TABP
38*
TABP
39*
TABP
40*
TABP
41*
TABP
42*
TABP
43*
TABP
44*
TABP
45*
TABP
46*
TABP
47*
001011001100
0C
001101
0D
001110
0E
001111
0F
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BML
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
010000
010111
011000
011111
18–1F
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
• ** (SBK and RBK instructions) cannot be used in the M34524M8.
• * cannot be used after the SBK instruction is executed in the M34524MC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the
M34524MC/ED.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to
95 in the M34524MC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to
127 in the M34524ED.
(Ex. TABP 0 → TABP 64)
•
The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63.
10–17
000000
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-
tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
0A
TABP
48*
TABP
49*
TABP
50*
TABP
51*
TABP
52*
TABP
53*
TABP
54*
TABP
55*
TABP
56*
TABP
57*
TABP
58*
TABP
59*
TABP
60*
TABP
61*
TABP
62*
TABP
63*
0B
Rev.2.00 Jul 27, 2004 page 149 of 159
REJ03B0091-0200Z
4524 Group
INSTRUCTION CODE TABLE (continued)
–
–
TJ1A
–
TQ1A
TQ2A
TQ3A
–
–
–
TL1A
TL2A
–
TLCA
TW1A
TW2A
TW3A
TW4A
TW5A
TW6A
TK1A
TK2A
TMRA
TI1A
TI2A
–
TI3A
TK0A
–
–
–
–
T1AB
T2AB
T3AB
T4AB
–
TPSAB
–
T4HAB
TSIAB
TADAB
–
TR3AB
–
–
–
TR1AB
–
–
TAJ1
–
TAQ1
TAQ2
TAQ3
–
–
TALA
TAL1
TAW1
TAW2
TAW3
TAW4
TAW5
TAW6
–
TAMR
TAI1
TAI2
TAI3
TAK0
TAPU0
–
TAK1
TAK2
–
–
–
TAPU1
–
IAP0
IAP1
IAP2
IAP3
IAP4
–
–
–
–
–
–
–
–
–
–
–
TAB1
TAB2
TAB3
TAB4
–
TABPS
–
–
TABSI
TABAD
–
–
–
–
–
–
SNZT1
SNZT2
SNZT3
SNZT4
SNZT5
–
–
SNZAD
SNZSI
–
–
–
RCP
SCP
–
–
–
–
–
SVDE
–
–
–
T4R4L
–
–
CMCK
CRCK
DWDT
–
SST
ADST
WRST
–
–
–
–
–
–
–
–
–
TPAA
–
–
–
–
–
TAM
0
TAM
1
TAM
2
TAM
3
TAM
4
TAM
5
TAM
6
TAM
7
TAM
8
TAM
9
TAM
10
TAM
11
TAM
12
TAM
13
TAM
14
TAM
15
XAM
0
XAM
1
XAM
2
XAM
3
XAM
4
XAM
5
XAM
6
XAM
7
XAM
8
XAM
9
XAM
10
XAM
11
XAM
12
XAM
13
XAM
14
XAM
15
XAMI
0
XAMI
1
XAMI
2
XAMI
3
XAMI
4
XAMI
5
XAMI
6
XAMI
7
XAMI
8
XAMI
9
XAMI
10
XAMI
11
XAMI
12
XAMI
13
XAMI
14
XAMI
15
XAMD
0
XAMD
1
XAMD
2
XAMD
3
XAMD
4
XAMD
5
XAMD
6
XAMD
7
XAMD
8
XAMD
9
XAMD
10
XAMD
11
XAMD
12
XAMD
13
XAMD
14
XAMD
15
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
TMA
0
TMA
1
TMA
2
TMA
3
TMA
4
TMA
5
TMA
6
TMA
7
TMA
8
TMA
9
TMA
10
TMA
11
TMA
12
TMA
13
TMA
14
TMA
15
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
OP0A
OP1A
OP2A
OP3A
OP4A
–
–
–
TFR0A
TFR1A
TFR2A
TFR3A
–
TPU0A
TPU1A
–
D3–D0Hex.
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D9–D4
20
100001
21
100010
22
100011
23
100100
24
100101
25
100110
26
100111
27
101000
28
101001
29
101010
2A
101011
2B
101100
2C
101101
2D
101110
2E
101111
2F
110000
111111
30–3F
100000
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-
order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
Rev.2.00 Jul 27, 2004 page 150 of 159
REJ03B0091-0200Z
4524 Group
Parameter
Supply voltage
Input voltage
P0, P1, P2, P3, P4, D0–D7, RESET, XIN, XCIN, VDCE
Input voltage SCK, SIN, CNTR0, CNTR1, INT0, INT1
Input voltage AIN0–AIN7
Output voltage
P0, P1, P2, P3, P4, D
0
–D
9
, RESET, S
CK
, S
OUT
, CNTR0, CNTR1
Output voltage C, XOUT, XCOUT
Output voltage SEG0–SEG19, COM0–COM3
Power dissipation
Operating temperature range
Storage temperature range
Conditions
Output transistors in cut-off state
Ta = 25 °C
Symbol
VDD
VI
VI
VI
VO
VO
VO
Pd
Topr
Tstg
Unit
V
V
V
V
V
V
V
mW
°C
°C
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
–20 to 85
–40 to 125
ABSOLUTE MAXIMUM RATINGS
Rev.2.00 Jul 27, 2004 page 151 of 159
REJ03B0091-0200Z
4524 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VDD
VDD
VRAM
VSS
VLC3
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
IOH(peak)
IOH(peak)
IOH(avg)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
IOL(avg)
ΣIOH(avg)
ΣIOL(avg)
Parameter
Supply voltage
(when ceramic resonator is used)
Supply voltage
(when RC oscillation is used)
RAM back-up voltage
Supply voltage
LCD power supply (Note 1)
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“H” level peak output current
“H” level peak output current
“H” level average output current
(Note 2)
“H” level average output current
(Note 2)
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
(Note 2)
“L” level average output current
(Note 2)
“L” level average output current
(Note 2)
“H” level total average current
“L” level total average current
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
2: The average output current is the average value during 100 ms.
UnitConditions
Mask ROM version
One Time PROM version
f(STCK) ≤ 4.4 MHz
at RAM back-up mode
Mask ROM version
One Time PROM version
P0, P1, P2, P3, P4, D0–D7, VDCE
XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, P2, P3, P4, D0–D7, VDCE
XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, P4, D0–D6
SCK, SOUT
D7, C
CNTR0, CNTR1
P0, P1, P4, D0–D6
SCK, SOUT
D7, C
CNTR0, CNTR1
P0, P1, P4
D0–D9, C, SCK, SOUT,
CNTR0, CNTR1
P2, P3, RESET
P0, P1, P4
D0–D9, C, SCK, SOUT,
CNTR0, CNTR1
P2, P3, RESET
P0, P1, D0–D6, SCK, SOUT
P4, D7, C, CNTR0, CNTR1
P0, P1, D0–D6, SCK, SOUT
P2, P3, P4, D7–D9, C, RESET, CNTR0, CNTR1
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VDD
VDD
VDD
VDD
VDD
VDD
0.2VDD
0.3VDD
0.3VDD
0.15VDD
–20
–10
–30
–15
–10
–5
–20
–10
24
12
24
12
10
4
12
6
15
7
5
2
–60
–60
80
80
Limits
Min.
4
2.7
2
4
2.7
2.5
2.7
1.8
2
2.5
0.8VDD
0.7VDD
0.85VDD
0.8VDD
0
0
0
0
Typ.
0
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev.2.00 Jul 27, 2004 page 152 of 159
REJ03B0091-0200Z
4524 Group
f(XIN)
f(XIN)
f(XIN)
f(XCIN)
f(CNTR)
tw(CNTR)
f(SCK)
tw(SCK)
TPON
Oscillation frequency
(with a ceramic resonator)
Oscillation frequency
(at RC oscillation) (Note)
Oscillation frequency
(with a ceramic resonator selected,
external clock input)
Oscillation frequency (sub-clock)
Timer external input frequency
Timer external input period
(“H” and “L” pulse width)
Serial I/O external input frequency
Serial I/O external input frequency
(“H” and “L“ pulse width)
Power-on reset circuit
valid supply voltage rising time
Conditions
MHz
MHz
MHz
kHz
Hz
s
Hz
s
µs
Max.
6
4.4
2.2
6
4.4
6
6
4.4
2.2
6
4.4
6
4.4
4.8
3.2
1.6
4.8
3.2
4.8
4.8
3.2
1.6
4.8
3.2
4.8
50
f(STCK)/6
f(STCK)/6
100
100
Limits
Mask ROM
version
One T ime PROM
version
VDD = 2.7 to 5.5 V
Mask ROM
version
One T ime PROM
version
Quartz-crystal oscillator
CNTR0, CNTR1
CNTR0, CNTR1
SCK
SCK
Mask ROM version
One Time PROM version
Min.
3/f(STCK)
3/f(STCK)
Typ.
Parameter
Symbol Unit
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
VDD = 4 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
VDD = 2 to 5.5 V
VDD = 4 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 4 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
VDD = 2 to 5.5 V
VDD = 4 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 2.5 to 5.5 V
VDD = 0 → 2 V
VDD = 0 → 2.5 V
Through mode
Frequency/2 mode
Frequency/4, 8 mode
Through mode
Frequency/2 mode
Frequency/4, 8 mode
Through mode
Frequency/2 mode
Frequency/4, 8 mode
Through mode
Frequency/2 mode
Frequency/4, 8 mode
6
4.4
2.2
f(STCK)
[MHz]
2
(2.5) 2.7 5.5
4VVV
DD
[V]
➀ When ceramic resonator is used.
<System clock (STCK) Operating condition map>
Recommended
operating
condition
4.4
2.7 5.5
DD
[V]
➁ When RC oscillation is used.
f(STCK)
[MHz]
3.2
1.6
2
(2.5) 2.7 5.5
4
DD
[V]
➂ When external clock is used.
4.8
f(STCK)
[MHz]
Recommended
operating
condition
Recommended
operating
condition
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Rev.2.00 Jul 27, 2004 page 153 of 159
REJ03B0091-0200Z
4524 Group
VOH
VOH
VOL
VOL
VOL
IIH
IIL
“H” level output voltage
P0, P1, P4, D0–D6, SCK, SOUT
“H” level output voltage
D7, C, CNTR0, CNTR1
“L” level output voltage
P0, P1, P4
“L” level output voltage
D0–D9, C, SCK, SOUT, CNTR0, CNTR1
“L” level output voltage
P2, P3, RESET
“H” level input current
P0, P1, P2, P3, P4, D0–D7, VDCE,
RESET, CNTR0, CNTR1, INT0, INT1
“L” level input current
P0, P1, P2, P3, P4, D0–D7, VDCE,
SCK, SIN, CNTR0, CNTR1, INT0, INT1
V
V
V
V
V
µ
A
µ
A
Test conditions
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VI = VDD
VI = 0 V P0, P1 No pull-up
Limits Max.
2
0.9
0.9
0.6
2
0.9
1.4
0.9
2
0.6
0.9
1
–1
IOH = –10 mA
IOH = –3 mA
IOH = –5 mA
IOH = –1 mA
IOH = –20 mA
IOH = –6 mA
IOH = –10 mA
IOH = –3 mA
IOL = 12 mA
IOL = 4 mA
IOL = 6 mA
IOL = 2 mA
IOL = 15 mA
IOL = 5 mA
IOL = 9 mA
IOL = 3 mA
IOL = 5 mA
IOL = 1 mA
IOL = 2 mA
Min.
3
4.1
2.1
2.4
3
4.1
2.1
2.4
Typ.
Symbol Parameter Unit
ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Rev.2.00 Jul 27, 2004 page 154 of 159
REJ03B0091-0200Z
4524 Group
ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
IDD
RPU
VT+ – VT–
VT+ – VT–
f(RING)
∆f(XIN)
RCOM
RSEG
RVLC
Supply current
Pull-up resistor value
P0, P1, RESET
Hysteresis
SCK, SIN, CNTR0, CNTR1, INT0, INT1
Hysteresis RESET
On-chip oscillator clock frequency
Frequency error
(with RC oscillation,
error of external R, C not included )
(Note)
COM output impedance
SEG output impedance
Internal resistor for LCD power supply
at active mode
(with a ceramic resonator)
at active mode
(with a quartz-crystal
oscillator)
at clock operation mode
(POF instruction execution)
at RAM back-up mode
(POF2 instruction execution)
mA
mA
mA
µ
A
µ
A
µ
A
µ
A
kΩ
V
V
MHz
%
kΩ
kΩ
kΩ
Test conditions
VDD = 5 V
f(XIN) = 6 MHz
f(XCIN) = 32 kHz
VDD = 5 V
f(XIN) = 4 MHz
f(XCIN) = 32 kHz
VDD = 3 V
f(XIN) = 4 MHz
f(XCIN) = 32 kHz
VDD = 5 V
f(XIN) = stop
f(XCIN) = 32 kHz
VDD = 3 V
f(XIN) = stop
f(XCIN) = 32 kHz
f(XCIN) = 32 kHz
Ta = 25 °C
VDD = 5 V
VDD = 3 V
VI = 0 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V ± 10 %, Ta = 25 °C
VDD = 5 V ± 10 %, Ta = 25 °C
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
When dividing resistor 2r ✕ 3 selected
When dividing resistor 2r ✕ 2 selected
When dividing resistor r ✕ 3 selected
When dividing resistor r ✕ 2 selected
Limits Max.
2.8
3.2
4
5.6
2.2
2.4
3
4
0.8
1
1.2
1.6
110
120
130
140
24
26
28
30
60
15
1
10
6
125
250
3
1.8
±17
±17
7.5
10
7.5
10
960
640
480
320
Min.
30
50
1
0.5
300
200
150
100
Typ.
1.4
1.6
2
2.8
1.1
1.2
1.5
2
0.4
0.5
0.6
0.8
55
60
65
70
12
13
14
15
20
5
0.1
60
120
0.2
0.2
1
0.4
2
1
1.5
2
1.5
2
480
320
240
160
Symbol Parameter Unit
Note: When RC oscillation is used, use the external 33 pF capacitor (C).
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Rev.2.00 Jul 27, 2004 page 155 of 159
REJ03B0091-0200Z
4524 Group
Symbol
VDD
VIA
f(XIN)
Parameter
Supply voltage
Analog input voltage
Oscillation frequency
A/D CONVERTER CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Conditions Unit
V
V
MHz
Ta = 25 °C
Ta = –20 to 85 °C
VDD = 2.7 to 5.5 V
Min.
2.7
3
0
0.8
0.4
0.2
0.1
Typ. Max.
5.5
5.5
VDD
Limits
Symbol
–
–
–
V0T
VFST
IADD
TCONV
–
–
–
Parameter
Resolution
Linearity error
Differential non-linearity error
Zero transition voltage
Full-scale transition voltage
A/D operating current
(Note 1)
A/D conversion time
Comparator resolution
Comparator error (Note 2)
Comparator comparison time
Test conditions Unit
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Ta = –20 °C to 85 ° C, VDD = 3 V to 5.5 V
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Ta = –20 °C to 85 ° C, VDD = 3 V to 5.5 V
VDD = 5.12 V
VDD = 3.072 V
VDD = 5.12 V
VDD = 3.072 V
VDD = 5 V
VDD = 3 V
f(XIN) = 6 MHz
VDD = 5.12 V
VDD = 3.072 V
f(XIN) = 6 MHz
Min.
0
0
5110
3063
Typ.
10
6
5120
3069
0.3
0.1
Max.
10
±2
±0.9
20
12
5130
3075
0.9
0.3
248
124
62
31
8
±20
±15
32
16
8
4
Limits
Notes 1: When the A/D converter is used, IADD is added to IDD (supply current).
2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref = ✕ n
n = Value of register AD (n = 0 to 255)
VDD
256
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
bits
LSB
LSB
mV
mV
mA
µ
s
bits
mV
µ
s
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode selected, Ta = –20 °C to 85 °C, unless otherwise noted)
Rev.2.00 Jul 27, 2004 page 156 of 159
REJ03B0091-0200Z
4524 Group
Test conditions
Ta = 25 °C
at power down VDD = 5 V
(Note 2) VDD = 3 V
VDD → (VRST–0.1 V) (Note 3)
Parameter
Detection voltage (Note 1)
Operation current
Detection time
Symbol
VRST
IRST
TRST
Limits Unit
Min.
3.3
2.7
Typ.
3.5
50
30
0.2
Max.
3.7
4.2
100
60
1.2
V
µ
A
ms
Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: After the SVDE instruction is executed, the voltage drop detection circuit is valid at power down mode.
3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST–0.1 V].
STCK
P
a
r
a
m
e
t
e
r
P
i
n
(
s
i
g
n
a
l
)
n
a
m
e
M
a
c
h
i
n
e
c
y
c
l
e
M
iM
i
+
1
D
0
–
D
9
System clock
Port D output
P
o
r
t
D
i
n
p
u
t
P
o
r
t
s
P
0
,
P
1
,
P
2
,
P
3
,
P
4
o
u
t
p
u
t
P
o
r
t
s
P
0
,
P
1
,
P
2
,
P
3
,
P
4
i
n
p
u
t
D
0
–D
7
I
N
T
0
,
I
N
T
1I
n
t
e
r
r
u
p
t
i
n
p
u
t
P
0
0
–
P
0
3
P1
0
–P1
3
P
0
0
–
P
0
3
P
1
0
–
P
1
3
P2
0
–P2
3
P
3
0
–
P
3
3
P
2
0
–
P
2
3
P
3
0
–
P
3
3
P
4
0
–
P
4
3
P
4
0
–
P
4
3
BASIC TIMING DIAGRAM
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Rev.2.00 Jul 27, 2004 page 157 of 159
REJ03B0091-0200Z
4524 Group
Table 25 Product of built-in PROM version
PROM size
(✕ 10 bits)
16384 words
RAM size
(✕ 4 bits)
512 words
M34524EDFP One Time PROM [shipped in blank]64P6N-A
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4524 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing to
built-in PROM.
Table 25 shows the product of built-in PROM version. Figure 75
shows the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
ROM type
Package
Part number
Fig. 75 Pin configuration of built-in PROM version
PIN CONFIGURATION (TOP VIEW)
64
4
9
50
51
5
2
5
3
5
4
55
56
5
7
5
8
59
60
6
1
6
2
6
3
789101
1121
314151
6345612
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
D3
P
31/
AI
N
5
P
30/
AI
N
4
P
00
P
01
P
02
P
03
P
11
P
13
P
10
P
12
D1
D2
R
E
S
E
T
P
33/
AI
N
7
P
32/
AI
N
6
XC
O
U
T
XCIN
C
N
VS
S
XOUT
XIN
VSS
VD
D
D5/SOUT
D4/SIN
Outline 64P6N-A
48 4
74
24
140393
8373
63
5343
34
64
5444
3
SEG14
S
E
G1
5
S
E
G1
3
S
E
G1
2
D0
V
D
C
E
P
2
1
/
AI
N
1
P
2
2
/
AI
N
2
SEG6
SEG5
SEG4
SEG3
V
LC
1/SEG2
V
L
C
2/
S
E
G1
V
LC
3/SEG0
C
O
M0
C
O
M1
C
O
M2
C
O
M3
SEG7
SEG8
SEG9
SEG11
P
2
3
/
AI
N
3
S
E
G1
0
S
E
G1
6
D7/
C
N
T
R
0
C
/
C
N
T
R
1
D8/INT0
D9/
I
N
T
1
D6/S
CK
M34524EDFP
S
E
G1
9
P
20/
AI
N
0
S
E
G1
7
S
E
G1
8
P
41
P
40
P
43
P
42
Rev.2.00 Jul 27, 2004 page 158 of 159
REJ03B0091-0200Z
4524 Group
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a nor-
mal operation mode. The PROM mode is used to write to and read
from the built-in PROM.
In the PROM mode, the programming adapter can be used with a
general-purpose PROM programmer to write to or read from the
built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 26. Contact addresses at
the end of this data sheet for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the PROM of
the built-in PROM version as shown in Figure 76.
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➁For the One Time PROM version shipped in blank, Renesas
Technology corp. does not perform PROM writing test and
screening in the assembly process and following processes. In
order to improve reliability after writing, performing writing and
test according to the flow shown in Figure 77 before using is rec-
ommended (Products shipped in blank: PROM contents is not
written in factory when shipped).
Fig. 76 PROM memory map
Writi n g with PROM pro g ramm e r
Screening (Leave at 150 °C for 40 hours) (Note)
Veri fy test with PROM programmer
Function test in target de vice
S
i
n
c
e
t
h
e
s
c
r
e
e
n
i
n
g
t
e
m
p
e
r
a
t
u
r
e
i
s
h
i
g
h
e
r
t
h
a
n
s
t
o
r
a
g
e
t
e
m
p
e
r
a
t
u
r
e
,
n
e
v
e
r
e
x
p
o
s
e
t
h
e
m
i
c
r
o
c
o
m
p
u
t
e
r
t
o
1
5
0
°
C
e
x
c
e
e
d
i
n
g
1
0
0
h
o
u
r
s
.
N
o
t
e
:
Fig. 77 Flow of writing and test of the product shipped in blank
A
d
d
r
e
s
s
0
0
0
01
6
3
F
F
F1
6
7
F
F
F1
6
111D4D3D2D1D0
H
i
g
h
-
o
r
d
e
r
5
b
i
t
s
111D4D3D2D1D0
L
o
w
-
o
r
d
e
r
5
b
i
t
s
4
0
0
01
6
Part number
M34524EDFP Name of Programming Adapter
PCA7448
Table 26 Programming adapter
Rev.2.00 Jul 27, 2004 page 159 of 159
REJ03B0091-0200Z
4524 Group
PACKAGE OUTLINE
QFP64-P-1414-0.80 1.11
Weight(g)
—
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
64P6N-A Plastic 64pin 14✕14mm body QFP
——
——
—
—
——
—
———
—
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A10.20.1
0.5 ——
I21.3 ——
MD14.6 ——
ME14.6
10¡0¡0.1
1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8
03.05
e
e
e
E
c
HE
1
64 49
32
48
33
17
16
HD
D
MD
ME
A
F
b
A1A2
L1
L
y
b2
I2
Recommended Mount Pad
Detail F
REVISION HISTORY
Rev. Date Description
Page Summary
4524 Group Data Sheet
1.00 Oct. 11, 2001
1.10 Nov. 07, 2001
2.00 Jul. 27, 2004
First edition issued
Note; f(RING) → f(RING)/8
Table 4; (th second) External 0 interrupt → External 1 interrupt
(13); • Prescaler; reload register RPS → prescaler data
(2); timer 2 count source selection bit → timer LC count source selection bit
(5); • Internal dividing registor; by setting bit 2 of register L1 to “0”
Fig. 53; Stabilizing time e ; high → low,
Note 1; power down → clock operating
➄ Prescaler ; reload register RPS → prescaler data
TAK0, TK0A, TAK1, TK1A, TAK2, TK2A instructions revised
RBK; Flag CY; “0” → “–”
SBK (Reset Bank Flag) → SBK (Set Bank Flag)
TAB; Grouping; Other operations → Register to register transfer
TAL1 (Transfer data to Accumulator from register LA)
→ TAL1 (Transfer data to Accumulator from register L1)
TAK0, TK0A, TAK1, TK1A, TAK2, TK2A instructions revised
WRST, DWDT instructions revised
Words standardized: On-chip oscillator, A/D converter
Power dissipation revised.
____________
Description of RESET pin revised.
Table 6: Notes added.
Fig.26 : Note 9 added.
Some description revised.
Fig.31: “DI” instruction added.
Table 11:Revised.
(5) LCD power supply circuit revised.
Fig.51: State of quartz-crystal oscillator added.
VOLTAGE DROP DETECTION CIRCUIT revised.
Table 21: Port level revised and Note 7 added.
Fig.55:
• Note 5 added,
• “T5F” added to the transitions between from state E to states B, A, C and D
• “Key-on wakeup”→“Wakeup”
Note on Voltage drop detection circuit added.
Note on Difference between Mask ROM version and One Time PROM version added.
Note on Power Source Voltage added.
Condition of IOL(peak) and IOL(avg) revised.
–
6
22
40
57
61
69
75
90
102
104
111
116
145
147
All pages
4
5
24
34
44
45
46
61
65
66
67
69
78
151
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
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Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
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©2001, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0
