MX29F001TQC-55 - Macronix International Co., Ltd.

P/N: PM0515

FEATURES

• 5.0V ± 10% for read, erase and write operation

• 131072x8 only organization

• Fast access time: 55/70/90/120ns

• Low power consumption

- 30mA maximum active current(5MHz)

-1uA typical standby current

• Command register architecture

- Byte Programming (7us typical)

- Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte

x 2, 32K-Byte x 1, and 64K-Byte x 1)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors

with Erase Suspend capability.

- Automatically programs and verifies data at

specified address

• Erase Suspend/Erase Resume

– Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

• Chip protect/unprotect for 5V only system or 5V/12V

system

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 32-pin PLCC

- 32-pin TSOP

- 32-pin PDIP

• Boot Code Sector Architecture

- T=Top Boot Sector

- B=Bottom Boot Sector

• 20 years data retention

GENERAL DESCRIPTION

The MX29F001T/B is a 1-mega bit Flash memory

organized as 128K bytes of 8 bits only MXIC's

Flash memories offer the most cost-effective and

reliable read/write non-volatile random access

memory. The MX29F001T/B is packaged in 32-pin

PLCC, TSOP, PDIP. It is designed to be repro-

grammed and erased in-system or in-standard

EPROM programmers.

The standard MX29F001T/B offers access time as

fast as 55ns, allowing operation of high-speed

microprocessors without wait states. To eliminate

bus contention, the MX29F001T/B has separate

chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM function-

ality with in-circuit electrical erasure and

programming. The MX29F001T/B uses a command

and fixed power supply levels during erase and

programming, while maintaining maximum EPROM

compatibility.

MXIC Flash technology reliably stores memory con-

tents even after 100,000 erase and program cycles.

The MXIC cell is designed to optimize the erase and

programming mechanisms. In addition, the combi-

nation of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling. The

MX29F001T/B uses a 5.0V ± 10% VCC supply to

perform the High Reliability Erase and auto

Program/Erase algorithms.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

MX29F001T/B

1M-BIT [128K x 8] CMOS FLASH MEMORY

REV. 2.5, NOV. 20, 2002

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MX29F001T/B

PIN CONFIGURATIONS

32 TSOP (TYPE 1) PIN DESCRIPTION:

(NORMAL TYPE)

SECTOR STRUCTURE

MX29F001T Sector Architecture MX29F001B Sector Architecture

SYMBOL PIN NAME

A0~A16 Address Input

Q0~Q7 Data Input/Output

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

VCC Power Supply Pin (+5V)

GND Ground Pin

MX29F001T/B

A16

A15

A12

GND

VCC

A14

A13

A11

A10

14 17 20

32 30 A14

A13

A11

A10

GND

A12

A15

A16

VCC

MX29F001T/B

A11

A13

A14

VCC

A16

A15

A12

A10

GND

MX29F001T/B

8 K-BYTE

00000H

64 K-BYTE

32 K-BYTE

8 K-BYTE

4 K-BYTE

1FFFFH

0FFFFH

05FFFH

02FFFH

01FFFH

03FFFH

A16~A0

07FFFH

64 K-BYTE

00000H

8 K-BYTE

4 K-BYTE

8 K-BYTE

32 K-BYTE

1FFFFH

1DFFFH

1CFFFH

19FFFH

17FFFH

0FFFFH

1BFFFH

A16~A0

32 PLCC32 PDIP

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MX29F001T/B

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

MX29F001T/B

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q7

A0-A16

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MX29F001T/B

AUTOMATIC PROGRAMMING

The MX29F001T/B is byte programmable using the Au-

tomatic Programming algorithm. The Automatic Program-

ming algorithm does not require the system to time out

or verify the data programmed. The typical chip pro-

gramming time of the MX29F001T/B at room tempera-

ture is less than 3.5 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 3 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

internally controlled within the device.

AUTOMATIC SECTOR ERASE

The MX29F001T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are inter-

nally con trolled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (include 2

unlock write cycle and A0H) and a program command

(progr am data and address). The de vice automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to D ATA polling and a status bit tog-

gling between consecutive read cycles, provides feed-

back to the user as to the status of the programming

operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches addresses and data needed for the pro-

gramming and erase operations. During a system write

cycle, addresses are latched on the falling edge, and

data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM

e xperience to produce the highest lev els of quality, reli-

ability, and cost effectiv eness. The MX29F001T/B elec-

trically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot elec-

tron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

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MX29F001T/B

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RD RD

Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Chip Protect Verify 4 555H AAH 2AAH 55H 555H 90H (SA) 00H

X02H 01H

Program 4 555H AAH 2AAH 55H 555H A0H PA PD

Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55 H SA 30 H

Sector Erase Suspend 1 XXXH B0H

Sector Erase Resume 1 XXXH 3 0H

Unlock for chip 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H

protect/unprotect

TABLE 1. SOFTWARE COMMAND DEFINITIONS

Note:

1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to

Table 3)

DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.

Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A16 in either state.

4. For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data

is 00H, it means the chip is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing

them in the improper sequence will reset the device to

the read mode. Table 1 defines the valid register

command sequences. Note that the Erase Suspend

(B0H) and Erase Resume (30H) commands are valid

only while the Sector Erase operation is in progress.

Either of the two reset command sequences will reset

the device(when applicable).

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MX29F001T/B

Pins C E OE W E A0 A1 A6 A9 Q0 ~ Q7

Mode

Read Silicon ID L L H L L X VID(2) C2H

Manufacturer Code(1)

Read Silicon ID L L H H L X VID(2) 18H/19H

Device Code(1)

Read L L H A0 A1 A6 A9 DOUT

Standby H X X X X X X HIGH Z

Output Disable L H H X X X X HIGH Z

Write L H L A0 A1 A6 A9 DIN(3)

Chip Protect with 12V L VID(2) L X X L VID(2) X

system(6)

Chip Unprotect with 12V L VID(2) L X X H VID(2) X

system(6)

Verify Chip Protect L L H X H X VID(2) Code(5)

with 12V system

Chip Protect without 12V L H L X X L H X

system (6)

Chip Unprotect without 12V L H L X X H H X

system (6)

Verify Chip Protect/Unprotect L L H X H X H Code(5)

without 12V system (7)

Reset X X X X X X X HIGH Z

TABLE 2. MX29F001T/B BUS OPERATION

NOTES:

1. Manufacturer and device codes ma y also be accessed via a command register write sequence. Refer to Tab le 1.

2. VID is the Silicon-ID-Read high voltage , 11.5V to 12.5V.

3. Refer to Table 1 f or valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system"

command.

7. The "verify chip protect/unprotect without 12V system" is only following "Chip protect/unprotect without 12V

system" command.

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MX29F001T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Microprocessor read cycles retrieve array data. The de-

vice remains enabled for reads until the command regis-

ter contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage . Howe ver , multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

The MX29F001T/B contains a Silicon-ID-Read operation

to supplement traditional PROM programming method-

ology. The operation is initiated by writing the read sili-

con ID command sequence into the command register .

Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 18H for MX29F001T,19H for MX29F001B.

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Code

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H

Device code VIH VIL 0 0 0 1 1 0 0 0 18H

for MX29F001T

Device code VIH VIL 0 0 0 1 1 0 0 1 19H

for MX29F001B

Chip Protection Verification X VIH 0 0 0 0 0 0 0 1 01H (Protected)

X VIH 0 0 0 0 0 0 0 0 00H (Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

SET-UP AUTOMATIC CHIP ERASE COM-

MANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are f ollow ed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero pat-

tern, a self-timed chip erase and verification begin. The

erase and verification operations are completed when

the data on Q7 is "1" at which time the device returns to

the Read mode. The system does not require to pro-

vide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no

erase verify command is required).

If the Erase operation was unsuccessful, the data on Q5

is "1"(see T able 4), indicating an erase operation e xceed

internal timing limit.

The automatic erase begins on the rising edge of the

last WE pulse in the command sequence and terminates

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode.

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MX29F001T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Set-up Sector Erase command and Automatic

Sector Erase command. Upon executing the Automatic

Sector Erase command, the device will automatically

program and verify the sector(s) memory for an all-zero

data pattern. The system does not require to provide

any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verifi-

cation begin. The erase and v erification operations are

complete when the data on Q7 is "1" and the data on Q6

stops toggling for two consecutive read cycles, at which

time the device returns to the Read mode. The system

does not require to provide any control or timing during

these operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector erase

is a six-bus cycle operation. There are two "unlock" write

cycles. These are followed by writing the set-up com-

mand 80H. Two more "unlock" write cycles are then fol-

lowed by the sector erase command 30H. The sector

address is latched on the falling edge of WE, while the

command(data) is latched on the rising edge of WE. Sec-

tor addresses selected are loaded into internal register

on the sixth falling edge of WE. Each successive sector

load cycle started by the f alling edge of WE must begin

within 30us from the rising edge of the preceding WE.

Otherwise, the loading period ends and internal auto sec-

tor erase cycle starts. (Monitor Q3 to determine if the

sector erase timer window is still open, see section Q3,

Sector Erase Timer.) Any command other than Sector

Erase (30H) or Erase Suspend (B0H) during the time-out

period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. Writing the Erase Suspend com-

mand during the Sector Erase time-out immediately ter-

minates the time-out immediately terminates the time-

out period and suspends the erase operation. After this

command has been executed, the command register will

initiate erase suspend mode. The state machine will re-

turn to read mode automatically after suspend is ready .

At this time, state machine only allows the command

Resume and Program commands.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

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MX29F001T/B

Status Q7 Q6 Q5 Q3

Byte Program in Auto Program Algorithm Q 7 Toggle 0 N/A

In Progress Auto Erase Algorithm 0 Toggle 0 1

Erase Suspended Mode Erase Suspend Read Data Data Data Data

Erase Suspend Program Q7 Toggle 0 N/A

(Non-Erase Suspended Sector) (Note1)

Byte Program in Auto Program Algorithm Q 7 Toggle 1 N/A

Exceeded Erase in Auto Erase Algorithm 0 Toggle 1 1

Time Limits Erase Suspended Mode Erase Suspend Program Q7 Toggle 1 N/A

(Non-Erase Suspended Sector)

Table 4. Write Operation Status

Note:

1. P erf orming successive read operations from an y address will cause Q6 to toggle.

10 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are followed by writing the Automatic Pro-

gram command A0H.

Once the Automatic Program command is initiated, the

next WE pulse causes a transition to an active program-

ming operation. Addresses are latched on the falling

edge, and data are internally latched on the rising edge

of the WE pulse. The rising edge of WE also begins the

programming operation. The system does not require to

provide further controls or timings. The device will auto-

matically provide an adequate internally generated pro-

gram pulse and verify margin.

If the program operation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the program operation

exceed internal timing limit. The automatic programming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data on

Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode

(no program verify command is required).

WRITE OPERATION STATUS

TOGGLE BIT-Q6

The MX29F001T/B features a "Toggle Bit" as a method

to indicate to the host system that the Auto Program/

Erase algorithms are either in progress or complete.

While the Automatic Program or Erase algorithm is in

progress, successive attempts to read data from the

de vice will result in Q6 toggling betw een one and z ero.

Once the Automatic Program or Erase algorithm is com-

pleted, Q6 will stop toggling and valid data will be read.

The toggle bit is valid after the rising edge of the sixth

WE pulse of the six write pulse sequences for chip/sec-

tor erase.

The Toggle Bit feature is active during Automatic Pro-

gram/Erase algorithms or sector erase time-out. (see

section Q3 Sector Erase Timer)

DATA POLLING-Q7

The MX29F001T/B also features Data Polling as a

method to indicate to the host system that the Auto-

matic Program or Erase algorithms are either in progress

or completed.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the comple-

ment data of the data last written to Q7. Upon comple-

tion of the Automatic Program Algorithm an attempt to

read the device will produce the true data last written to

Q7. The Data Polling feature is valid after the rising edge

of the fourth WE pulse of the four write pulse sequences

for automatic program.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data Polling feature is valid after the rising

edge of the sixth WE pulse of six write pulse sequences

for automatic chip/sector erase.

The Data P olling feature is activ e during Automatic Pro-

gram/Erase algorithm or sector erase time-out.(see sec-

tion Q3 Sector Erase Timer)

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MX29F001T/B

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data Polling and Toggle Bit are the

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during sector erase op-

eration, it is specifies that a particular sector is bad and

it may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. The device must be reset to use other sec-

tors. Write the Reset command sequence to the device,

and then execute program or erase command sequence.

This allows the system to continue to use the other ac-

tive sectors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

Sector Erase Timer

After the completion of the initial sector erase command

sequence the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and T oggle Bit are valid after the initial sector erase com-

mand sequence.

If Data P olling or the Toggle Bit indicates the de vice has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the de vice will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

DATA PROTECTION

The MX29F001T/B is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory con-

tents only occurs after successful completion of spe-

cific command sequences. The device also incorporates

several features to prevent inadvertent write cycles re-

sulting from VCC power-up and power-down transition or

system noise.

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MX29F001T/B

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =

VIH or WE = VIH. To initiate a wr ite cycle CE and WE

must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND. (Using a 10uF b ulk capacitor

connected for high current condition is available if nec-

essary.)

CHIP PROTECTION WITH 12V SYSTEM

The MX29F001T/B features hardware chip protection.

Which will disable both program and erase operations.

To activate this mode, the programming equipment must

force VID on address pin A9 and control pin OE, (sug-

gest VID=12V) A6=VIL and CE=VIL.(see Tab le 2) Pro-

gramming of the protection circuitry begins on the falling

edge of the WE pulse and is terminated with the rising

edge of the same. Please refer to chip protect algorithm

and waveform.

To verify programming of the protection circuitry , the pro-

gramming equipment must force VID on address pin A9

( with CE and OE at VIL and WE at VIH. When A1=1, it

will produce a logical "1" code at device output Q0 for

the protected status. Otherwise the device will produce

00H for the unprotected status. In this mode, the ad-

dress, except for A1, are don't care. Address locations

with A1 = VIL are reserved to read manufacturer and

device codes.(Read Silicon ID)

It is also possible to determine if the chip is protected in

the system by writing a Read Silicon ID command. P er-

forming a read operation with A1=VIH, it will produce a

logical "1" at Q0 for the protected status.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F001T/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect completion to incorporate any changes in the

code.

To activate this mode, the programming equipment must

force VID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.(see

Table 2) Refer to chip unprotect algorithm and wave-

form for the chip unprotect algorithm. The unprotection

mechanism begins on the f a lling edge of the WE pulse

and is terminated with the rising edge of the same.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs (Q0-Q7) for an unprotected sector. It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F001T/B also feature a hardware chip protec-

tion method in a system without 12V pow er supply. The

programming equipment do not need to supply 12 volts

to protect all sectors. The details are shown in chip pro-

tect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F001T/B also feature a hardware chip

unprotection method in a system without 12V power sup-

ply. The progr amming equipment do not need to supply

12 volts to unprotect all sectors. The details are shown

in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

The MX29F001T/B powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command se-

quences.

13 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature 0oC to 70oC

Storage Temperature -65oC to 125oC

Applied Input Voltage -0.5V to 7.0V

Applied Output Voltage -0.5V to 7.0V

VCC to Ground Potential -0.5V to 7.0V

A9 & OE -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage

to the device. This is a stress rating only and

functional operational sections of this specification is

not implied. Exposure to absolute maximum rating

conditions for extended period may affect reliability.

NOTICE:

Specifications contained within the following tables are

subject to change.

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V

CIN2 Control Pin Capacitance 12 pF VIN = 0V

COUT Output Capacitance 12 p F VOUT = 0V

READ OPERATION

DC CHARACTERISTICS VCC = 5V ± 10% (VCC = 5V ± 5% for 29F001T/B-55)

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 1 uA VIN = GND to VCC

IL O Output Leakage Current 1 0 u A VOUT = GND to VCC

ISB1 Standby VCC current 1 mA CE = VIH

ISB2 1 5 uA CE = VCC + 0.3V

ICC1 Operating VCC current 30 mA IOUT = 0mA, f=5MHz

ICC2 50 mA IOUT = 0mA, f=10MHz

VIL Input Low Voltage -0.3(NOTE 1) 0.8 V

VIH Input High Voltage 2.0 VCC + 0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA

VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA

VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA

VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is ov er the specified maximum v alue, read operation cannot be guar anteed.

CAPACITANCE TA = 25oC, f = 1.0 MHz

14 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AC CHARACTERISTICS VCC = 5V ± 10% (5V ± 5% for MX29F001T/B-55)

NOTE:

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V for 70ns max. ; 0V/3.0V

for 55ns

• Input rise and fall times: <10ns for 70ns max; <5ns for

55ns

• Output load: 1 TTL gate + 100pF (Including scope and

jig) for 70ns max. ; 1 TTL gate + 30pF (Including scope

and jig) for 55ns max.

• Reference levels for measuring timing : 0.8V & 2.0V for

70ns max.; 1.5V for 55ns

29F001T/B-55 29F001T/B-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 5 5 7 0 ns CE=OE=VIL

tCE CE to Output Delay 5 5 7 0 ns OE=VIL

tOE OE to Output Delay 3 0 40 ns CE=VIL

tDF OE High to Output Float (Note1) 0 2 0 0 2 0 ns CE=VIL

tO H Address to Output hold 0 0 ns CE=OE=VIL

29F001T/B-90 29F001T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 9 0 1 2 0 ns CE=OE=VIL

tCE CE to Output Delay 9 0 1 2 0 ns OE=VIL

tOE OE to Output Delay 4 0 50 ns CE=VIL

tDF OE High to Output Float (Note1) 0 3 0 0 3 0 ns CE=VIL

tO H Address to Output hold 0 0 ns CE=OE=VIL

15 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=5MHz

ICC2 50 mA IOUT=0mA, F=10MHz

ICC3 (Program) 50 mA In Programming

ICC4 (Erase) 50 mA In Erase

ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

NOTES:

1. VIL min. = -0.6V for pulse width < 20ns.

2. If VIH is over the specified maxim um value, prog ramming operation cannot be guaranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

READ TIMING WAVEFORMS

A0~16

tACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

D ATA V alid

tOE tDF

tCE

DATA

Q0~7

tOH

ADD V alid

DC CHARACTERISTICS VCC = 5V ± 10% (VCC = 5V ± 5% for 29F001T/B-55)

16 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

29F001T/B-70 29F001T/B-90 29F001T/B-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT

tOES OE setup time 0 0 0 ns

tCWC Command programming cycle 70 90 120 ns

tCEP WE programming pulse width 45 45 50 ns

tCEPH1 WE programming pulse width High 20 20 20 ns

tCEPH2 WE programming pulse width High 20 20 20 ns

tAS Address setup time 0 0 0 ns

tAH Address hold time 4 5 45 5 0 ns

tDS Data setup time 3 0 4 5 50 ns

tDH Data hold time 0 0 0 ns

tCESC CE setup time before command write 0 0 0 ns

tDF Output disable time (Note 1) 3 0 4 0 4 0 ns

tAETC Total erase time in auto chip erase 3(TYP.) 24 3(TYP.) 24 3(TYP.) 24 s

tAETB Total erase time in auto sector erase 1(TYP.) 8 1(TYP.) 8 1(TYP.) 8 s

tAVT Total programming time in auto verify 7 210 7 210 7 2 1 0 us

tBAL Sector address load time 100 1 00 1 00 us

tCH CE Hold Time 0 0 0 ns

tCS CE setup to WE going low 0 0 0 ns

tVLHT Voltage Transition Time 4 4 4 us

tOESP OE Setup Time to WE Active 4 4 4 us

tWPP Write pulse width for chip protect 1 0 1 0 10 us

tWPP2 Write pulse width for chip unprotect 1 2 1 2 1 2 ms

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

AC CHARACTERISTICS VCC = 5V ± 10% (VCC = 5V ± 5% for 29F001T/B-55)

17 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AC CHARACTERISTICS VCC = 5V ± 5% for MX29F001T/B-55

29F001T/B-55

SYMBOL PARAMETER MIN. MAX. UNIT

tOES OE setup time 0 ns

tCWC Command programming cycle 70 ns

tCEP WE programming pulse width 45 ns

tCEPH1 WE programming pulse width High 20 ns

tCEPH2 WE programming pulse width High 20 ns

tAS Address setup time 0 ns

tAH Address hold time 4 5 ns

tDS Data setup time 2 0 ns

tDH Data hold time 0 ns

tCESC CE setup time before command write 0 ns

tDF Output disable time (Note 1) 2 0 ns

tAETC Total erase time in auto chip erase 3(TYP.) 24 s

tAETB Total erase time in auto sector erase 1(TYP.) 8 s

tAVT Total programming time in auto verify 7 2 1 0 us

tBAL Sector address load time 1 00 us

tCH CE Hold Time 0 ns

tCS CE setup to WE going low 0 ns

tVLHT Voltage Transition Time 4 us

tOESP OE Setup Time to WE Active 4 us

tWPP Write pulse width for chip protect 1 0 us

tWPP2 Write pulse width for chip unprotect 1 2 ms

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

18 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS(I) for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12

SWITCHING TEST WAVEFORMS(II) for 29F001T/B-55

3.0 V

0 V

1.5V TEST POINTS

INPUT

1.5V

OUTPUT

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

2.0V

2.4 V

0.45 V 0.8V TEST POINTS

INPUT

2.0V

0.8V

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 10ns.

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 1.2K ohm

1.6K ohm +5V

CL=100pF Including jig capacitance for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12

30pF Including jig capacitance for 29F001T/B-55

19 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

COMMAND WRITE TIMING WAVEFORM

ADD

A0~16

DIN

tDS

tAH

DATA

Q0-7

tDH

tCS tCH

tCWC

tCEPH1

tCEP

tOES

tAS

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

20 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verification in fast

algorithm and additional programming by external control

are not required because these operations are executed

automatically by internal control circuit. Programming

completion can be verified by DATA polling and toggle bit

AUTOMATIC PROGRAMMING TIMING WAVEFORM

checking after automatic verify starts. Device outputs

DATA during programming and DATA after programming

on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,

timing waveform)

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

Q0~Q2

,Q4(Note 1)

A11~A16

tCEPH1

tAH

ADD V alid

tCESC

Command In

ADD V alid

A0~A10

Command InCommand In Data In DATA

Command In Command InCommand In Data In DATADATA

tAVT

tOE

DATA polling

2AAH

555H 555H

Command #AAH Command #55H Command #A0H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

21 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Verify Byte Ok

YES

Q5 = 1

Reset

Auto Program Completed

Auto Program Exceed

Timing Limit

Invalid

Command

YES

NO .

22 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

TOGGLE BIT ALGORITHM

Notes:

1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text.

2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.

START

Read Q7~Q0

YES

Toggle Bit Q6

=Toggle?

Q5=1?

YES

(Note 1)

Read Q7~Q0 Twice (Note 1,2)

Toggle Bit Q6=

Toggle?

Program/Erase Operation Not

Complete, Write Reset Command

YES

Program/Erase Operation Complete

23 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

matic erase starts. Device outputs 0 during erasure and

1 after erasure 0n Q7.(Q6 is for toggle bit; see toggle bit,

DATA polling, timing waveform)

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be veri-

fied by DATA polling and toggle bit checking after auto

AUTOMATIC CHIP ERASE TIMING WAVEFORM

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A16

tCEPH1

tAH

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETC

DATA polling

2AAH

555H 555H

Command #AAH Command #55H Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H 2AAH 555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

AUTOMATIC CHIP ERASE TIMING WAVEFORM

24 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Reset

Auto Chip Erase Exceed

Timing Limit

DATA Polling

Q7 = 1

YES

Q5 = 1

Auto Chip Erase Completed

NO .

Invalid

Command

25 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector data indicated by A13 to A16 are erased. External

erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

during erasure and 1 after erasure on Q7.(Q6 is for toggle

bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tAH

Sector

Address0

555H 2AAH 2AAH

555H 555H

Sector

Address1 Sector

Addressn

Vcc 5V

Q0,Q1,

Q4(Note 1)

A13~A16

A0~A10

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

26 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO .

Toggle Bit Checking

Q6 not Toggled

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Reset

Auto Sector Erase

Exceed Timing

DATA Polling

Q7 = 1

Q5 = 1

Auto Sector Erase Completed

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

YES

Last Sector

to Erase

Time-out Bit

Checking Q3=1 ?

Toggle Bit Checking

Q6 Toggled ? Invalid Command

YES

27 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO .

YES

28 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V

tOE

Data

12V

tOESP

tWPP 1

tVLHT

Verify

01H F0H

29 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

tOE

Data

12V

tOESP

tWPP 2

tVLHT

Verify

00H

F0H

30 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

PLSCNT=1

Chip Protection

Complete

Data=01H?

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

Device Failed

31 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Set OE=CE=VIL

A9=VID,A1=1

Remove VID from A9

Write Reset Command Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes Yes

32 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

* See the following Note!

Verify

01H

Note: 1. Must issue "unlock for sector protect/unprotect" command

before chip protection for a system without 12V provided.

2. Except F0H

Toggle bit polling

Don't care

(Note 2)

tCEP

F0H

33 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

Verify

00H

Note: 1. Must issue "unlock for sector protect/unprotect" command

before chip unprotection for a system without 12V provided.

2. Except F0H

tCEP

Toggle bit polling

Don't care

(Note 2)

* See the following Note!

F0H

34 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Chip Protection

Complete

Data=01H?

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Set CE=OE=VIL

A9=VIH

Raed from Sector

Addr=SA, A1=1

Write Reset Command

Device Failed

PLSCNT=32?

Yes

Increment PLSCNT

Write "unlock for chip protect/unprotect"

Command(Table1)

Toggle bit checking

DQ6 not Toggled No .

Yes

35 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Set OE=A9=VIH

CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

Set OE=CE=VIL

A9=VIH,A1=1

Write Reset Command Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes Yes

Write "unlock for chip protect/unprotect"

Command (Table 1)

Toggle bit checking

DQ6 not Toggled

Yes

36 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H 18H/19H

VID

VIH

VIL

ADD

A2-A8

A10-A16

DATA OUT

DATA

Q0-Q7

VCC 5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

37 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V

Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V

Current -100mA +100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 1 8 s

Chip Erase Time 3 2 4 s

Byte Programming Time 7 2 10 us

Chip Programming Time 3.5 10.5 sec

Erase/Program Cycles 100,000 Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE (1)

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C, 5V.

3.Maximum values measured at 25°C, 4.5V.

PARAMETER MIN. UNIT

Data Retention Time 2 0 Years

DATA RETENTION

38 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

ORDERING INFORMATION

PLASTIC PACKAGE (Top Boot Sector as an sample For Bottom Boot Sector ones,MX29F001Txx will

change to MX29F001Bxx)

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE

(ns) MAX.(mA) MAX.(uA)

MX29F001TQC-55 55 30 5 32 Pin PLCC

MX29F001TQC-70 70 3 0 5 32 Pin PLCC

MX29F001TQC-90 90 3 0 5 32 Pin PLCC

MX29F001TQC-12 120 3 0 5 32 Pin PLCC

MX29F001TTC-55 5 5 3 0 5 32 Pin TSOP

(Normal Type)

MX29F001TTC-70 70 30 5 32 Pin TSOP

(Normal Type)

MX29F001TTC-90 90 30 5 32 Pin TSOP

(Normal Type)

MX29F001TTC-12 120 30 5 32 Pin TSOP

(Normal Type)

MX29F001TPC-55 55 30 5 32 Pin PDIP

MX29F001TPC-70 70 30 5 32 Pin PDIP

MX29F001TPC-90 90 30 5 32 Pin PDIP

MX29F001TPC-12 12 0 30 5 32 Pin PDIP

39 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

PACKAGE INFORMATION

40 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

41 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

42 REV. 2.5,NOV. 20, 2002P/N: PM0515

MX29F001T/B

Revision Description Page Date

2. 0 1. To remov e "Advanced Information" data sheet marking and P1 DEC/21/1999

contain information on products in full production

2.The modification summary from Revision 0.0 to Revision 1.0:

2-1.Program/erase cycle times:10K cycles-->100K cycles P1,38

2-2.To add data retention 20 years P1,38

2-3.To remov e A9 from the timing wa v ef orm of protection/ P32,33

unprotection without 12V

2-4.Multi-sector erase time out:80ms-->30us P8

2-5.tBAL:80us-->100us P16,17

2. 1 To modify "Package Information" P39~41 JUN/14/2001

2.2 T o corrected typing error All JUL/01/2002

2.3 1. Add industrial grade spec P13,38 JUL/09/2002

2. Modify maximum value measurement temperature from 25°C to 85°C P37

2.4 1. Remove industrial grade spec P13,37,38 AUG/12/2002

2. 5 1. To modify P ackage Information P39~41 NOV/20/2002

REVISION HISTORY

MX29F001T/B

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