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FAN54063 High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Features Description The FAN54063 is a 1.55 A USB-compliant switch-mode charger featuring power path operation, USB OTG boost support, JEITA temperature control, and production test mode support, in a small 25 bump, 0.4 mm pitch WLCSP package. Fully Integrated, High-Efficiency Switch-Mode Charger for Single-Cell Li-Ion and Li-Polymer Batteries Power Path Circuit Ensures Fast System Startup with a Dead Battery when VBUS is Connected 1.55 A Maximum Charge Current Programmable High Accuracy Float Voltage: - 0.5% at 25C - 1% from 0 to 125C 5% Input and Charge Current Regulation Accuracy Temperature-Sense Input for JEITA Compliance Thermal Regulation and Shutdown 4.2 V at 2.3 A Production Test Support 5 V, 500 mA Boost Mode for USB OTG 28 V Absolute Maximum Input Voltage 6 V Maximum Input Operating Voltage 2 Programmable through High-Speed I C Interface (3.4 Mb/s) with Fast Mode Plus Compatibility - Input Current - Fast-Charge / Termination Current - Float Voltage - Termination Enable 3 MHz Synchronous Buck PWM Controller with Wide Duty Cycle Range Small Footprint 1 H External Inductor Safety Timer with Reset Control Dynamic Input Voltage Control Very Low Battery Current when Charger Inactive Applications Cell Phones, Smart Phones, PDAs Tablet, Portable Media Players Gaming Device, Digital Cameras To facilitate fast system startup, the IC includes a power path circuit, which disconnects the battery from the system rail, ensuring that the system can power up quickly following a VBUS connection. The power path circuit ensures that the system rail stays up when the charger is plugged in, even if the battery is dead. The charging parameters and operating modes are 2 programmable through an I C Interface that operates up to 3.4 Mbps. The charger and boost regulator circuits switch at 3 MHz to minimize the size of external passive components. The FAN54063 provides battery charging in three phases: conditioning, constant current and constant voltage. The IC automatically restarts the charge cycle when the battery falls below a voltage threshold. If the input source is removed, the IC enters a high-impedance mode blocking battery current from leaking to the input. Charger status is reported back to 2 the host through the I C port. Dynamic input voltage control prevents a weak adapters voltage from collapsing, ensuring charging capability from such adapters. The FAN54063 is available in a space saving 2.4 mm x 2.0 mm WLCSP package. VBUS SYS (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 CSYS PGND PMID GATE CMID FAN54063 POK_B SDA SCL Q5 STAT Figure 1. SYSTEM LOAD External PMOS VBAT CBAT NTC REF RREF DIS AGND All trademarks are the property of their respective owners. L1 SW CBUS BATTERY CREF + T Typical Application www.fairchildsemi.com FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint July 2015 Part Number Temperature Range Package FAN54063UCX -40 to 85C 25-Bump, Wafer-Level Chip-Scale Package (WLCSP), 0.4 mm Pitch Table 1. PN Bits: FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Ordering Information Packing Method IC_INFO[5:3] 010 Tape and Reel Feature Summary Part Number Slave Address Automatic Charge Battery Absent Behavior E1 Pin Watchdog Timer Default FAN54063 1101011 No On POK_B Disabled Block Diagram VBUS PMID Q3 CBUS PGND Q1 Q1B IBUS & VBUS CONTROL AGND CMID Q1A CHARGE PUMP L1 SW 30mA PWM MODULATOR CSYS Q2 SYS VBUS OVP POWER OK SYSTEM LOAD PGND Q5 GATE CC and CV Battery Charger POK_B SDA Q4A Q4B I2C INTERFACE VBAT LOGIC AND CONTROL NTC SCL DIS External PMOS Q4 TEMP SENSE STAT REF CBAT RREF BATTERY CREF + T Q1A Q1B Q4A Q4B Greater than VBAT PMID ON OFF Greater than VBAT ON OFF Less than VBAT OFF ON Less than VBAT OFF ON Figure 2. Table 2. SYS IC and System Block Diagram Recommended External Components Component Vendor Parameter Typ. 1 H, 20%, 4.0 A, 2016 Semco CIGT201610EH1R0M or Equivalent L 1.0 DCR (Series R) 33 CBAT, CSYS 10 F, 20%, 6.3 V, X5R, 0603 Murata: GRM188R60J106M TDK: C1608X5R0J106M C 10 CMID 4.7 F, 10%, 10 V , X5R, 0603 Murata: GRM188R61A475K TDK: C1608X5R1A475K C 4.7 CBUS 1.0 F, 10%, 25 V, X5R, 0603 Murata GRM188R61E105K TDK:C1608X5R1E105M C 1.0 Q5 PMOS,12 V, 16 m, MLP2x2 Fairchild FDMA905P RDS(ON) 16 CREF 1.0 F, 10%, 6.3 V, X5R, 0402 C 1.0 L1 Description (1) Note: 1. 10 V rating is sufficient for CMID since PMID is protected from over-voltage surges on VBUS by Q3. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Unit H m F F F m F www.fairchildsemi.com 2 SDA PGND SW A1 A2 A3 PMID VBUS A4 A5 B2 B3 B4 B5 C2 C3 C4 C5 SYS VBAT NTC D3 D4 D5 E3 E4 A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 D2 D1 E5 E4 E3 E2 E1 SCL B1 DIS C1 GATE STAT D1 D2 POK_B AGND E1 E2 REF Figure 3. E5 Top View Figure 4. Bottom View Pin Definitions Pin # Name Description 2 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Pin Configuration A1 SDA I C Interface Serial Data. This pin should not be left floating. B1 SCL I C Interface Serial Clock. This pin should not be left floating. C1 DIS Disable. If this pin is held HIGH, Q1 and Q3 are turned off; creating a HIGH Z condition at VBUS and the PWM converter is disabled. D1 STAT E1 POK_B Power OK. Open-drain output that pulls LOW when VBUS is plugged in and the battery has risen above VLOWV. This signal is used to signal the host processor that it can begin to draw significant current. A2 - D2 PGND Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of CMID should be as short as possible. E2 AGND Analog Ground. All IC signals are referenced to this node. A3 - C3 SW Switching Node. Connect to output inductor. D3 - E3 SYS System Supply. Output voltage of the switching charger and input to the power path controller. Bypass SYS to PGND with a 10 F capacitor. A4 - C4 PMID Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense. Bypass with a minimum of a 4.7 F, 6.3 V capacitor to PGND. D4 - E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor to PGND. VBAT is a power path connection. A5 - B5 VBUS Charger Input Voltage and USB-OTG Output Voltage. Bypass with a 1 F capacitor to PGND. C5 GATE External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS and the drain should be connected to VBAT. D5 NTC Thermistor Input. The IC compares this node with taps on a resistor divider from REF to inhibit autocharging when the battery temperature is outside of permitted fast-charge limits. E5 REF Reference Voltage. REF is a 1.8 V regulated output. 2 Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in progress; can be used to signal the host processor when a fault condition occurs. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 3 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VBUS Parameter Voltage on VBUS Pin Min. Continuous -0.3 Pulsed, 100 ms Maximum Non-Repetitive -1.0 VI Voltage on PMID, SW, SYS, VBAT, STAT, DIS Pins -0.3 VO Voltage on Other Pins -0.3 dVBUS dt Max. 28.0 7.0 6.5 Maximum VBUS Slope Above 5.5 V when Boost or Charger Active Electrostatic Discharge Protection Level ESD (3) IEC 61000-4-2 System ESD (2) 4 Human Body Model per JESD22-A114 2000 Charged Device Model per JESD22-C101 500 Air Gap USB Connector Pins (VBUS to GND) Contact 15 V V V kV 8 Junction Temperature -40 +150 TSTG Storage Temperature -65 +150 Lead Soldering Temperature, 10 Seconds V V/s TJ TL Unit +260 Notes: 2. Lesser of 6.5 V or VI + 0.3 V. 3. Guaranteed if CBUS 1 F and CMID 4.7 F. Recommended Operating Conditions C C C The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VBUS VBAT(MAX) dVBUS dt Parameter Supply Voltage Min. Max. 4 6 Maximum Battery Voltage when Boost enabled V 4.5 Negative VBUS Slew Rate during VBUS Short Circuit, CMID < 4.7 F TA < 60C 4 TA > 60C 2 Unit V V/s TA Ambient Temperature -30 +85 TJ Junction Temperature (see Thermal Regulation and Shutdown) -30 +120 Thermal Properties C C Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(MAX) at a given ambient temperature TA. Symbol Parameter Typical JA Junction-to-Ambient Thermal Resistance 50 JB Junction-to-PCB Thermal Resistance 20 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Unit C/W C/W www.fairchildsemi.com 4 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE = "0"; OPA_MODE = "0" (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for TJ = 25C. Min. and Max. values are not tested in production, but are determined by characterization. Symbol Parameter Conditions Min. Typ. Max. Unit Power Supplies IVBUS VBUS Current PWM Switching 20 VBAT > VOREG IBUSLIM = 500 mA 6 0C < TJ < 85C, DIS pin HIGH or HZ_MODE = "1", VBAT > VLOWV IBAT_HZ Battery Discharge Current in High-Impedance Mode DIS pin HIGH, or HZ_MODE = "1", VBAT = 4.35 V IBUS_HZ Battery Leakage Current to VBUS in High-Impedance Mode DIS pin HIGH or HZ_MODE = "1", VBAT = 4.35 V, VBUS Shorted to Ground -5.0 mA mA 190 280 <1.25 10.00 VOREG Charge Voltage Accuracy 3.51 4.45 V -0.5 +0.5 % -1 +1 % IO_LEVEL = "0" 550 1550 mA IO_LEVEL = "1" (default) 165 230 mA TA = 25C, VOREG = 4.35 V TJ = 0 to 125C Charging Current Regulation (Fast Charge) IOCHARGE Output Charge Current Range VLOWV < VBAT < VOREG Charge Current Accuracy IO_LEVEL = "0" 200 -5 +5 Weak Battery Threshold Range 3.4 3.7 Weak Battery Threshold Accuracy -5 +5 Weak Battery Detection VLOWV Weak Battery Deglitch Time 32 Rising PWM Charging Threshold VBATFALL Falling PWM Charging Threshold 3.1 3.2 3.3 3.0 High-Level Input Voltage VIL Low-Level Input Voltage IIN Input Bias Current Input Tied to GND or VBUS 0.01 DIS Pull-Down Resistance VDIS = 0.4 V 300 RPD 1.05 1.00 Termination Current Accuracy 50 400 ITERM Setting < 100 mA -15 +15 ITERM Setting > 200 mA -5 +5 Termination Current Deglitch (4) Time (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 V 32 V A k Charge Termination Detection ITERM % V 0.4 Termination Current Range V V Logic Levels: DIS, SDA, SCL VIH % ms PWM Charging Threshold VBATMIN A A -0.2 Charger Voltage Regulation Charge Voltage Range A mA % ms www.fairchildsemi.com 5 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications (Continued) Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE = "0"; OPA_MODE = "0" (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for TJ = 25C. Min. and Max. values are not tested in production, but are determined by characterization. Symbol Parameter Conditions Min. Typ. Max. Unit IO_LEVEL = "1" (default) 165 200 235 mA IO_LEVEL = "0", IBUSLIM < "01" 165 200 235 mA IO_LEVEL = "0", IBUSLIM >"01", IOCHARGE < "02" 375 450 520 mA IO_LEVEL = "0", IBUSLIM >"01", IOCHARGE > "02" 610 730 840 mA -6 -5 -3 mV -1 1 2 Power Path (Q4) Control (Precharge) Power Path Maximum Charge Current IPP VBAT to SYS Threshold (SYS - VBAT) Falling for Q4 and Gate Transition (SYS - VBAT) Rising While Charging VTHSYS Production Test Mode (4) Production Test Output Voltage 1 mA < IBAT < 2 A, VBUS = 5.5 V (4) Production Test Output Current 20% Duty with Max. Period 10 ms VBAT(PTM) IBAT(PTM) 4.116 4.200 4.284 2.3 T1 T1 (0C) Temperature Threshold 71.9 73.9 75.9 T2 T2 (10C) Temperature Threshold 62.6 64.6 66.6 T3 T3 (45C) Temperature Threshold 31.9 32.9 34.9 T4 T4 (60C) Temperature Threshold 21.3 23.3 25.3 Input Power Source Detection VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation 4.35 4.45 VIN(MIN)2 Minimum VBUS during Charge 3.71 3.94 tVBUS_VALID (4) VBUS Validation Time 32 VBUS Loop Setpoint Accuracy -3 +3 Input Current Limit IBUSLIM = "00" IBUSLIM Charger Input Current Limit Threshold 450 IBUSLIM = "01" 475 972 Bias Regulator Voltage Short-Circuit Current Limit 1080 V 2.5 mA Battery Recharge Threshold VRCH Recharge Threshold VBAT Below VOREG 100 Deglitch Time VBAT Falling Below VRCH Threshold 120 % 1188 1.8 Charge Mode V mA VREF Bias Generator VREF V 500 760 IBUSLIM = "10" % of VREF ms VBUS Control Loop VBUSLIM V A Battery Temperature Monitor (NTC) During Charging mV 150 130 mV ms STAT, POK_B Outputs V(OL) Output Low ISINK = 10 mA 0.4 V I(OH) Output High Leakage Current VOUTPUT = 5 V 1 A (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 6 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications (Continued) Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE = "0"; OPA_MODE = "0" (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for TJ = 25C. Min. and Max. values are not tested in production, but are determined by characterization. Symbol Parameter Conditions Min. Typ. Battery Detection IDETECT Battery Detection Current before (5) Charge Done (Sink Current) tDETECT Battery Detection Time -1.9 Begins after Termination Detected and VBAT < VOREG - VRCH mA 262 ms Sleep Comparator VSLP Sleep-Mode Entry Threshold, VBUS - VBAT VIN(MIN)2 < VBAT < VOREG, VBUS Falling 0 0.04 0.10 Power Switches (see Figure 2) Q3 On Resistance (VBUS to PMID) RDS(ON) ISYNC IBUSLIM = 500 mA 180 340 Q1 On Resistance (PMID to SW) 130 225 Q2 On Resistance (SW to GND) 150 225 100 Q4 On Resistance (SYS to VBAT) VBAT = 4.35 V 70 Synchronous to Non-Synchronous (6) Current Cut-Off Threshold Low-Side MOSFET (Q2) Cycle-by-Cycle Current Limit 180 fSW Oscillator Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle 2.7 3.0 0 IBAT(BOOST) Boost Mode Quiescent Current ILIMPK(BST) Q2 Peak Current Limit UVLOBST Minimum Battery Voltage for Boost Operation ILIMPK(CHG) VSHORT ISHORT 3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA 4.77 5.07 5.20 250 350 A 1800 2100 mA V PFM Mode, VBAT = 3.6 V, ILOAD = 0 A While Boost Active 2.32 To Start Boost Regulator 2.48 Normal Operation 500 VBUS Validation 100 TSHUTDWN VBUS Rising Hysteresis VBUS Falling Q1 Cycle-by-Cycle Peak Current Limit Charge Mode Battery Short-Circuit Threshold VBAT Rising Hysteresis Thermal Shutdown Threshold Hysteresis 6.09 6.29 100 3 1.95 2.00 100 (4) (4) TCF Thermal Regulation Threshold tINT Detection Interval (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 (4) % 5.20 VBUS Over-Voltage Shutdown Linear Charging Current MHz 5.07 Protection and Timers VBUSOVP 3.3 100 4.80 1550 VBUS to PGND Resistance m 2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA VBUS Load Resistance RVBUS m % Boost Mode Operation (OPA_MODE = 1) Boost Output Voltage at VBUS V mA Charger PWM Modulator VBOOST Max. Unit VBAT < VSHORT 30 TJ Rising 145 TJ Falling 25 Charge Current Reduction Begins 120 2 2.70 V k 6.49 V mV A 2.07 V mV mA C C s www.fairchildsemi.com 7 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications (Continued) Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for TJ = 25C. Min. and Max. values are not tested in production, but are determined by characterization. Symbol Parameter (7) t32S 32-Second Timer tLF Low-Frequency Timer Accuracy Conditions Min. Typ. Max. Unit Charger Enabled 20.5 25.2 28.0 Charger Disabled 18.0 25.2 34.0 Charger Inactive -23 Notes: 4. Guaranteed by design; not tested in production. 5. Negative current is current flowing from the battery to ground (discharging the battery). 6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC. 7. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 27 s % www.fairchildsemi.com 8 Guaranteed by design. Symbol Parameter Conditions Min. Typ. Standard Mode fSCL SCL Clock Frequency 100 Fast Mode 400 Fast Mode Plus 1000 High-Speed Mode, CB < 100 pF 3400 High-Speed Mode, CB < 400 pF tBUF BUS-free Time between STOP and START Conditions 1700 Standard Mode 4.7 Fast Mode 1.3 Fast Mode Plus 0.5 Standard Mode tHD;STA tLOW START or Repeated START Hold Time SCL LOW Period 600 Fast Mode Plus 260 High-Speed Mode 160 Standard Mode 4.7 Fast Mode 1.3 Fast Mode Plus 0.5 High-Speed Mode, CB < 100 pF 160 High-Speed Mode, CB < 400 pF 320 tSU;STA tSU;DAT SCL HIGH Period Repeated START Setup Time Data Setup Time 600 Fast Mode Plus 260 High-Speed Mode, CB < 100 pF 60 High-Speed Mode, CB < 400 pF 120 Standard Mode 4.7 Fast Mode 600 Fast Mode Plus 260 High-Speed Mode 160 Standard Mode 250 Fast Mode 100 Fast Mode Plus 50 High-Speed Mode tHD;DAT tRCL Data Hold Time SCL Rise Time (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 kHz s ns ns ns s s s ns ns s 4 Fast Mode Unit s 4 Fast Mode Standard Mode tHIGH Max. FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support I2C Timing Specifications ns ns ns ns s ns ns ns ns 10 Standard Mode 0 3.45 Fast Mode 0 900 Fast Mode Plus 0 450 High-Speed Mode, CB < 100 pF 0 70 High-Speed Mode, CB < 400 pF 0 150 Standard Mode 20 + 0.1CB 1000 Fast Mode 20 + 0.1CB 300 Fast Mode Plus 20 + 0.1CB 120 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 s ns ns ns ns ns www.fairchildsemi.com 9 Guaranteed by design. Symbol tFCL tRCL1 tRDA Parameter SCL Fall Time Rise Time of SCL after a Repeated START Condition and after ACK Bit SDA Rise Time Conditions tSU;STO CB Stop Condition Setup Time 300 Fast Mode 20 + 0.1CB 300 Fast Mode Plus 20 + 0.1CB 120 High-Speed Mode, CB < 100 pF 10 40 High-Speed Mode, CB < 400 pF 20 80 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 20 + 0.1CB 1000 Fast Mode 20 + 0.1CB 300 Fast Mode Plus 20 + 0.1CB 120 10 80 20 160 Standard Mode 20 + 0.1CB 300 Fast Mode 20 + 0.1CB 300 Fast Mode Plus 20 + 0.1CB 120 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 4 Fast Mode 600 Fast Mode Plus 120 High-Speed Mode 160 Capacitive Load for SDA and SCL (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Max. 20 + 0.1CB High-Speed Mode, CB < 400 pF SDA Fall Time Typ. Standard Mode High-Speed Mode, CB < 100 pF tFDA Min. FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support I2C Timing Specifications (Continued) Unit ns ns ns ns s ns ns ns 400 pF www.fairchildsemi.com 10 tF tSU;STA tBUF SDA tR TSU;DAT tHD;STO tHIGH SCL tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START tFDA STOP 2 Figure 5. I C Interface Timing for Fast and Slow Modes tRDA REPEATED START tSU;DAT SDAH tSU;STA tRCL1 tFCL tRCL tSU;STO tHIGH SCLH tLOW tHD;STA REPEATED START tHD;DAT note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. Figure 6. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 2 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Timing Diagrams I C Interface Timing for High-Speed Mode STOP START www.fairchildsemi.com 11 800 1,700 700 1,500 Battery Charge Current (mA) Battery Charge Current (mA) Unless otherwise specified, circuit of Figure 1, VOREG = 4.35 V, IOCHARGE = 950 mA, VBUS = 5.0 V, and TA = 25C. 600 500 400 300 4.7 VBUS 200 1,300 1,100 900 700 4.7 VBUS 500 5.0 VBUS 5.0 VBUS 5.5 VBUS 5.5 VBUS 100 300 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 2.7 2.9 3.1 Battery Voltage VBAT (V) 3.3 3.5 3.7 3.9 4.1 Battery Voltage VBAT (V) Battery Charge Current vs. VBUS with IBUSLIM = 500 mA Figure 8. 95 94 90 92 85 90 Efficiency (%) Efficiency (%) Figure 7. 80 75 88 86 5.0VBUS, 3.9VBAT 84 5.0 VBUS 5.0VBUS, 4.3VBAT 5.5 VBUS 5.5VBUS, 4.3VBAT 65 82 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 550 750 Battery Voltage VBAT (V) 950 1150 1350 Battery Charge Current IBAT (mA) Efficiency vs. VBUS, IBUSLIM = 500 mA, ISYS = 0 Figure 10. 1,000 2.00 800 1.80 VREF Output Voltage (V) High-Z Mode Input Current (A) Figure 9. 600 400 -30C 200 1.40 1.20 -30C +25C +85C +85C 0 1.00 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 0 VBUS Input Voltage (V) Figure 11. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 1 2 3 VREF Load Current (mA) HZ Mode VBUS Current vs. Temperature, 3.7 VBAT Figure 12. 4.5 1550 Efficiency vs. Charging Current, IBUSLIM = No Limit 1.60 +25C 4.3 Battery Charge Current vs. VBUS with IBUSLIM = 1100 mA 4.7VBUS, 3.9VBAT 4.7 VBUS 70 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics 4 5 VREF vs. Load Current, Over-Temperature www.fairchildsemi.com 12 Unless otherwise specified, circuit of Figure 1, VOREG = 4.35 V, IOCHARGE = 950 mA, VBUS = 5.0 V, and TA = 25C. Figure 13. Charger Startup at VBUS Plug-In, 500 mA IBUSLIM, 3.1 VBAT, 50 SYS Load, CE# = 0, IO_LEVEL = 1 Figure 14. Charger Startup at VBUS Plug-In, 1100 mA IBUSLIM, 3.6 VBAT, 700 mA SYS Load, CE# = 0, IO_LEVEL = 0 Figure 15. Charger Startup at VBUS Plug-In Using 300 mA Current Limited Source, 500 mA IBUSLIM, 3.1 VBAT, 200 mA SYS Load, CE# = 0, IO_LEVEL = 0 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics Figure 16. Charger Startup with HZ Bit Reset, 500 mA IBUSLIM, 950 mA IOCHARGE, 50 SYS Load, CE# = 0 www.fairchildsemi.com 13 Unless otherwise specified, circuit of Figure 1, VOREG = 4.35 V, IOCHARGE = 950 mA, VBUS = 5.0 V, and TA = 25C. Figure 17. Battery Removal / Insertion while Charging, TE = 0, 3.9 VBAT, IOCHARGE = 950 mA, IBUSLIM = No Limit, 50 SYS Load Figure 18. Battery Removal / Insertion when Charging, TE = 1, 3.9 VBAT, IBUSLIM = No Limit, 50 SYS Load Figure 19. Charger Enable (CE# = 1 to 0) with VBUS Applied, IBUSLIM = 500 mA, 200 mA SYS Load, IO_LEVEL = 0 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics Figure 20. No Battery at VBUS Power-Up, 100 SYS Load, 1 k VBAT Load www.fairchildsemi.com 14 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support GSM Typical Characteristics A 2.0 A GSM pulse applied at VBAT with 5 s rise / fall time. Simultaneous to GSM pulse, 50 additional load applied at SYS. Figure 21. 2.0 A GSM Pulse Response, IBUSLIM = 500 mA Control, IOCHARGE 950 mA, 3.7 VBAT, VOREG = 4.35 V (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Figure 22. 2.0 A GSM Pulse Response, IBUSLIM = 500 mA, IOCHARGE = 950 mA, 3.7 VBAT, VOREG = 4.35 V, 200 mA Source Current Limit www.fairchildsemi.com 15 100 100 95 95 90 90 Efficiency (%) Efficiency (%) Unless otherwise specified, using circuit of Figure 1, VBAT = 3.6 V, TA = 25C. 85 85 -10C, 3.6VBAT 80 2.7VBAT 80 +25C, 3.6VBAT 3.6VBAT +85C, 3.6VBAT 4.2VBAT 75 75 0 100 200 300 400 0 500 100 200 300 400 VBUS Load Current (mA) VBUS Load Current (mA) Figure 23. Efficiency vs. IBUS Over VBAT Figure 24. 5.15 30 3.6VBAT Output Voltage VBUS (V) 25 4.2VBAT 20 VBUS Ripple (mVpp) 5.05 5.00 4.95 500 Efficiency vs. IBUS Over-Temperature, 3.6 VBAT 2.7VBAT 5.10 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Mode Typical Characteristics 15 10 2.7VBAT 4.90 5 3.6VBAT 4.2VBAT 4.85 0 0 100 200 300 400 500 0 100 VBUS Load Current (mA) Figure 25. 200 300 400 VBUS Load Current (mA) Regulation vs. IBUS Over VBAT Figure 26. Output Ripple vs. IBUS Over VBAT 10 350 +25C +85C HZ Mode Battery Current (A) OTG/Boost Quiescent Current (A) -30C 300 250 200 150 500 8 6 4 -30C 2 +25C +85C 100 0 2 2.5 3 3.5 4 4.5 5 2 Battery Voltage, VBAT (V) Figure 27. 3 3.5 Battery Voltage, VBAT (V) Quiescent Current (IQ) vs. VBAT OverTemperature (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 2.5 Figure 28. 4 4.5 5 Battery Discharge Current vs. VBAT, HZ / Sleep Mode www.fairchildsemi.com 16 Unless otherwise specified, using circuit of Figure 1, VBAT = 3.6 V, TA = 25C. Figure 29. OTG Startup, 50 Load, 3.6 VBAT External / Additional 10 F on VBUS Figure 31. Figure 30. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 OTG VBUS Overload Response Figure 32. Line Transient, 50 Load, 3.9-3.3-3.9 VBAT, tRISE/FALL = 10 s Load Transient, 20-200-20 mA IBUS, tRISE/FALL = 100 ns FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Mode Typical Characteristics www.fairchildsemi.com 17 When charging batteries with a current-limited input source, such as USB, a switching chargers high efficiency over a wide range of output voltages minimizes charging time. PWM Controller in Charge Mode The IC uses a current-mode PWM controller to regulate the output voltage and battery charge currents. The synchronous rectifier (Q2) has a negative current limit that turns off Q2 at 180 mA to prevent current flow from the battery. FAN54063 combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5 V to USB On-The-Go (OTG) peripherals. The FAN54063 employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. Battery Charging Curve If the battery voltage is below VSHORT, a linear current source pre-charges the battery until VBAT reaches VSHORT. The PWM charging circuit is then started and the battery is charged with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. The FAN54063 has four operating modes: 2. Boost Mode: Provides 5 V power to USB-OTG with an integrated synchronous rectification boost regulator, using the battery as input. 3. High-Impedance Mode: Both the boost and charging circuits are OFF in this mode. Current flow from VBUS to the battery or from the battery to VBUS is blocked in this mode. This mode consumes very little current from VBUS or the battery. 4. Production Test Mode: This mode provides 4.2 V output on VBAT and supplies a load current of up to 2.3 A. During the current regulation phase of charging, IBUSLIM or the programmed charging current limits the amount of current available to charge the battery and power the system. During the voltage regulation phase of charging, assuming that VOREG is programmed to the cells fully charged "float" voltage, the current that the battery accepts with the PWM regulator limiting its output (sensed at VBAT) to V OREG declines. IPP VBATMIN Charge Mode VSHORT In Charge Mode, FAN54063 employs six regulation loops: ISHORT 2. 3. 4. 5. 6. Input Current: Limits the amount of current drawn from VBUS. This current is sensed internally and can be 2 programmed through the I C interface. ITERM ISHORT CONSTANT CONSTANT PRECHARGE CHARGE CURRENT (CC) VOLTAGE (CV) RECHARGE IOCHARGE Current Charging Charging Current: Limits the maximum charging current. This current is sensed using an internal sense MOSFET. Figure 33. VBUS Voltage: This loop is designed to prevent the input supply from being dragged below VBUSLIM (typically 4.5 V) when the input power source is current limited. An example of this would be a travel charger. This loop cuts back the current when VBUS approaches VBUSLIM, allowing the input source to run in current limit. Charge Curve, IOCHARGE Not Limited by IBUSLIM The FAN54063 is designed to work with a current-limited input source at VBUS as shown below: VBAT VFLOAT IOCHARGE Charge Voltage: The regulator is restricted from exceeding this voltage. As the internal battery voltage rises, the batterys internal impedance works in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery. Battery charging is completed when the current through Q4 drops below the ITERM threshold. IB IPP AT VBATMIN ITERM VSHORT ISHORT Pre-charge: When VBAT is below VBATMIN, Q4 operates as a linear current source and modulates its current to ensure that the voltage on SYS stays above 3.4 V. ISHORT CONSTANT CONSTANT PRECHARGE CHARGE CURRENT (CC) VOLTAGE (CV) Input Current Limited Charging Temperature: If the ICs junction temperature reaches 120C, charge current is reduced until the ICs temperature is below 120C. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 IBAT IOCHARGE Charge Mode and Registers 1. VBAT VFLOAT BATTERY VOLTAGE DECAY Charge Mode: Charges a single-cell Li-ion or Li-polymer battery. BATTERY VOLTAGE DECAY 1. FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Circuit Description / Overview Figure 34. RECHARGE Charge Curve, IBUSLIM Limits IOCHARGE www.fairchildsemi.com 18 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support The following charging parameters can be programmed by 2 the host through I C: VBAT falls to VRCH below VOREG, the Fast Charge cycle starts again. Table 3. Programmable Charging Parameters See ITERM Register Bit Definitions Parameter Weak Battery Voltage (VLOWV) Output Voltage Regulation Battery Charging Current Limit Name Register VOREG REG02[7:2] IOCHARGE REG04[6:3] Input Current Limit IBUSLIM REG01[7:6] Charge Termination Limit ITERM REG04[2:0] Weak Battery Voltage VLOWV REG01[5:4] The FAN54063 monitors the level of the battery with respect to a programmable VLOWV threshold set by VLOWV (REG01[5:4]) and the default is 3.7V. VLOWV defines the voltage level of the battery at which the system is guaranteed to be fully operational when only powered by the battery. The POK_B pin pulls LOW once VBAT reaches VLOWV, and remains LOW as long as the IC is in Fast Charge. The IC will remain in Fast Charge as long as VBAT > 3.0 V. Output Voltage Regulation (VOREG) See VLOWV Register Bit Definitions The charger output or "float" voltage can be programmed by the OREG (REG02[7:2]) bits from 3.51 V to 4.45 V in 20 mV increments. The default setting is 3.55 V. VBUS Control loop (VBUSLIM) The IC includes a control loop that limits input current in case a current-limited source is supplying VBUS. See OREG Register Bit Definitions Battery Charging Current Limit (IOCHARGE) The control increases the charging current until either: When the IO_LEVEL bit is set (default), the IOCHARGE bits are ignored and charge current is set to 200 mA. IBUSLIM or IOCHARGE limit is reached VBUS = VBUSLIM. OR If VBUS collapses to VBUSLIM, set by VBUSLIM bits (REG05[2:0]), the VBUS loop reduces its current to keep VBUS = VBUSLIM. When the VBUS control loop is limiting the charge current, the VLIM bit (REG05[3]) is set. See IOCHARGE Register Bit Definitions Input Current Limiting (IBUSLIM) To minimize charging time without overloading VBUS current limitations, the ICs input current limit can be programmed by the IBUSLIM (REG01[7:6]) bits. See VBUSLIM Register Bit Definitions See IBUSLIM Register Bit Definitions Charger Operation Termination Limit (ITERM) VBUS Plug In and Safety Timer Charge current termination can be enabled or disabled using the TE (REG01[3]) bit. By default TE = "0", therefore, termination is disabled and charging does not terminate at the programmed ITERM level. At VBUS plug in, the TMR_RST (Reg00[7]) bit must be set within 2 seconds of VBUS rising above V(INMIN)1 or all registers, except for SAFETY (REG06), are set to their default values. This functionality occurs regardless of the state of the CE# and WD_DIS bit. If plug in occurs with the device in a HZ or Charge Done state and the TMR_RST bit is not set within 2 seconds of VBUS rising above V(INMIN)1, all register, except for SAFETY, will reset when the device enters PWM Charging or Recharge. When TE = "1", and VBAT reaches VOREG, the charging current is reduced, limited by the batterys ESR and its internal cell voltage. When the charge current falls below ITERM; PWM charging stops; but the STAT pin remains LOW. The STAT pin then goes HIGH and the STAT bits change to CHARGE DONE (10), provided the battery and charger are still connected. If VBAT falls to VRCH below VOREG, the Fast Charge cycle starts again. By default, the safety timers do not run in the FAN54063. A Watchdog (t32S) timer can be enabled by setting the WD_DIS register bit, (REG13[1]) to "0". When WD_DIS = "0", charging is controlled by the host with the t32S timer running to ensure that the host is alive. Setting the TMR_RST bit resets the t 32S timer. If the t32S timer times out; all registers, except SAFETY, are set to their default values (including WD_DIS and CE#), the FAULT bits are set to "110", and STAT is pulsed. Post-charging can be enabled to "top-off" the battery to a lower termination current threshold than ITERM. The PC_EN bit (REG07[3]) must be set to "1" before the battery charging current reaches ITERM. The lower termination current is set by the PC_IT (REG07[2:0] bits. Post-charging begins after normal charging is ended (as described above) with the PC_ON (REG11[2]) monitor bit set to "1". During post-charging, the STAT pin is HIGH, indicating that the charge current is below the ITERM level. Once the current reaches the threshold for post-charging completion (set by the PC_IT bits), PWM charging stops and the PC_ON bit changes back to "0". If the charging current goes above ITERM without first falling to PC_IT, the PC_ON bit can be reset by using any of these methods: VBAT moving below and above VBATMIN, a VBUS POR, or the CE# or HZ_MODE bit cycled. If (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 19 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support VBUS POR / Non-Compliant Charger Rejection Power Path Operation 256 ms after VBUS is connected, the IC pulses the STAT pin and sets the VBUS_CON bit. Before starting to supply current, the IC applies a 100 load from VBUS to GND. VBUS must remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID (32 ms) before the IC initiates charging or supplies power to SYS. As long as VBAT < VBATMIN, Q4 operates as a linear current source, (Precharge) with its current (IPP) limited to 200 mA when IO_LEVEL (REG05[5]) is set to its default value of "1". If IO_LEVEL is set to "0" and IBUSLIM > "01", charge current is limited to 450 mA when IOCHARGE 750 mA, and 730 mA when IOCHARGE > 750 mA. Providing the input current is not limited by the IBUSLIM setting or the current available from the source, during precharge, the IC regulates SYS to 3.55 V and provides the IPP limited current to the battery. The VBUS validation sequence always occurs before significant current is drawn from VBUS (for example, after a VBUS OVP fault or a recharge initiation. tVBUS_VALID ensures that unfiltered 50/60 Hz chargers and other non-compliant chargers are rejected. System power always has the highest priority when power from the buck is limited ensuring SYS does not fall below 3.4 V. This is managed by folding back the current to charge the battery until charge current is reduced to 0 A. USB-Friendly Boot Sequence The FAN54063 does not automatically initiate charging at VBUS POR. Instead, prior to receiving host commands, the buck is enabled to provide power to SYS while Q4 and Q5 remain off until register bit CE# (REG01[2]) is set to "0" 2 through the I C interface, allowing charging through Q4. After VBAT reaches VBATMIN, Q4 closes and is used as a 2 current-sense element to limit current (IOCHARGE) per the I C register settings. This is accomplished by limiting the PWM modulators current (Fast Charge). If SYS drops more than 5 mV (VTHSYS) below VBAT and CE# = "0", Q4 and Q5 are turned on (GATE is pulled LOW). If CE# = "1", only Q5 is turned on. Once SYS voltage becomes higher than VBAT, Q5 is turned off and Q4 again serves as the current-sense element to limit IOCHARGE. Startup with No Battery The FAN54063 has Battery Absent Behavior enabled. At VBUS POR with the battery absent, the PWM will run, providing 3.55 V to the system from the input source with current limited by the default IBUSLIM setting. If the DIS pin is HIGH or HZ_MODE = "1" while VBAT > VLOWV, Q4 and Q5 are enabled to prevent the system from crashing. Q4 and Q5 are also both turned on when the IC enters SLEEP Mode (VBUS < VBAT). Startup with a Dead Battery At VBUS POR, if VBAT < VSHORT, all registers, including the SAFETY register, are reset to their default values and the DBAT_B (REG02[1]) bit is reset. CE# = "1", so charging is disabled. POK_B (see Table 4) The POK_B pin and the POK_B (REG11[5]) bit are intended to provide feedback to the processor that the battery is strong enough to allow the device to fully function. Whenever the IC is operating in precharge, POK_B is HIGH. On exiting Precharge, POK_B remains HIGH until VBAT > VLOWV. REG01[5:4] sets the VLOWV threshold. POK_B pulls LOW once VBAT reaches VLOWV, and remains LOW as long as the IC is in Fast Charge and the IC will remain in Fast Charge as long as VBAT > 3.0 V. If the battery voltage falls below 3.0 V the IC enters Precharge. If WD_DIS = "0" and the t32S timer expires during charging, the POK_B pin will go HIGH. If the batterys protection switch is open, the PWM will run, providing 3.55 V to the system from the input source with current limited by the default IBUSLIM setting. This allows the host processor to awaken and establish host control. Once this occurs, the hosts low level software can program the CE# bit to "0" and a linear current source closes the battery protection switch. When VBAT voltage rises above VBATMIN and sufficient power is available, PWM charging begins and the battery is charged through the BATFET, Q4. The IO_LEVEL (REG05[5]) bit is set to "1" by default which limits charge current to 200 mA. The POK_B bit can be set via I2C to change the state of the pin to HIGH. This setting of the bit and pin can be used to signal the system into a low-power state, preventing excessive loading from the system while attempting to recharge a depleted battery. With CE# = "1" once VBAT rises above VSHORT, DBAT_B is set. With CE# = "0" once VBAT rises above VBATMIN, DBAT_B is set. The STAT pin pulses any time the POK_B pin and bit change states. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 20 Q4, Q5, POK_B vs. Operating Mode Operating Mode VBUS VBAT CE# PWM VSYS Q4 Q5 GATE POK_B < VBAT ON ON LOW HIGH VBUS Disconnected < VBAT OR < VIN(MIN)2 OFF > VSHORT X OFF VBUS Plug in with Battery Protection Switch Open PWM 30 mA Linear Charging (9) Valid OPEN Valid < VSHORT 1 0 0 VOREG OFF OFF HIGH ON 3.55 OFF OFF HIGH HIGH 3.55 Linear OFF HIGH HIGH HIGH Precharge Valid > VSHORT and < VBATMIN 0 ON Precharge: ISYS + Ipp > IPWM, IBAT < IPP Valid < VBATMIN 0 ON < 3.55 Linear OFF HIGH Fast Charge Valid > VBATMIN and < VLOWV 0 ON > VBAT OFF HIGH ON > VLOWV 0 VBATFALL ON 3.55 Valid > VBATMIN and > VSYS + VTHSYS HIGH ON OFF HIGH HIGH X ON LOW X Battery Supplementing SYS Supplemental Mode: ISYS > IPWM (8) Indeterminate LOW Battery Voltage Falling from Fast Charge Valid HIGH ON Charge Mode Precharge FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Table 4. X ON < VBAT Notes: 8. When VBAT is open, VBAT can float to VSYS, and POK_B = HIGH when VBAT < VLOWV and POK_B = LOW when VBAT > VLOWV. Batterys presence or not (VBAT open) can be monitored by reading NOBAT bit (REG11[3]). 9. 30 mA Linear Charging operating mode assumes the host has programmed CE# = "0" during PWM Operating Mode. The state of the MONITOR register bits listed in HighImpedance Mode is valid only when VBUS is valid. Charger Status / Fault Status The STAT pin indicates the operating condition of the IC and provides a fault indicator for interrupt driven systems. Table 5. Charge Mode Control Bits The CE# (REG01[2]) bit is set to "1 by default, therefore, charging is disabled. Setting the RESET (REG04[7]) bit clears all registers (except SAFETY). The CE# bit will only be cleared if RESET occurs with a valid VBUS and VBAT < VLOWV. If the HZ_MODE bit was set when the RESET bit is set, this bit is also cleared. Refer to the Register Bit Definitions section for more details. STAT Pin Function EN_STAT Charge State STAT Pin 0 X OPEN X Normal Conditions OPEN 1 Charging LOW X Fault (Charging or Boost) 128 s Pulse, then OPEN Setting the HZ_MODE bit (REG01[1]) or raising the DIS pin will put the device in High-Impedance Mode, where the buck is disabled. Q4 and Q5 are enabled to prevent the system from crashing. Refer to Table 6 for details. The FAULT bits (REG00[2:0]) indicate the type of fault in Charge Mode. If the charger is in High-Impedance mode and VBAT drops below VLOWV, or High Impedance mode is entered while VBAT < VLOWV, all registers (except SAFETY), including HZ_MODE and CE#, are reset to their default values. If WD_DIS = "0" (REG13[1]), the register resets, including WD_DIS, only occur if the Watch-Dog Timer (t32S) expires. If the DIS pin is HIGH, the IC will remain in High-Impedance Mode. If the DIS pin is LOW, the buck will be enabled. Monitor Registers (REG10, REG11) Additional status monitoring bits enable the host processor to have more visibility into the status of the IC. The monitor bits are real-time status indicators and are not internally debounced or otherwise time qualified. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 21 DIS Pin, HZ_MODE and WD_DIS Bit Operation Conditions Functionality 2 WD_DIS = 1 (default) and VBAT > VLOWV FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Table 6. Setting either the HZ_MODE bit through I C or the DIS pin HIGH will disable the charger and put the IC into High-Impedance Mode. Resetting the HZ_MODE bit or the DIS pin to LOW will allow charging to resume. 2 WD_DIS = 0 and VBAT > VLOWV (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Setting either the HZ_MODE bit through I C or the DIS pin HIGH will stop the t32S timer from advancing (does not reset it), disable the charger, and put the IC into High-Impedance Mode. Resetting the HZ_MODE bit or the DIS pin LOW allows charging to resume. The t32S timer resuming counting down the remainder of time from where it was suspended, at HZ mode entry. www.fairchildsemi.com 22 VBUS POR Note: At VBUS plug in, the TMR_RST (REG00[7]) bit must be set within 2 seconds of VBUS rising above VIN(MIN)1 or all registers, except for SAFETY (REG06), are set to their default values. YES VBAT < VSHORT Enable Linear charging Reset Safety register FIRST NO VBAT < VSHORT TIME? YES NO NO YES Enable PWM YES VBUS OK? YES Battery YES CE# = 1 Enable PWM Present? NO NO NO Enunciate battery absent fault Indicate VBUS Fault YES VBAT < VBATMIN Battery Present? NO Enunciate battery absent fault NO Reset Charge Parameters (see bottom of page) YES Enable Precharge charging NO Enable Fast charging FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Flow Charts Indicate Charge Complete EOC = 1 IOUT < ITERM and TE = 1 NO VBAT < VOREG - VRCH ? YES NO Disable PWM for 2 seconds PWM ON Q4 and Q5 OFF YES YES Note: Reset Charge Parameters is a condition that results in the OREG, IOCHARGE, IBUSLIM, ITERM, VLOWV, and the Safety register bits resetting. It does not reset the IO_LEVEL, EOC, and TE register bits. Figure 35. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Charge State Flow Chart www.fairchildsemi.com 23 Sleep Mode When VBUS falls below VBAT + VSLP and VBUS is above VIN(MIN)2, the IC enters Sleep Mode to prevent the battery from draining into VBUS. During Sleep Mode, reverse current is disabled by body switching Q1. Table 9. Parameter The Idle State is related to the condition of the battery. During Idle mode the Switch Mode Power Supply (SMPS) is operating, but the battery is not being charged for one or more of the following conditions exists: the Safety Timer expires (CE# reset to 1), charging is complete, or the BATFET is disabled by the Charge Enable bit, CE# = "1". The PWM Buck continues to supply power to the system, but the Battery is no longer being charged and the BATFET is disabled. The Standby State is an intermediate state where the switch mode supply is off due to either bad input power, the device has been put in High-Impedance Mode, or the die temperature is too hot. Battery Temperature (NTC) Monitor The FAN54063 reduces the maximum charge current and termination voltage if an NTC measuring battery temperature (TBAT) indicates that it is outside the fast-charging limits (T2 1 to T3), as described in the JEITA specification . There are four temperature thresholds that change battery charger operation: T1, T2, T3, and T4, shown below. 0C 73.9 10 k 47 k 100 k 4250 3380 3940 4050 T1 0C 3C 6 T2 10C 12C 13 T3 45C 42C 41 T4 60C 55C 53 8 14 40 51 Table 10. NTC1-NTC4 Decoding For use with 10 k NTC, = 3380, and RREF = 10 k. T1 10 k The IC first measures the NTC immediately prior to entering any PWM charging state, then measures the NTC once per second, updating the result in NTC1 to NTC4 bits (REG 12[3:0]). Battery Temperature Thresholds % of VREF RTHRM(25C) To disable the thermistor circuit, tie the NTC pin to GND. Before enabling the charger, the IC tests to see if NTC is shorted to GND. If NTC is shorted to GND, no thermistor readings occur and the NTC_OK and NTC1 to NTC4 are reset. Charger Protection Temperature Various Thermistors The host processor can disable temperature-driven control of charging parameters by writing "1" to the TEMP_DIS bit. Since TEMP_DIS is reset whenever the IC resets its registers, the temperature controls are enforced whenever the IC is auto-charging, since auto-charge is always preceded by a reset of registers. Standby State Threshold Thermistor Temperature Thresholds RREF = RTHRM at 25C. Idle State Table 7. FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Thermistors with other values can be used, with some shift in the corresponding temperature threshold, as shown in Table 9. Non-Charging States TBAT (C) NTC4 NTC3 NTC2 Above T4 1 1 1 Between T3 and T4 0 1 1 Between T2 and T3 0 0 1 Between T1 and T2 0 0 0 Below T1 0 0 0 NTC1 1 1 1 1 T2 10C 64.6 T3 45C 32.9 T4 60C 23.3 Safety Register Settings VFLOAT The IC contains a SAFETY register (REG06) that prevents the values of OREG (REG02[7:2]) and IOCHARGE (REG04[6:3]) from exceeding the values of VSAFE (REG06[3:0]) and ISAFE (REG06[7:4]) in the SAFETY register. Table 8. Charge Parameters vs. TBAT TBAT (C) Below T1 ICHARGE Charging to VBAT Disabled Between T1 and T2 IOCHARGE / 2 Between T2 and T3 IOCHARGE Between T3 and T4 IOCHARGE / 2 Above T4 (10) 4.0 V After VBAT rises above VSHORT, the SAFETY register is loaded with its default value and may be written to only before writing to any other register. The same 8-bit value should be written to the SAFETY register twice to set the register value. After writing to any other register, the SAFETY register is locked until VBAT falls below VSHORT. VOREG (10) 4.0 V Charging to VBAT Disabled Note: 10. If IOCHARGE is programmed to less than 650 mA, the charge current is limited to 340 mA. If the host attempts to write a value higher than VSAFE or ISAFE to OREG or IOCHARGE, respectively; the VSAFE, ISAFE value appears as the OREG, IOCHARGE register value, respectively. 1 Japan Electronics and Information Technology Industries Association (JEITA) and Battery Association of Japan. "A Guide to the Safe Use of Secondary Lithium Ion Batteries in Notebook-type Personal Computers," April 28, 2007. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 0 The Safety register is reset when the battery is below VSHORT and power is removed from VBUS. www.fairchildsemi.com 24 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support See VSAFE and ISAFE Register Bit Definitions Charge Mode Battery Detection & Protection Thermal Regulation and Shutdown VBAT Over-Voltage Protection When the ICs junction temperature reaches TCF (about 120C), the charger reduces its output current to 550 mA to prevent overheating. If the temperature increases beyond TSHUTDOWN; charging is suspended, the FAULT bits are set to 101, and STAT is pulsed high. In Suspend Mode, all timers stop and the state of the ICs logic is preserved. Charging resumes at programmed current after the die cools to about 120C. The OREG voltage regulation loop prevents V BAT from overshooting VOREG by more than 50 mV when the battery is removed. When the PWM charger runs with no battery, the TE bit is not set and a battery is inserted that is charged to a voltage higher than VOREG; PWM pulses stop. If no further pulses occur for 30 ms, the IC sets the FAULT bits to "100", sets the STAT bits to "11", and pulses the STAT pin. Note that as power dissipation increases, the effective JA decreases due to the larger difference between the die temperature and ambient. The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set to "1" and CE# = "0". During normal charging, once VBAT is close to VOREG and the charge current falls below ITERM; the PWM charger continues to provide power to SYS and Q4 is turned off. It then turns on a discharge current, IDETECT, for tDETECT. If VBAT is still above VOREG - VRCH, the battery is present and the IC sets the STAT bits to "10" (Charge Done). If VBAT is below VOREG - VRCH, the battery is absent and the IC: Battery Detection during Charging Charge Mode Input Supply Protection Input Supply Low-Voltage Detection The IC continuously monitors VBUS during charging. If VBUS falls below VIN(MIN)2, the IC: 1. Terminates charging 2. Pulses the STAT pin, sets the STAT bits to "00", and sets the FAULT bits to "011". If VBUS recovers above the VIN(MIN)1 rising threshold after time tINT (about two seconds), the charging process is repeated. This function prevents the USB power bus from collapsing or oscillating when the IC is connected to a suspended USB port or a low-current-capable OTG device. Input Over-Voltage Detection When VBUS exceeds VBUSOVP, the IC: 1. Sets the charging parameters to their default values. 2. Sets the FAULT bits to "111" (Battery Absent) and sets the NOBAT bit. 3. If EOC = "0", the IC turns off the PWM for tINT, then resumes charging and retries Battery Detection. If the battery is still absent, the process repeats with the "No Battery" fault re-enunciated. 4. If EOC = "1", the PWM remains on to provide power to SYS, but charge termination and the battery absent test are performed every tINT. 1. Turns off Q3 Linear Charging 2. Suspends charging 3. Sets the FAULT bits to "001", sets the STAT bits to "11", and pulses the STAT pin. If the battery voltage is below the short-circuit threshold (VSHORT); a linear current source, ISHORT, charges VBAT until VBAT > VSHORT. When VBUS falls about 100 mV below VBUSOVP, the fault is cleared and charging resumes after VBUS is revalidated. Production Test Mode (PTM) PTM provides 4.20 V at up to 2.3 A to VBAT when VBUS = 5.5 V 5%. SYS Short During Discharge / Supplemental Mode Caution should be taken to ensure the SYS pin is not shorted when connected to a battery. This condition can induce high current flow through the BATFET (Q4) and the external FET (Q5) until the batterys own safety circuit trips. The resulting high current can damage the IC. The IC enters PTM when the PROD (REG05[6]) bit is set after the NOBAT (REG11[3]) bit has been set. The NOBAT bit indicates that the IC has detected battery absence. A battery absence detection test is performed automatically at current termination. The steps for entering PTM should include: set the TE (REG01[3]) bit high, set the CE# (REG01[2]) bit low, wait for the NOBAT bit to set HIGH, then set the PROD bit to "1" to enter PTM. Battery absence detection is completed within 500 ms from the time that CE# is set. In PTM, the GATE bit (REG11[7]) is LOW, Q5 is on, and all auxiliary control loops are disabled. Only the OREG loop is active, which controls VBAT to 4.20 V, regardless of the OREG register setting. Thermal shutdown remains active. During PTM, high current pulses (load currents greater than 1.5 A) must be limited to 20% duty cycle with a minimum period of 10 ms. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 25 PFM Mode Boost Mode can be enabled by setting the OPA_MODE REG01[0]) bit HIGH and clearing the HZ_MODE bit. If VBUS > VREFBOOST (nominally 5.07 V) when the minimum off-time ends, the regulator enters PFM Mode. Boost pulses are inhibited until VBUS < VREFBOOST. The minimum on-time is increased to enable the output to pump up sufficiently with each PFM boost pulse. Therefore, the regulator behaves like a constant on-time regulator, with the bottom of its output voltage ripple at 5.07 V in PFM Mode. Table 11. Enabling Boost HZ_MODE OPA_MODE BOOST 0 1 Enabled 1 X Disabled X 0 Disabled FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Mode Table 12. Boost PWM Operating States If WD_DIS = "0", to remain in Boost Mode, the TMR_RST must be set by the host before the t32S timer times out. If t32S times out in Boost Mode; the IC resets all registers, pulses the STAT pin, sets the FAULT bits to 110, and resets the BOOST bit. VBUS POR or reading REG00 clears the fault condition. Mode Description Invoked When LIN Linear Startup VBAT > VBUS SS Boost Soft-Start VBUS < VBST BST Boost Operating Mode VBAT > UVLOBST and SS Completed Boost PWM Control Startup The IC uses a minimum on-time and computed minimum offtime to regulate VBUS. The regulator achieves excellent transient response by employing current-mode modulation. This technique causes the regulator to exhibit a load line. The output voltage drops slightly as the output current rises. With a constant VBAT, this appears as a constant output resistance. When the boost regulator is shut down, current flow is prevented from VBAT to VBUS, as well as reverse flow from VBUS to VBAT. LIN State When the boost is enabled by setting OPA_MODE = 1 and HZ_MODE = 0, if VBAT > UVLOBST, the regulator first attempts to bring PMID to within approximately 500 mV of VBAT using an internal 1100 mA limited current source from VBAT. If PMID has not achieved VBAT - 500 mV after 8 ms, a fault state is declared. The "droop" caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. This can be seen in Figure 31 and Figure 36. SS State VBUS Output Resistance (m) 400 Once PMID > VBAT - 500 mV, Q3 begins to close, connecting VBUS to PMID, and the boost regulator begins switching with a reduced peak current limit of 50% of it nominal current limit for up to 128 s. After the 128 s, the peak current limit is increased to 100%. 360 320 If the output fails to achieve 95% of its setpoint within 4 ms, while the peak current limit is 100%, a restart cycle is initiated. Up to 15 restart attempts will be made before a fault is declared. 280 240 Once the voltage reaches 95%, the device begins to increment the voltage in 50 mV steps, every 512 s, until full regulation is achieved. 200 2.0 2.5 3.0 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 36. During the soft start state, the high-side FET (Q1) is operated asynchronously until PMID > VBAT. Output Resistance (ROUT) VBUS as a function of ILOAD can be computed when the regulator is in PWM Mode (continuous conduction) as: VOUT 5.07 ROUT I LOAD BST State This is the normal operating mode of the regulator. The regulator uses a calculated tOFF, modulated tON scheme. The calculated tOFF is proportional to VIN , which keeps the EQ. 1 VOUT At VBAT = 3.0 V and ILOAD = 300 mA, VBUS drops to: VOUT 5.07 0.30 0.3 4.98V regulators switching frequency reasonably constant in CCM. tON(MIN) is proportional to VBAT and is a higher value if the inductor current reached 0 before tOFF(MIN) in the prior cycle. EQ. 2 At VBAT = 3.6 V and ILOAD = 500 mA, VBUS drops to: VOUT 5.07 0.24 0.5 4.95V (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 To ensure VBUS does not overshoot the regulation point, the boost switch remains off as long as VBUS > VREFBOOST. EQ. 3 If a USB peripheral hot insertion causes VBUS to dip below VBAT, the device will commence a restart without faulting. www.fairchildsemi.com 26 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Faults Bus Timing If a BOOST fault occurs: 1. The STAT pin pulses. 2. OPA_MODE bit is reset. 3. The power stage is in High-Impedance Mode. 4. The FAULT bits (REG0[2:0]) are set per Table 13. Shown in Figure 37, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. Data change allowed Restart After Boost Faults OPA_MODE is reset on boost faults. Boost Mode can only be re-enabled by setting the OPA_MODE bit. SDA Table 13. Fault Bits During Boost Mode tH Fault Bit Fault (REG00h[2:0]) Description B2 B1 B0 0 0 0 Normal (no fault) 0 0 1 VBUS > VBUSOVP tSU SCL Figure 37. 0 1 0 VBUS fails to achieve the voltage required to advance to the next state during soft-start or sustained (>50 s) current limit during the BST state. 0 1 1 VBAT < UVLOBST 1 0 0 NA: This code does not appear. 1 0 1 Thermal shutdown 1 1 0 Timer fault; all registers reset. 1 1 1 NA: This code does not appear. Data Transfer Timing Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 38. SDA tHD;STA Slave Address MS Bit SCL Figure 38. 2 I C Interface Start Bit Transactions end with a STOP condition, which is SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 39. The FAN54063s serial interface is compatible with 2 Standard, Fast, Fast Plus, and High-Speed Mode I C bus specifications. The FAN54063 SCL line is an input and the SDA line is a bi-directional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. Slave Releases SDA Slave Address Master Drives ACK(0) or NACK(1) SCL 2 Table 14. I C Slave Address Byte Figure 39. 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 R/ W During a read from the FAN54063, the master issues a Repeated Start after sending the register address and before resending the slave address. The Repeated Start is a 1-to-0 transition on SDA while SCL is HIGH, as shown in Figure 40. In hex notation, the slave address assumes a 0 LSB. The hex slave address is D6 for all parts in the family. Other slave addresses can be accommodated upon request. Contact a Fairchild Semiconductor representative. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Stop Bit tHD;STO www.fairchildsemi.com 27 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support High-Speed (HS) Mode Read and Write Transactions The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) Modes are identical except the bus speed for HS Mode is 3.4 MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus Mode (less than 1 MHz clock); slaves do not ACK the transmission. The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, Master Drives Bus defined as and All addresses and data are MSB first. Symbol The bus remains in HS Mode until a stop bit is sent by the master. While in HS Mode, packets are separated by repeated start conditions (Figure 40). SDA tSU;STA ACK(0) or NACK(1) tHD;STA SLADDR MS Bit Definition S START, see Figure 38 A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet. R Repeated START, see Figure 40 P STOP, see Figure 39 Multi-Byte (Sequential) Read and Write Transactions SCL Figure 40. . Table 15. Bit Definitions for Figure 41- Figure 44 The master then generates a repeated start condition that causes all slaves on the bus to switch to HS Mode. The 2 master then sends I C packets, as described above, using the HS Mode clock rate and timing. Slave Releases Slave Drives Bus Repeated Start Timing Sequential Write The Slave Address, Reg Addr address, and the first data byte are transmitted to the FAN54063 in the same way as in a byte write Figure 41. However, instead of generating a Stop condition, the master transmits additional bytes that are written to consecutive sequential registers after the falling edge of the eighth bit. After the last byte written and its ACK bit received, the master issues a STOP bit. The IC contains an 8-bit counter that increments the address pointer after each byte is written. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 28 Sequential reads are initiated in the same way as a singlebyte read, except that once the slave transmits the first data byte, the master issues an acknowledge instead of a STOP (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Footprint FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support FAN54053-- USB-OTG, 1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support 2 condition. This directs the slaves I C logic to transmit the next sequentially addressed 8-bit word. The FAN54063 contains an 8-bit counter that increments the address pointer after each byte is read, which allows the entire memory 2 contents to be read during one I C transaction. Sequential Read Figure 41. Single-Byte Write Transaction Figure 42. Single-Byte Read Transaction Figure 43. Multi-Byte (Sequential) Write Transaction Figure 44. Multi-Byte (Sequential) Read Transaction www.fairchildsemi.com 29 The Twelve user-accessible IC registers are defined in Table 17. 2 Table 16. I C Register Map Register BIT NAME Name REG# 7 CONTROL0 0H TMR_RST CONTROL1 1H OREG 2H IC_INFO 3H IBAT 4H RESET VBUS_ CONTROL 5H Reserved SAFETY 6H POST_ CHARGING 7H Reserved Reserved MONITOR0 10H ITERM_CMP VBAT_CMP LINCHG T_120 ICHG IBUS VBUS_VALID CV MONITOR1 11H GATE VBAT POK_B DIS_LEVEL NOBAT PC_ON Reserved Reserved NTC 12H WD_CONTROL 13H RESTART FA 6 5 4 EN_STAT IBUSLIM 3 STAT BOOST VLOWV TE 2 1 CE# HZ_MODE OPA_MODE DBAT_B EOC FAULT OREG Vendor Code PN REVISION IOCHARGE PROD IO_LEVEL ITERM VBUS_CON VLIM VBUSLIM ISAFE Reserved Reserved (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Reserved 0 VSAFE VBUS_LOAD PC_EN PC_IT TEMP_DIS NTC_OK NTC4 NTC3 NTC2 NTC1 Reserved Reserved Reserved EN_REG WD_DIS Reserved RESTART www.fairchildsemi.com 30 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Register Descriptions This table defines the operation of each register bit. Default values are in bold text. Bit Name Value Type CONTROL0 7 6 TMR_RST EN_STAT Register Address: 00h 0 0 W R/W 1 5:4 STAT 3 BOOST Description 00 0 1 R R Writing a 1 resets the t32S timer; writing a 0 has no effect. Reading this bit always returns 0 Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults Enables STAT pin to be LOW when IC is charging Bit STAT Description 5 4 0 0 Standby 0 1 PWM enabled. Charging is occurring if CE# = 0 1 0 Charge Done 1 1 Fault IC is not in Boost Mode IC is in Boost Mode 2 0 2:0 FAULT 000 See table to the right. Default Value = 0100 0000 (40h) Fault Bit 1 0 0 0 Type FAULT Description R Normal (No Fault) 0 0 1 R VBUS OVP 0 1 0 RC Sleep Mode 0 1 1 R Poor Input Source 1 0 0 R Battery OVP 1 0 1 R Thermal Shutdown 1 1 0 RC Timer Fault 1 1 1 RC No Battery For Boost Mode faults, see Table 13. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 31 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Table 17. Register Bit Definitions Name Value Type CONTROL1 Description Register Address: 01h Default Value = 0011 0100 (34h) Input current limit 7:6 IBUSLIM 00 R/W Bit 7 6 0 0 0 1 1 0 1 1 Weak battery voltage threshold Bit 5 0 0 1 1 4 0 1 0 1 IBUSLIM (mA) 475 760 1080 No Limit VLOWV (V) 5:4 VLOWV 11 R/W 3 TE 0 R/W Setting the TE bit to a 1 will enable Charge Termination. 2 CE# 1 R/W This is an active low bit and by setting the bit to a "0" will enable Charging. When the bit is reset, it will return to the "1" state and charging will be disabled. 1 HZ_MODE 0 R/W Setting this bit to a "1" puts the device in High Impedance mode. 0 OPA_MODE 0 R/W The device is in Charge Mode when the OPA_MODE bit = 0 and in Boost Operation when the bit = 1. (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 3.4 3.5 3.6 3.7 See Table 11 www.fairchildsemi.com 32 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Name Value Type OREG Description Register Address: 02h 7:2 OREG 000010 R/W 0 1 DBAT_B 1 R/W 0 0 EOC R/W Charger output "float" voltage; programmable from 3.51 to 4.45 V in 20 mV increments. Dec Hex VOREG Dec Hex VOREG Dec Hex 0 00 3.51 16 10 3.83 32 20 1 01 3.53 17 11 3.85 33 21 2 02 3.55 18 12 3.87 34 22 3 03 3.57 19 13 3.89 35 23 4 04 3.59 20 14 3.91 36 24 5 05 3.61 21 15 3.93 37 25 6 06 3.63 22 16 3.95 38 26 7 07 3.65 23 17 3.97 39 27 8 08 3.67 24 18 3.99 40 28 9 09 3.69 25 19 4.01 41 29 10 0A 3.71 26 1A 4.03 42 2A 11 0B 3.73 27 1B 4.05 43 2B 12 0C 3.75 28 1C 4.07 44 2C 13 0D 3.77 29 1D 4.09 45 2D 14 0E 3.79 30 1E 4.11 46 2E 15 0F 3.81 31 1F 4.13 47-63 2F-3F Indicates that the IC detected a dead battery after VBUS_POR. IC_INFO The IC sets this bit to 1 if a dead battery (VBAT < VSHORT) was not detected at VBUS_POR. Writing a 1" or a "0" to this bit does not affect charger operation. The bit state will not change until the next VBUS POR. If TE = "1", and no battery is detected at ITERM, the IC turns off the PWM for tINT, then resumes charging and retries Battery Detection. If the battery is still absent, the process repeats with the "No Battery" fault re-enunciated, and sets the charging parameters to the default values (see Charge State Flow Chart) Register Address: 03h 7:6 Vendor Code 5:3 PN 010 2:0 REV (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 VOREG 4.15 4.17 4.19 4.21 4.23 4.25 4.27 4.29 4.31 4.33 4.35 4.37 4.39 4.41 4.43 4.45 If no battery is detected when a full battery (end of charge) is reached, the PWM charger stays on, allowing the host processor to continue to run with no battery. 1 10 Default Value = 0000 1000 (08h) Default Value = 1001 0XXX (9Xh) R Identifies Fairchild Semiconductor as the IC supplier R Part number bits, see Ordering Information R IC Revision bits www.fairchildsemi.com 33 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Name Value Type IBAT Description Register Address: 04h Conditions Default Value 1000 0001 (81h) Functionality Setting the RESET bit clears all registers (except SAFETY and CE#) including WD_DIS and HZ_MODE. Setting the RESET bit clears all registers (except Valid VBUS, VBAT < VLOWV SAFETY) including WD_DIS, HZ_MODE and CE#. Setting the RESET bit clears all registers (except Absent VBUS SAFETY and CE#) including WD_DIS and HZ_MODE. Writing a 0 has no effect; read returns 1 Valid VBUS, VBAT > VLOWV 7 6:3 2:0 RESET IOCHARGE ITERM 1 0000 001 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 W R/W Programs the typical charge current (550 mA default) Bit IOCHARGE (mA) 6 5 4 3 0 0 0 0 550 0 0 0 1 650 0 0 1 0 750 0 0 1 1 850 0 1 0 0 950 0 1 0 1 1,050 0 1 1 0 1,150 0 1 1 1 1,250 1 0 0 0 1,350 1 0 0 1 1,450 1010-1111 1,550 R/W Sets the current used for charging termination Bit ITERM (mA) 2 1 0 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 200 1 0 0 250 1 0 1 300 1 1 0 350 1 1 1 400 www.fairchildsemi.com 34 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Name Value Type VBUS_CONTROL 7 Reserved 6 PROD 5 IO_LEVEL Register Address: 05h 0 0 1 0 R R/W R/W 1 4 VBUS_CON 3 VLIM 2:0 VBUSLIM Description 1 100 This bit always returns 0 Charger operates in Normal Mode. Charger operates in Production Test Mode. Battery current is controlled by IOCHARGE and IBUSLIM bits while Fast Charging. During Precharge Mode, battery current is limited to 450 mA when IOCHARGE < 750 mA and 730 mA when IOCHARGE > 750 mA. IBUSLIM bits must be set to "10" or "11" or IO_LEVEL current will remain at 200 mA. Battery current control is set to 200 mA for Fast Charge and Precharge Mode. R 0 R R/W SAFETY 1 Indicates that VBUS is above 4.4 V (rising) or 3.7 V (falling). When VBUS_CON changes from 0 to 1, a STAT pulse occurs. VBUS control loop is not active (VBUS is able to stay above VBUSLIM) VBUS control loop is active and VBUS is being regulated to VBUSLIM VBUS control voltage reference Bit 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Register Address: 06h 7:4 ISAFE 0100 R/W 3:0 VSAFE 1010 R/W (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 Default Value = 001X X100 VBUSLIM (V) 4.213 4.293 4.373 4.453 4.533 4.613 4.693 4.773 Default Value = 0100 1010 (4Ah) Sets the maximum IOCHARGE value used by the control circuit Bit IOCHARGE(MAX) (mA) 7 6 5 4 0 0 0 0 550 0 0 0 1 650 0 0 1 0 750 0 0 1 1 850 0 1 0 0 950 0 1 0 1 1,050 0 1 1 0 1,050 0 1 1 1 1,250 1 0 0 0 1,350 1 0 0 1 1,450 1010-1111 1,550 Sets the maximum VOREG used by the control circuit Bit VOREG(MAX) (V) 3 2 1 0 0 0 0 0 4.21 0 0 0 1 4.23 0 0 1 0 4.25 0 0 1 1 4.27 0 1 0 0 4.29 0 1 0 1 4.31 0 1 1 0 4.33 0 1 1 1 4.35 1 0 0 0 4.37 1 0 0 1 4.39 1 0 1 0 4.41 1 0 1 1 4.43 1100-1111 4.45 www.fairchildsemi.com 35 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Name Value Type POST_CHARGING 7:6 Reserved Description Register Address: 07h 00 R Default Value = 0000 0001 (01h) These bits always return 0 After charger termination, in the charge done state, these bits control VBUS loading to improve detection of AC power removal from the AC adapter. [5:4] VBUS Loading in Charge Done State: 5:4 VBUS_LOAD 3 PC_EN 2:0 PC_IT 00 R/W 0 R/W 1 001 00 01 10 11 None Load VBUS for 4 ms every two seconds Load VBUS for 131 ms every two seconds Load VBUS for 135 ms every two seconds Post charging or background charging feature is disabled Post charging or background charging feature is enabled R/W MONITOR0 Sets the termination current for post charging Bit PC_IT (mA) 2 1 0 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 200 1 0 0 250 1 0 1 300 1 1 0 350 1 1 1 400 Register Address: 10h Default Value = XXXX XXXX 7 ITERM_CMP R ITERM comparator output, 1 when ICHARGE > ITERM reference 6 VBAT_CMP R Output of VBAT comparator, 1 when VBAT < VBUS 5 LINCHG R 1 when 30 mA linear charger ON (VBAT < VSHORT) 4 T_120 R Thermal regulation comparator, 1 when the die temperature is greater than 120C. If battery is being charged in Precharge mode, the charge current is limited to 200 mA and in Fast Charge, 550 mA. 3 ICHG R 0 indicates the ICHARGE loop is controlling the battery charge current. 2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current. 1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging. 0 CV R 1 indicates the constant-voltage loop (OREG) is controlling the charger and all current limiting loops have released. MONITOR1 Register Address: 11h Default Value = XX1X XX00 7 GATE R The GATE bit indicates the state of the GATE pin. If the bit is "0", the pin is low, driving the PFET, Q5 on. A "1" will disable Q5, but current can still flow from battery to the system through Q5s body diode. 6 VBAT R A "1" indicates VBAT > VLOWV. A "0" indicates VBAT < VLOWV in fast charging. 5 POK_B 4 DIS_LEVEL R This pin indicates the state of the DIS pin. A "1" indicates the DIS pin is high and the device is in a Hi-Z state on the input and the PWM controller is not running. 3 NOBAT R A "1" on this bit indicates that the device has determined there is no battery connected. 2 PC_ON R A "1" on this bit indicates that Post charging (background charging) is in progress. 1:0 Reserved R These bits always return 0. 1 00 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 R/W POK_B indicates the state of the POK_B pin (see section on POK_B). This bit can be set to a 1 if VBAT has fallen below VLOWV, in turn the open drain POK_B pin will be Hi-Z. www.fairchildsemi.com 36 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Name Value Type NTC 7:6 Description Register Address: 12H Reserved 00 R 0 Default Value = 000X XXXX These bits always return 0. NTC Temperature measurement results affect charge parameters. 5 TEMP_DIS 4 NTC_OK R 0 if NTC is either shorted to GND, open, or shorted to REF. 3 NTC4 R 1 indicates that NTC is above the T4 threshold. 2 NTC3 R 1 indicates that NTC is above the T3 threshold. 1 NTC2 R 1 indicates that NTC is above the T2 threshold. 0 NTC1 R 1 indicates that NTC is above the T1 threshold. 1 R/W WD_CONTROL NTC Temperature measurement results do not affect charge. Temperature measurements continue to be updated every second in the NTC1-4 monitor bits. Register Address: 13h See Battery Temperature (NTC) Monitor Default Value = 0110 1110 (6Eh) 7 Reserved 0 R This bit always returns 0 6 Reserved 1 R This bit always returns 1 5 Reserved 1 R This bit always returns 1 4 Reserved 0 R This bit always returns 0 3 Reserved 1 R This bit always returns 1 2 EN_VREG 1 R/W The EN_VREG defaults to a "1" enabling the regulator. To disable the regulator, set the bit to a "0". 1 WD_DIS 1 R/W A "1" disables the Watchdog (t32S) timer. Setting the bit to a "0" will enable the timers (See Safety Timer Section for further information). 0 Reserved 0 R RESTART 7:0 RESTART (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 This bit always returns 0 Register Address: FAh W Default Value = 1111 1111 (FFh) Writing B5h restarts charging when the IC is in the charge done state. This register reads back FF. www.fairchildsemi.com 37 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint Bit Bypass capacitors should be placed as close to the IC as possible. In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. Power and ground pins should be Figure 45. routed directly to their bypass capacitors using the top copper layer. The copper area connecting to the IC should be maximized to improve thermal performance. PCB Layout Recommendation Product-Specific Dimensions Product D E X Y FAN54063UCX 2.40 0.030 2.00 0.030 0.180 0.380 (c) 2015 Fairchild Semiconductor Corporation FAN54063 * Rev. 1.0 www.fairchildsemi.com 38 FAN54063-- High Efficiency, 1.55 A, Li-Ion Switching Charger with Power Path, USB-OTG, in a Small Solution Footprint PCB Layout Recommendation 0.03 C E 2X A F 1.60 B A1 BALL A1 INDEX AREA 1.60 D 0.40 0.40 (O0.200) Cu Pad (O0.300) Solder Mask 0.03 C RECOMMENDED LAND PATTERN (NSMD PAD TYPE) 2X TOP VIEW 0.06 C 0.625 0.547 0.05 C 0.3780.018 0.2080.021 E SIDE VIEWS C D SEATING PLANE NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. 1.60 0.005 O0.2600.02 25X 0.40 1.60 E D C B 0.40 D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS 39 MICRONS (547-625 MICRONS). (Y) 0.018 A F 1 2 3 4 5 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILENAME: MKT-UC025AArev3. (X) 0.018 BOTTOM VIEW C A B C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 1994. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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