Rev. 1.3 September 2009 www.aosmd.com Page 1 of 16
AOZ1024D
EZBuck™ 4A Synchronous Buck Regulator
General Description
The AOZ1024D is a synchronous high efficiency, simple
to use, 4A buck regulator. The AOZ1024D works from a
4.5V to 16V input voltage range, and provides up to 4A
of continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1024D comes in a DFN 5 x 4 p ackage and is
rated over a -40°C to +85°C ambient temperature range.
Features
●4.5V to 16V operating input voltage range
●Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ internal low-side switch
●High efficiency: up to 95%
●Internal soft start
●1.5% initial output accuracy
●Output voltage adjustable to 0.8V
●4A continuous output current
●Fixed 500kHz PWM opera tio n
●Cycle-by-cycle current limit
●Pre-bias start-up
●Short-circuit protection
●Thermal shutdown
●Small size DFN 5 x 4 packages
Applications
●Point of load DC/DC conversion
●PCIe graphics cards
●Set top boxes
●DVD drives and HDD
●LCD panels
●Cable modems
●Telecom/networking/datacom equipment
Typical Application
Figure 1. 3.3V/4A Synchronous Buck Regulator
LX
VIN
VOUT
VIN
FB
PGND
EN
COMP
AGND
C1
22µF
Ceramic
C2, C3
22µF
Ceramic
R1
R2
RC
CC
L1 4.7µH
AOZ1024D
Not Recommended For New Designs
Not Recommended For New Designs
Replacement Part: AOZ6604PI
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 2 of 16
Ordering Information
All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1024DI -40°C to +85°C DFN-8 Green
PGND
VIN
AGND
FB
LX
LX
EN
COMP
5 x 4 DFN
(Top Thru View)
1
2
3
4
8
7
6
5
GND
LX
Pin Number Pin Name Pin Function
1 PGND Power ground. Electrically needs to be connected to AGND.
2V
IN Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
3 AGND Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND.
4 FB The FB pin is used to determine the output voltage via a resistor divider between the output
and GND.
5 COMP External loop compensa tion pin.
6 EN The enable pin is active high. Connect in to VIN if not used and do not leave it open.
7, 8 LX PWM output conne ction to inductor.
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 3 of 16
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage th e
device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2 FR-4
board with 2oz. Copper, in a still air environment with TA = 25°C. The
value in any given application depends on the user's specific board
design.
500kHz/68kHz
Oscillator
AGND PGND
VIN
EN
FB
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
Q2
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
+
–
+
–
Frequency
Foldback
Comparator
0.2V
+
–
+
–
+
Parameter Rating
Supply Voltage (VIN)18V
LX to AGND -0.7V to VIN+0.3V
EN to AGND -0.3V to VIN+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to +0.3V
PGOOD to AGND -0.3V to 6V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2.0kV
Parameter Rating
Supply Voltage (VIN) 4.5V to 16V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Ther mal Re sistance DFN-8
(ΘJA)(2) 50°C/W
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 4 of 16
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3)
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by d esign.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 16 V
VUVLO Input Under-Voltage Lockout Threshold VIN Rising
VIN Falling 4.1
3.7 V
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 1.6 2.5 mA
IOFF Shutdown Supply Current VEN = 0V 320µA
VFB Feedback Voltage 0.788 0.8 0.812 V
Load Regulation 0.5 %
Line Regulation 1%
IFB Feedback Voltage Input Current 200 nA
VEN EN Input Threshold Off Threshold
On Threshold 20.6 V
VHYS EN Input Hysteresis 100 mV
MODULATOR
fOFrequency 350 500 600 kHz
DMAX Maximum Duty Cycle 100 %
DMIN Minimum Duty Cycle 6%
Error Amplifier Voltage Gain 500 V / V
Error Amplifier Tr ansconductance 200 µA / V
PROTECTION
ILIM Current Limit 5.0 6.0 A
Over-Temperature Shutdown Limit TJ Rising
TJ Falling 150
100 °C
tSS Soft Start Interval 3 5 6.5 ms
OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12V
VIN = 5V 97
166 130
200 mΩ
Low-Side Switch On-Resistance VIN = 12V
VIN = 5V 18
30 23
36 mΩ
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 5 of 16
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation Full Load (CCM) Operation
Startup to Full Load Short Circuit Protection
50% to 100% Load Transient Short Circuit Recovery
1μs/div 1μs/div
1ms/div 100μs/div
100μs/div 2ms/div
Vin ripple
0.1V/div
VIN
10V/div
Vo ripple
20mV/div
Vo
2V/div
lin
1A/div
Vo Ripple
200mV/div
lo
2A/div
Vo
2V/div
LX
10V/div
lL
5A/div
Vo
2V/div
IL
5A/div
IL
1A/div
VLX
10V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
Not Recommended For New Designs
Rev. 1.3 September 2009 www.aosmd.com Page 6 of 16
AOZ1024D
Efficiency
Thermal Derating Curves
For DFN package part under typical line and output voltage condition. Circuit of Figure 1. 25°C ambient temperature
and natural convection (air speed<50LFM) unless otherwise specified.
AOZ1024D Efficiency
Efficiency (VIN = 12V) vs. Load Current
1.2V OUTPUT
3.3V OUTPUT
5V OUTPUT
1.8V OUTPUT
Load Current (A)
Efficieny (%)
65
70
75
80
85
90
95
100
00.511.522.533.54
Derating Curve at 5V/6V Input
1.2V OUTPUT
3.3V
OUTPUT
3.3V
5V
OUTPUT
Ambient Temperature (T
A
)
Output Current (I
O
)
5
4
3
2
1
0
25 35 45 55 65 75 85
Derating Curve at 12 Input
1.2V, 1.8V OUTPUT
Ambient Temperature (T
A
)
Output Current (I
O
)
4.4
4.2
4.0
3.8
3.6
3.4
25 35 45 55 65 75 85
1.8V
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 7 of 16
Detailed Description
The AOZ1024D is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 16V input volt-
age range and supplies up to 4A of load current. The
duty cycle can be adjusted from 6% to 100% allowing a
wide range of output voltage. Features include enable
control, Power-On Reset, input under voltage lockout,
output over voltage protection, active high power good
state, fixed internal soft-start, and thermal shut down.
The AOZ1024D is available in a DFN 5x4 package.
Enable and Soft Start
The AOZ1024D has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on the EN pin is HIGH. In the soft start process, the
output voltage is typically ramped to regulation voltage in
4ms. The 4ms soft start time is set internally.
The EN pin of the AOZ1024D is active HIGH. Connect
the EN pin to VIN if enable function is not used. Pulling
EN to ground will disable the AOZ1024D. Do not leave it
open. The vo ltage on EN pin must be above 2V to enabl e
the AOZ1024D. When voltage on the EN pin falls below
0.6V, the AOZ1024D is disabled. If an application circuit
requires the AOZ1024D to be disabled, an open drain or
open collector circuit should be used to interface to the
EN pin.
Steady-State Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM)
.
The AOZ1024D in tegrates a n inter nal P-MOSFET as the
high-side switch. In ductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divid ed down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor curren t signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage,
the high-side switch is off. The inductor current is
freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver guar-
antees no turn on overlap of both high-side and low-side
switch.
Compared with regulators using freewheeling Schottky
diodes, the AOZ1024D uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1024D uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor
normally seen in a circuit which is using an NMOS
switch. It allows 100% turn-on of the high-side switch to
achieve linear regulation mode of operation. The mini-
mum voltage drop from VIN to VO is the load current x
DC resistance of MOSFET + DC resistance of buck
inductor. It can be calculated by equation below:
where;
VO_MAX is the maximum output voltage,
VIN is the input voltage from 4.5V to 16V,
IO is the output current from 0A to 2A, and
RDS(ON) is the on resi stance of internal MOSFET, the value is
between 97mΩ and 200mΩ depe nding on input voltage and
junction temperature.
Switching Frequency
The AOZ1024D switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
Output Voltage Programming
Output voltage can be set by feeding back the output
to the FB pin by using a resistor divider network (see
Figure 1). The resistor divider network includes R1 and
R2. Usually, a design is started by picking a fixed R2
value and calculating the required R1 with equation
below:
Some standard values of R1 and R2 for the most
commonly used output voltage values are listed in
Table 1.
VO_MAX VIN IORDSON
×–=
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 8 of 16
Table 1.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Protection Features
The AOZ1024D has multiple protection features to pre-
vent system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1024D employs peak
current mode control, the COMP pin voltage is propor-
tional to the peak inductor current. The COMP pin volt-
age is limited to be betwee n 0. 4V an d 2. 5V int er nally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slowly during
a switching cycle beca use of VO = 0V. To prevent cata-
strophic failure, a secondary current limit is designed
inside the AOZ1024D. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 5.0A and 6.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shut s down the inter nal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100ºC.
Application Information
The basic AOZ1024 application circuit is show in
Figure 1. Component selection is explained below.
Input capacitor
The input cap acitor must be conne cted to the VIN pin and
PGND pin of AOZ1024D to maint ain steady input volt age
and filter out the pulsing inp ut cu rrent. The vo ltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by equa-
tion below:
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concer n when selecting the cap acitor . For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
if we let m equal the conversion ratio:
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 on the next p age. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
VO (V) R1 (kΩ) R2 (kΩ)
0.8 1.0 Open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.6 10
5.0 52.3 10
ΔVIN
IO
fC
IN
×
----------------- 1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IO
VO
VIN
---------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 9 of 16
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have cu rrent rating higher than I CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capa citor may also be
used. When sele ctin g ce rami c capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics. Note
that the ripple current rating from capacitor manufactures
are based on certain amount of life time. Further
de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires a larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20–30%
of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Surface mount indu ctors in differ ent shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise, but they
cost more than unshielded inductors. The choice
depends on EMI requirement, price, and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capa citor
value and ESR. It can be calculated by the equation
below:
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When a low ESR ceramic capacitor is used as the output
capacitor , the imp edance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitors are
recommended to be used as output capacitors.
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
ΔIL
VO
fL×
-----------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
ΔVOΔILESRCO
1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL
1
8fC
O
××
-------------------------
×=
ΔVOΔILESRCO
×=
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 10 of 16
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
Usually, the ripple current rating of the output cap acitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, output capacitor could be over-
stressed.
Loop Compensation
The AOZ1024D employs peak current mode control for
easy use and fast tr ansient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1024D. For most ca ses,
a series capacitor and resistor network connected to the
COMP pin set s the pole-zero and is adequa te for a stable
high-bandwidth control loop.
In the AOZ1024D, FB pin and COMP pin are the invert-
ing input and the output of internal error amplifier. A
series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
C2 is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. Th e system
crossover frequency is where con trol loop has unity gain.
The crossover is the also called the conve rter bandwid th.
Generally a higher bandwidth means faster response to
load transient. Howe ver, the bandwid th should not b e too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1024D operates at a frequency range from 350kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate R3:
where;
fC is the desired crossover frequency. For best performance, fC
is set to be about 1/10 of the switching frequency;
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is 6.68
A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
ICO_RMS
ΔIL
12
----------
=
fP1
1
2πCORL
××
-----------------------------------
=
fZ1
1
2πCOESRCO
××
------------------------------------------------
=
fP2
GEA
2πC2GVEA
××
------------------------------------------
=
fZ2
1
2πCCRC
××
-----------------------------------
=
fC40kHz=
RCfC
VO
VFB
---------- 2πC2
×
GEA GCS
×
------------------------------
××=
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 11 of 16
dominate pole fp1 but lower than 1/5 of selected cross-
over frequency. C2 can is selected by:
The previous equation can also be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1024D buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor
and load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side NMOSFET.
Current flows in the second loop when the low-side
NMOSFET is on.
In PCB layout, minimizing the two loops area redu ces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1024D.
In the AOZ1024D buck regulator circuit, th e major power
dissipating components are the AOZ1024D and the
output inductor. The total power dissipation of converter
circuit can be measured by input power – output power.
The power dissipation of the inductor can be
approximately calculated by output current and DCR
of inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ1024D and thermal
impedance from junction to ambient.
The maximum junction temperature of AOZ1024D is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1024D under different ambient
temperature.
The thermal performance of the AOZ1024D is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1024D is standard DFN5*4 package. Several
layout tips are listed below for the best electric and
thermal performance. Figure 3 on the next page
illustrates a PCB layout example of AOZ1024D.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation. For full load (4A) application,
also connect the LX pads to the bottom layer by
thermal vias to enhance the thermal dissipation.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current tr ace from LX pins to L to CO to the
PGND as short as possible .
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
7. Keep sensitive signal trace far away form the LX
pins.
CC
1.5
2πRCfP1
××
-----------------------------------
=
CC
CORL
×
RC
---------------------
=
Ptotal VIN IIN VOIO
×–×=
Pinductor IO2Rinductor 1.1××=
Tjunction Ptotal Pinductor_loss
–()Θ
JA
×=
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 12 of 16
Figure 3. AOZ1024D (DFN 5x4) PCB Layout
Thermal Vias Bottom Layer
Thermal Dissipation
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 13 of 16
Package Dimensions, DFN 5x4
D
Index Area
(D/2
x
E/2)
L
R
1
E2 E3
L1
D2 D3
aaa
C
ccc
C
ddd
C
bbb
aaa
C
D/2
E/2
A3
b
A1
2.125 1.775
0.6
2.2
0.950.5
0.8
2.7
Unit: mm
A
Ae
B
E
C
CAB
Seating
Plane
Pin #1 IDA
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
Dimensions in millimeters
Recommended Land Pattern
Min.
0.80
0.00
0.35
1.975
1.625
2.500
2.050
0.600
0.400
–
–
–
–
Nom.
0.90
0.02
0.20 REF
0.40
5.00 BSC
2.125
1.775
4.00 BSC
2.650
2.200
0.95 BSC
0.700
0.500
0.30 REF
0.15
0.10
0.10
0.08
Max.
1.00
0.05
0.45
2.225
1.875
2.750
2.300
0.800
0.600
–
–
–
–
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
Dimensions in inches
Min.
0.031
0.000
0.014
0.078
0.064
0.098
0.081
0.024
0.016
–
–
–
–
Nom.
0.035
0.001
0.008 REF
0.016
0.197 BSC
0.084
0.070
0.157 BSC
0.104
0.087
0.037 BSC
0.028
0.020
0.012 REF
0.006
0.004
0.004
0.003
Max.
0.039
0.002
0.018
0.088
0.074
0.108
0.091
0.031
0.024
–
–
–
–
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 14 of 16
Tape Dimensions, DFN 5x4
R0.40
P0
K0 A0
E
E2 D0
E1
D1
B0
Package
DFN 5x4
(12 mm)
A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T
5.30
±0.10 ±0.10
4.30
±0.10
1.20 Min.
1.50 1.50 12.00
±0.10
1.75
±0.10
5.50
±0.10
8.00
±0.20
4.00
±0.10
2.00
±0.05
0.30
Unit: mm
T
Typ.
0.20
Feeding
Direction
Tape
Leader/Trailer and Orientation
±0.30
+0.10 / –0
Trailer Tape
(300mm Min.)
Components Tape
Orientation in Pocket
Leader Tape
(500mm Min.)
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 15 of 16
Reel Dimensions, DFN 5x4
VIEW: C
C
0.05
3-1.8
ø96±0.2
6.45±0.05
3-ø2.9±0.05
3-ø1/8"
3-ø1/4"
8.9±0.1
11.90
14 REF
1.8
5.0
12 REF
41.5 REF
43.00
44.5±0.1
2.00
6.50
10.0
10.71
10°
3-ø3/16"
R48 REF
ø86.0±0.1
2.20
6.2
ø13.00
ø21.20
ø17.0
R1.10
R3.10
2.00
3.3
4.0
6.10
0.80
3.00
8.00
+0.05
0.00
R0.5
1.80
2.5
38°
44.5±0.1
46.0±0.1
8.0±0.1
40°
6°
3-ø3/16"
R3.95
6.50
ø90.00
6.0
1.8
1.8
R1
8.00
0.00
-0.05
N=ø100±2 A
A
A
R121
R127
R159
R6
R55
P
B
W1
M
II I
I
6.0±1
R1
Zoom In
III
Zoom In
II
Zoom In
A
Not Recommended For New Designs
AOZ1024D
Rev. 1.3 September 2009 www.aosmd.com Page 16 of 16
AOZ1024D Package Marking
Z1024DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perfor m can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Not Recommended For New Designs
