MCM69L736CZP5.5R - Freescale Semiconductor, Inc.

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

4M Late Write HSTL

The MCM69L736C/818C is a 4M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69L818C

(organized as 256K words by 18 bits) and the MCM69L736C (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

the RAM. At the rising edge of CK, all addresses, write enables, and synchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control

signals. Read data is available at the falling edge of CK.

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)

and output voltage (VDDQ) gives the system designer greater flexibility in

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or

the entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•Byte Write Control

•Single 3.3 V +10%, –5% Operation

•HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

•HSTL — User Selectable Input Trip–Point

•HSTL — Compatible Programmable Impedance Output Drivers

•Register to Latch Synchronous Operation

•Asynchronous Output Enable

•Boundary Scan (JTAG) IEEE 1149.1 Compatible

•Differential Clock Inputs

•Optional x18 or x36 Organization

•MCM69L736C/818C–5.5 = 5..5 ns

MCM69L736C/818C–6.5 = 6.5 ns

MCM69L736C/818C–7.5 = 7.5 ns

MCM69L736C/818C–8.5 = 8.5 ns

•Sleep Mode Operation (ZZ Pin)

•119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

Order this document

by MCM69L736C/D



SEMICONDUCTOR TECHNICAL DATA

MCM69L736C

MCM69L818C

ZP PACKAGE

PBGA

CASE 999–02

REV 1

8/10/99

 Motorola, Inc. 1999

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

2MOTOROLA FAST SRAM

ADDRESS

REGISTERS

SBx

CONTROL

LOGIC

DATA IN

MEMORY

ARRAY

REGISTERS

DATA OUT

LATCH

SS SS

REGISTERS

FUNCTIONAL BLOCK DIAGRAM

PIN ASSIGNMENTS

MCM69L736C

6543217

VSS

SBb

VSS

SA SA SA SA

NC SA SA NC

DQb

SA SA

DQa

VDDQ

DQb

VDDQ

DQb

DQa

VSS

VDD

TDO

TDITMS

TCK

DQd DQd VSS SA

VDD

DQa

DQaSAVSS

DQdDQd

VDDQ DQd VSS

DQa

DQaSBa

SBdDQdDQd

DQd DQd VSS CK VSS

DQc

DQa

VDD

Vref

VDD

Vref

VDD

VDDQ

DQc VSS NC DQb

DQb

DQbNCSBc

DQcDQc

VDDQ DQc VSS G

DQbSSVSS

DQc

DQc DQc VSS ZQ DQb

VDD

NC NC SA NC

VDDQ VDDQ

6543217

VSS

SA SA SA SA

SA SA

VDDQ

DQa

VSS

VDD

TDO

TDITMS

TCK

NC DQb VSS SA

VDD

DQaSAVSS

NCDQb

VDDQ DQb VSS

DQaSBa

VSS

NCDQb

NC DQb VSS CK VSS

DQb

VDD

Vref

VDD

Vref

VDD

VDDQ

NC VSS NC DQa

DQa

NCNCSBb

DQbNC

VDDQ NC VSS G

NCSSVSS

DQbNC

DQb NC VSS ZQ DQa

VDD

NC NC SA NC

VDDQ VDDQ

MCM69L818C

DQc

TOP VIEW

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

MCM69L736C PIN DESCRIPTIONS

PBGA Pin Locations Symbol Type Description

4K CK Input Address, data in, and control input register clock. Active high.

4L CK Input Address, data in, and control input register clock. Active low.

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P

(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H

(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,

4N, 4P, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 5G, 3G, 3L

(a), (b), (c), (d) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW input. Has no effect on read cycles, active

low.

4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.

4U TCK Input Test Clock (JTAG).

3U TDI Input Test Data In (JTAG).

5U TDO Output Test Data Out (JTAG).

2U TMS Input Test Mode Select (JTAG).

4D ZQ Input Programmable Output Impedance: Programming pin.

7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 3R VDD Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers.

3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers.

3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K,

3M, 5M, 3N, 5N, 3P, 5P, 5R VSS Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4G, 4H,

1R, 7R, 1T, 2T, 6T, 6U NC —No Connection: There is no connection to the chip.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

4MOTOROLA FAST SRAM

MCM69L818C PIN DESCRIPTIONS

PBGA Pin Locations Symbol Type Description

4K CK Input Address, data in, and control input register clock. Active high.

4L CK Input Address, data in, and control input register clock. Active low.

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,

4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 3G

(a), (b) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW input. Has no effect on read cycles, active

low.

4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.

4U TCK Input Test Clock (JTAG).

3U TDI Input Test Data In (JTAG).

5U TDO Output Test Data Out (JTAG).

2U TMS Input Test Mode Select (JTAG).

4D ZQ Input Programmable Output Impedance: Programming pin.

7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 3R VDD Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers.

3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers.

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,

5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R VSS Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 2D, 7D,

1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H, 1K,

6K, 2L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R,

1T, 4T, 6U

NC —No Connection: There is no connection to the chip.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note)

Rating Symbol Value Unit

Core Supply Voltage VDD –0.5 to 4.6 V

Output Supply Voltage VDDQ – 0.5 to VDD + 0.5 V

Voltage On Any Pin Vin – 0.5 to VDD + 0.5 V

Input Current (per I/O) Iin ±50 mA

Output Current (per I/O) Iout ±70 mA

Operating Temperature TA0 to 70 °C

Temperature Under Bias Tbias –10 to 85 °C

Storage Temperature Tstg –55 to 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could af fect device reliability.

PBGA PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit Notes

Junction to Ambient (Still Air) RθJA 53 °C/W 1, 2

Junction to Ambient (@200 ft/min) Single–Layer Board RθJA 38 °C/W 1, 2

Junction to Ambient (@200 ft/min) Four–Layer Board RθJA 22 °C/W

Junction to Board (Bottom) RθJB 14 °C/W 3

Junction to Case (Top) RθJC 5°C/W 4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883

Method 1012.1).

CLOCK TRUTH TABLE

K, CLK ZZ SS SW SBa SBb SBc SBd DQ (n) DQ (n+1) Mode

L – H L L H X X X X Dout 0–35 XRead Cycle All Bytes

L – H L L L L H H H High–Z DIn 0–8 Write Cycle 1st Byte

L – H L L L H L H H High–Z DIn 9–17 Write Cycle 2nd Byte

L – H L L L H H L H High–Z DIn 18 – 26 Write Cycle 3rd Byte

L – H L L L H H H L High–Z DIn 27 – 35 Write Cycle 4th Byte

L – H L L L L L L L High–Z DIn 0–35 Write Cycle All Bytes

L – H L L L H H H H High–Z High–Z Abort W rite Cycle

L – H L H X X X X X High–Z X Deselect Cycle

X H X X X X X X High–Z High–Z Sleep Mode

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

This BiCMOS memory circuit has been

designed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established.

This device contains circuitry that will ensure

the output devices are in High–Z at power up.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

6MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)

Parameter Symbol Min Max

–5.5 Max

–6.5 Max

–7.5 Max

–8.5 Max Unit Notes

Core Power Supply Voltage VDD 3.135 — — — — 3.6 V

Output Driver Supply Voltage VDDQ 1.4 — — — — 2.0 V

Active Power Supply Current (Device Selected,

All Outputs Open, Freq = Max, VDD = Max,

VDDQ = Max). Includes Supply Currents

for VDD.

IDD1 — 795 775 750 750 — mA 5

Quiescent Active Power Supply Current

(Device Selected, All Outputs Open, Freq = 0,

VDD = Max, VDDQ = Max). Includes Supply

Currents for VDD.

IDD2 — 540 540 540 540 — mA 6

Active Standby Power Supply Current

(Device Deselected, Freq = Max, VDD = Max,

VDDQ = Max)

ISB1 — 400 400 400 400 — mA 7

CMOS Standby Supply Current (Device

Deselected, Freq = 0, VDD = Max,

VDDQ = Max, All Inputs Static at

CMOS Levels)

ISB2 — 390 390 390 390 — mA 6, 7

Sleep Mode Current (ZZ = VIH, Freq = Max,

VDD = Max, VDDQ = Max) IZZ — 100 100 100 100 — mA 6

Input Reference DC Voltage Vref (dc) 0.6 — — — — 1.1 V 8

NOTES:

1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS

bumps.

2. Supply voltage applied to VDD connections.

3. Supply voltage applied to VDDQ connections.

4. All power supply currents measured with outputs open or deselected.

5. All inputs are zero.

6. CMOS levels for I/Os are VIC ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.

7. Device deselected as defined by the Clock T ruth Table.

8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of V ref is supported, the peak–to–peak ac compo-

nent superimposed on V ref may not exceed 5% of the dc component of Vref.

DC INPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

DC Input Logic High VIH (dc) Vref + 0.1 VDD + 0.3 V

DC Input Logic Low VIL (dc) –0.5 Vref – 0.1 V

Input Leakage Current Ilkg(1) —±5µA 1

Clock Input Signal Voltage Vin –0.3 VDD + 0.3 V

Clock Input Differential Voltage (See Figure 3) VDIF (dc) 0.1 VDD + 0.6 V 2

Clock Input Common Mode Voltage Range (See Figure 3) VCM (dc) 0.6 1.1 V 3

NOTES:

1. 0 V ≤ Vin ≤ VDD for all pins.

2. Minimum instantaneous dif ferential input voltage required for dif ferential input clock operation.

3. Maximum rejectable common mode input voltage variation.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

DC OUTPUT BUFFER CHARACTERISTICS — PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE

(VDD = 3.3 V, VDDQ = 1.5 V, TA = 70°C, See Notes 1 and 2)

Parameter Symbol Min Max Unit Notes

Output Logic Low IOL (VDDQ/2) /

[(RQ/5) + 30%] (VDDQ/2) /

[(RQ/5) – 15%] A 3

Output Logic High IOH (VDDQ/2) /

[(RQ/5) + 30%] (VDDQ/2) /

[(RQ/5) – 15%] A 4

Light Load Output Logic Low VOL1 VSS 0.2 V 5

Light Load Output Logic High VOH1 VDDQ – 0.2 VDDQ V 6

NOTES:

1. The impedance controlled mode is expected to be used in point–to–point applications, driving high–impedance inputs.

2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.

3. VOL = VDDQ/2.

4. VOH = VDDQ/2.

5. IOL ≤ 100 µA.

6. | IOH | ≤ 100 µA.

DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE

(0°C ≤ TA ≤ 70°C, ZQ = VDD, See Notes 1 and 2)

Parameter Symbol Min Max Unit Notes

Output Logic Low VOL2 VSS 0.4 V 3

Output Logic High VOH2 VDDQ – 0.4 VDDQ V 4

Light Load Output Logic Low VOL3 VSS 0.2 V 5

Light Load Output Logic High VOH3 VDDQ – 0.2 VDDQ V 6

NOTES:

1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC

Standard JESD8–6 Class I.

2. The ZQ pin is connected to VDD to enable the minimum impedance mode.

3. IOL ≥ – 8 mA.

4. IOH ≥ 8 mA.

5. IOL ≥ 100 µA.

6. IOH ≥100 µA.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0°C ≤ TA ≤ 70°C, Periodically Sampled Rather Than 100% Tested)

Characteristic Symbol Typ Max Unit

Input Capacitance Cin 4 5 pF

Input/Output Capacitance CI/O 7 7 pF

CK, CK Capacitance CCK 4 7 pF

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

8MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Input Pulse Levels 0.25 to 1.25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 0.75 V. . . . . . . . . . . . . .

Output Timing Reference Level 0.75 V. . . . . . . . . . . . . . . . . . . . . . . . .

Clock Input T iming Reference Level Differential Cross–Point. . . . . .

ZQ for 50 Ω Impedance 250 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RθJA Device TBD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING

69L736C–5.5

69L818C–5.5 69L736C–6.5

69L818C–6.5 69L736C–7.5

69L818C–7.5 69L736C–8.5

69L818C–8.5

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Cycle Time tKHKH 5.5 — 6 — 7 — 8 — ns

Clock High Pulse Width tKHKL 2.2 — 2.4 — 2.8 — 3.2 — ns

Clock Low Pulse Width tKLKH 2.2 — 2.4 — 2.8 — 3.2 — ns

Clock High to Output Valid tKHQV — 5.5 — 6.5 — 7.5 — 8.5 ns

Clock Low to Output Valid tKLQV — 2.5 — 2.5 — 3 — 3.5 ns

Clock Low to Output Hold tKLQX 0.7 — 0.7 — 0.7 — 0.7 — ns 1

Clock Low to Output Low–Z tKLQX1 0.7 — 1 — 1 — 1 — ns 1, 2

Clock High to Output High–Z tKHQZ 0.7 2.5 1 2.5 1 3 1 3.5 ns 1, 2

Output Enable Low to Output

Low–Z tGLQX 0.5 — 0.5 — 0.5 — 0.5 — ns

Output Enable Low to Output

Valid tGLQV — 2.3 — 2.5 — 3 — 3.5 ns

Output Enable to Output Hold tGHQX 0.5 — 0.5 — 0.5 — 0.5 — ns

Output Enable High to Output

High–Z tGHQZ — 2.3 — 2.5 — 3 — 2.3 ns 1, 2

ZZ High to Sleep Mode tZZE — 50 — 50 — 50 — 50 ns

ZZ Low to Recovery tZZR 200 — 200 — 200 — 200 — ns

Setup T imes: Address

Data In

Chip Select

Write Enable

tAVKH

tDVKH

tSVKH

tWVKH

0.5 — 0.5 — 0.5 — 0.5 — ns

Hold T imes: Address

Data In

Chip Select

Write Enable

tKHAX

tKHDX

tKHSX

tKHWX

1 — 1 — 1 — 1 — ns

NOTES:

1. This parameter is sampled and not 100% tested.

2. Measured at ±200 mV from steady state.

The table of timing values shows either a mini-

mum or a maximum limit for each parameter. Input

requirements are specified from the external system

point of view . Thus, address setup time is shown as

a minimum since the system must supply at least

that much time. On the other hand, responses from

the memory are specified from the device point of

view. Thus, the access time is shown as a maximum

since the device never provides data later than that

time.

TIMING LIMITS

DEVICE

UNDER

TEST

Ω

0.75 V VDDQ/2

Vref

250

Ω

Figure 1. AC Test Load

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

AC INPUT CHARACTERISTICS

Parameter Symbol Min Max Notes

AC Input Logic High (See Figure 4) VIH (ac) Vref + 200 mV — 1

AC Input Logic Low (See Figures 2 and 4) VIL (ac) — Vref – 200 mV 2

Input Reference Peak–to–Peak AC Voltage Vref (ac) —5% Vref (dc) 3

Clock Input Differential Voltage Vdif (ac) 400 mV VDDQ + 600 mV 4

NOTES:

1. Inputs may overshoot to VDD – 1 V for 30% tKHKH and VDD + 1.5 V peak overshoot.

2. Inputs may undershoot to VSS – 1 V for 30% tKHKH and VSS – 1.5 V peak undershoot.

3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-

nent superimposed on Vref may not exceed 5% of the dc component of Vref.

4. Minimum instantaneous dif ferential input voltage required for dif ferential input clock operation.

VOH

VSS

50%

100% 20% tKHKH

Figure 2. Undershoot Voltage

CROSSING POINT

VDDQ

VSS

VTR

VDIF

VCP VCM*

Figure 3. Differential Inputs/Common Mode Input Voltage

*VCM, the Common Mode Input Voltage, equals VTR – [(VTR – VCP)/2].

VIH(ac)

Vref

VIL(ac)

Figure 4. AC Input Conditions

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MCM69L736C•MCM69L818C

10 MOTOROLA FAST SRAM

tKHKL

tKHKH

SA A0 A1

tKLKH

Q1 Q3

tKLQV

A2 A3 A4

tWVKH

tKHWX

tSVKH tKHSX

tAVKH tKHAX

SBx

tDVKH

Q4D2

tKHQV tKLQX

tKHDX

READ READ WRITE READ READ

tKHQZ

tKLQX1

DESELECT (HIGH–Z)

tKLQX1 tKHQZ

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

SA A0 A1 A2 A3 A4

SBx

tGLQX

READ READ WRITE READ READ

(G Controlled)

tGLQV

DESELECT (HIGH–Z)

tGHQX

Q0 Q1 Q3 Q4D2

tGHQZ

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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

SLEEP MODE TIMING

tZZE tZZR

ADDR

NORMAL OPERATION

NO READS OR

WRITES ALLOWEDIN SLEEP MODE

NO NEW READS OR

WRITES ALLOWEDNORMAL OPERATION

IZZ

IDD

MCM69L736C•MCM69L818C

12 MOTOROLA FAST SRAM

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2007

MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

FUNCTIONAL OPERATION

READ AND WRITE OPERATIONS

All control signals except G are registered on the rising

edge of the CK clock. These signals must meet the setup

and hold times shown in the AC Characteristics table. On the

falling edge of the current cycle, the output latch becomes

transparent and data is available. The output data is latched

on the rising edge of the next clock. The output data is avail-

able at the output at tKLQV or tKHQV, whichever is later.

tKHQV is the internal latency of the device. During this same

cycle, a new read address can be applied to the address

pins.

A write cycle can occur on the next cycle as long as

tKHQZ and tDVKH are met. Read cycles may follow write

cycles immediately.

G, SS, and SW control output drive. Chip deselect via a

high on SS at the rising edge of the CK clock has its effect on

the output drivers immediately. SW low deselects the output

drivers immediately (on the same cycle). Output selecting via

a low on SS and high on SW at a rising CK clock has its

effect on the output drivers at tKLQX. Output drive is also

controlled directly by output enable (G). G is an asynchro-

nous input. No clock edges are required to enable or disable

the output with G.

Output data will be valid at tGLQV, tKHQV, or tKLQV,

which is even later. Outputs will begin driving at tKLQX1.

Outputs will hold previous data until tKLQX or tGHQX, or

tKHQZ in the case of a write following a read.

WRITE AND BYTE WRITE FUNCTIONS

Note that in the following discussion the term “byte” refers

to nine bits of the RAM I/O bus. In all cases, the timing

parameters described for synchronous write input (SW)

apply to each of the byte write enable inputs (SBa, SBb,

etc.).

Byte write enable inputs have no effect on read cycles.

This allows the system designer not interested in performing

byte writes to connect the byte enable inputs to active low

(VSS). Reads of all bytes proceed normally and write cycles,

activated via a low on SW and the rising edge of CK, write

the entire RAM I/O width. This way the designer is spared

having to drive multiple write input buffer loads.

Byte writes are performed using the byte write enable

inputs in conjunction with the synchronous write input (SW).

It is important to note that writing any one byte will inhibit a

read of all bytes at the current address. The RAM can not

simultaneously read one byte and write another at the same

address. A write cycle initiated with none of the byte write

enable inputs active, is neither a read or a write. No write will

occur, but the outputs will be deselected as in a normal write

cycle.

LATE WRITE

The write address is sampled on the first rising edge of

clock, and write data is sampled on the following rising edge.

The late write feature is implemented with single stage

write buffering. Write buffering is transparent to the user. A

comparator monitors the address bus and, when necessary,

routes buffer contents to the outputs to ensure coherent

operation. This occurs in all cases, whether there is a byte

write or a full word is written.

PROGRAMMABLE IMPEDANCE OPERATION

The designer can program the RAMs output buffer imped-

ance by terminating the ZQ pin to VSS through a precision

resistor (RQ). The value of RQ is five times the output imped-

ance desired. For example, a 250 Ω resistor will give an out-

put impedance of 50 Ω.

Impedance updates occur continuously and the frequency

of the update is based on the subdivided CK clock. Note that

if the K clock stops, so does the impedance update.

The actual change in the impedance occurs in small incre-

ments and is monotonic. There are no significant distur-

bances that occur on the output because of this smooth

update method.

The impedance update is not related to any particular type

of cycle because the impedance is updated continuously and

is based on the CK clock. Updates occur regardless of

whether the device is performing a read, write, or a deselect

cycle and does not depend on the state of G.

At power up or recovery from sleep mode, the output

impedance defaults to approximately 50 Ω. It will take 4,000

to 16,000 cycles for the impedance to be completely updated

if the programmed impedance is much higher or lower than

50 Ω.

The output buffers can also be programmed in a minimum

impedance configuration by connecting ZQ to VDD.

POWER UP AND INITIALIZATION

The following supply voltage application sequence is

recommended: VSS, VDD, then VDDQ. Please note, per

the Absolute Maximum Ratings table, VDDQ is not to exceed

VDD + 0.5 V, whatever the instantaneous value of VDD.

Once supplies have reached specification levels, a minimum

dwell of 1.0 ms with CK clock inputs cycling is required

before beginning normal operations. At power up the output

impedance will be set at approximately 50 Ω as stated

above.

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MCM69L736C•MCM69L818C

14 MOTOROLA FAST SRAM

SLEEP MODE

This device is equipped with an optional sleep or low

power mode. The sleep mode pin is asynchronous and

active high. During normal operation, the ZZ pin is pulled low .

When ZZ is pulled high, the chip will enter sleep mode where

the device will meet the lowest possible power conditions.

The Sleep Mode T iming diagram shows the following modes

of operation: Normal Operation, No Read/Write Allowed, and

Sleep Mode.

Normal Operation

All inputs must meet setup and hold times prior to sleep

and tZZR nanoseconds after recovering from sleep. Clock

(CK) must also meet cycle high and low times during these

periods. T wo cycles prior to sleep, initiation of either a read or

write operation is not allowed.

No Read/Write Allowed

During the period of time just prior to sleep and during

recovery from sleep, the assertion of any write or read signal

is not allowed. If a write or read operation occurs during

these periods, the memory array may be corrupted. Validity

of data out from the RAM can not be guaranteed immediately

after ZZ is asserted (prior to being in sleep). During sleep

mode recovery, the output impedance must be given

additional time above and beyond tZZR in order to match

desired impedance (see explanation in Output Impedance

Circuitry paragraph).

Sleep Mode

The RAM automatically deselects itself. The RAM discon-

nects its internal clock buffer. The external clock may con-

tinue to run without impacting the RAMs sleep current (IZZ).

All outputs will remain in a High–Z state while in sleep mode.

All inputs are allowed to toggle. The RAM will not be

selected, and perform any reads or writes.

SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION

OVERVIEW

The serial boundary scan test access port (TAP) on this

RAM is designed to operate in a manner consistent with

IEEE standard 1149.1–1990 (commonly referred to as

JTAG), but does not implement all of the functions required

for IEEE 1149.1 compliance. Certain functions have been

modified or eliminated because their implementation places

extra delays in the RAMs critical speed path. Nevertheless,

the RAM supports the standard TAP controller architecture.

The TAP controller is the state machine that controls the T AP

operation and can be expected to function in a manner that

does not conflict with the operation of devices with IEEE

1149.1 compliant TAPs. The TAP operates using conven-

tional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS

logic level signaling.

DISABLING THE TEST ACCESS PORT

It is possible to use this device without utilizing the TAP. To

disable the TAP controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude

mid–level inputs. TDI and TMS are designed so an undriven

input will produce a response identical to the application of a

logic 1, and may be left unconnected. But they may also be

tied to VDD through a 1 k resistor. TDO should be left uncon-

nected.

TAP DC OPERATING CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Parameter Symbol Min Max Unit Notes

Logic Input Logic High VIH1 2.0 VDD + 0.3 V

Logic Input Logic Low VIL1 –0.3 0.8 V

Logic Input Leakage Current Ilkg —±5µA 1

CMOS Output Logic Low VOL1 — 0.2 V 2

CMOS Output Logic High VOH1 VDD – 0.2 — V 3

TTL Output Logic Low VOL2 — 0.4 V 4

TTL Output Logic High VOH2 2.4 — V 5

NOTES:

1. 0 V ± Vin ± VDDQ for all logic input pins.

2. IOL1 ≤ 100 µA @ VOL = 0.2 V. Sampled, not 100% tested.

3. IOH1 ≤ 100 µA @ VDDQ – 0.2 V. Sampled, not 100% tested.

4. IOL2 ≤ 8 mA @ VOL = 0.4 V.

5. IOH2 ≤ 8 mA @ VOH = 2.4 V.

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MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

TAP AC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Test Load 50 Ω Parallel Terminated T–Line with 20 pF. . . . . Receiver Input Capacitance

Test Load Termination Supply Voltage (VT) 1.5 V. . . . . . . . . . . . . . .

TAP CONTROLLER TIMING

Parameter Symbol Min Max Unit Notes

Cycle Time tTHTH 100 — ns

Clock High T ime tTHTL 40 — ns

Clock Low T ime tTLTH 40 — ns

TMS Setup tMVTH 10 — ns

TMS Hold tTHMX 10 — ns

TDI Valid to TCK High tDVTH 10 — ns

TCK High to TDI Don’t Care tTHDX 10 — ns

Capture Setup tCS 10 — ns 1

Capture Hold tCH 10 — ns 1

TCK Low to TDO Unknown tTLQX 0 — ns

TCK Low to TDO Valid tTLOV — 20 ns

NOTE:

1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to ensure accurate pad data capture.

AC TEST LOAD

DEVICE

UNDER

TEST

Ω

1.5 V

tTHDX

tTLQV

tTLQX

tDVTH

tTLTH

tTHMX

tMVTH

TAP CONTROLLER TIMING DIAGRAM

tTHTH

TEST CLOCK

(TCK)

TEST MODE SELECT

(TMS)

TEST DATA IN

(TDI)

TEST DATA OUT

(TDO)

tTHTL

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MCM69L736C•MCM69L818C

16 MOTOROLA FAST SRAM

TEST ACCESS PORT PINS

TCK — TEST CLOCK (INPUT)

Clocks all TAP events. All inputs are captured on the rising

edge of TCK and all outputs propagate from the falling edge

of TCK.

TMS — TEST MODE SELECT (INPUT)

The TMS input is sampled on the rising edge of TCK. This

is the command input for the TAP controller state machine.

An undriven TMS input will produce the same result as a

logic 1 input level.

TDI — TEST DATA IN (INPUT)

The TDI input is sampled on the rising edge of TCK. This is

the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is deter-

mined by the state of the TAP controller state machine and

the instruction that is currently loaded in the TAP instruction

same result as a logic 1 input level.

TDO — TEST DATA OUT (OUTPUT)

Output that is active depending on the state of the TAP

state machine (see Figure 6). Output changes in response to

the falling edge of TCK. This is the output side of the serial

registers placed between TDI and TDO.

TRST — TAP RESET

This device does not have a TRST pin. TRST is optional in

IEEE 1149.1. The test–logic–reset state is entered while

TMS is held high for five rising edges of TCK. Power–on

reset circuitry is included internally. This type of reset does

not affect the operation of the system logic. The reset af fects

test logic only.

TEST ACCESS PORT REGISTERS

OVERVIEW

The various TAP registers are selected (one at a time) via

the sequences of 1s and 0s input to the TMS pin as the TCK

is strobed. Each of the TAP registers are serial shift registers

that capture serial input data on the rising edge of TCK and

push serial data out on the subsequent falling edge of TCK.

When a register is selected, it is “placed” between the TDI

and TDO pins.

INSTRUCTION REGISTER

The instruction register holds the instructions that are

executed by the TAP controller when it is moved into the run

test/idle or the various data register states. The instructions

are 3 bits long. The register can be loaded when it is placed

between the TDI and TDO pins. The instruction register is

automatically preloaded with the IDCODE instruction at

power up or whenever the controller is placed in test–logic–

reset state.

BYPASS REGISTER

The bypass register is a single bit register that can be

placed between TDI and TDO. It allows serial test data to be

passed through the RAMs TAP to another device in the scan

chain with as little delay as possible.

BOUNDARY SCAN REGISTER

The boundary scan register is identical in length to the

number of active input and I/O connections on the RAM (not

counting the TAP pins). This also includes a number of place

holder locations (always set to a logic 1) reserved for density

upgrade address pins. There are a total of 70 bits in the case

of the x36 device and 51 bits in the case of the x18 device.

The boundary scan register, under the control of the TAP

controller, is loaded with the contents of the RAM I/O ring

when the controller is in capture–DR state and then is placed

between the TDI and TDO pins when the controller is moved

to shift–DR state. Several TAP instructions can be used to

activate the boundary scan register.

The Bump/Bit Scan Order tables describe which device

bump connects to each boundary scan register location. The

first column defines the bit’s position in the boundary scan

shifted out) is defined as bit 1. The second column is the

name of the input or I/O at the bump and the third column is

the bump number.

IDENTIFICATION (ID) REGISTER

The ID register is a 32–bit register that is loaded with a

device and vendor specific 32–bit code when the controller is

put in capture–DR state with the IDCODE command loaded

in the instruction register. The code is loaded from a 32–bit

on–chip ROM. It describes various attributes of the RAM as

indicated below. The register is then placed between the TDI

and TDO pins when the controller is moved into shift–DR

state. Bit 0 in the register is the LSB and the first to reach

TDO when shifting begins.

ID Register Presence Indicator

Bit No. 0

Value 1

Motorola JEDEC ID Code (Compressed Format, per

IEEE Standard 1149.1–1990)

Bit No. 11 10 9 8 7 6 5 4 3 2 1

Value 0 0 0 0 0 0 0 1 1 1 0

Reserved For Future Use

Bit No. 17 16 15 14 13 12

Value x x x x x x

Device Width

Configuration Bit No. 22 21 20 19 18

128K x 36 Value 0 0 1 0 0

256K x 18 Value 0 0 0 1 1

Device Depth

Configuration Bit No. 27 26 25 24 23

128K x 36 Value 0 0 1 0 1

256K x 18 Value 0 0 1 1 0

Revision Number

Bit No. 31 30 29 28

Value x x x x

Figure 5. ID Register Bit Meanings

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MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

MCM69L736C Bump/Bit Scan Order

Bit

No. Signal

Name Bump

ID Bit

No. Signal

Name Bump

1 M2 5R 36 SA 3B

2 SA 4P 37 NC 2B

3 SA 4T 38 SA 3A

4 SA 6R 39 SA 3C

5 SA 5T 40 SA 2C

6 ZZ 7T 41 SA 2A

7 DQa 6P 42 DQc 2D

8 DQa 7P 43 DQc 1D

9 DQa 6N 44 DQc 2E

10 DQa 7N 45 DQc 1E

11 DQa 6M 46 DQc 2F

12 DQa 6L 47 DQc 2G

13 DQa 7L 48 DQc 1G

14 DQa 6K 49 DQc 2H

15 DQa 7K 50 DQc 1H

16 SBa 5L 51 SBc 3G

17 CK 4L 52 ZQ 4D

18 CK 4K 53 SS 4E

19 G 4F 54 NC 4G

20 SBb 5G 55 NC 4H

21 DQb 7H 56 SW 4M

22 DQb 6H 57 SBd 3L

23 DQb 7G 58 DQd 1K

24 DQb 6G 59 DQd 2K

25 DQb 6F 60 DQd 1L

26 DQb 7E 61 DQd 2L

27 DQb 6E 62 DQd 2M

28 DQb 7D 63 DQd 1N

29 DQb 6D 64 DQd 2N

30 SA 6A 65 DQd 1P

31 SA 6C 66 DQd 2P

32 SA 5C 67 SA 3T

33 SA 5A 68 SA 2R

34 NC 6B 69 SA 4N

35 SA 5B 70 M1 3R

MCM69L818C Bump/Bit Scan Order

Bit

No. Signal

Name Bump

ID Bit

No. Signal

Name Bump

1 M2 5R 36 SBb 3G

2 SA 6T 37 ZQ 4D

3 SA 4P 38 SS 4E

4 SA 6R 39 NC 4G

5 SA 5T 40 NC 4H

6 ZZ 7T 41 SW 4M

7 DQa 7P 42 DQb 2K

8 DQa 6N 43 DQb 1L

9 DQa 6L 44 DQb 2M

10 DQa 7K 45 DQb 1N

11 SBa 5L 46 DQb 2P

12 CK 4L 47 SA 3T

13 CK 4K 48 SA 2R

14 G 4F 49 SA 4N

15 DQa 6H 50 SA 2T

16 DQa 7G 51 M1 3R

17 DQa 6F

18 DQa 7E

19 DQa 6D

20 SA 6A

21 SA 6C

22 SA 5C

23 SA 5A

24 NC 6B

25 SA 5B

26 SA 3B

27 NC 2B

28 SA 3A

29 SA 3C

30 SA 2C

31 SA 2A

32 DQb 1D

33 DQb 2E

34 DQb 2G

35 DQb 1H

NOTES:

1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced

to logic one. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.

2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.

3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV

of a VDD or VSS supply rail to ensure consistent results.

4. ZZ must remain at VIL during boundary scan to ensure consistent results.

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MCM69L736C•MCM69L818C

18 MOTOROLA FAST SRAM

TAP CONTROLLER INSTRUCTION SET

OVERVIEW

There are two classes of instructions defined in IEEE Stan-

dard 1149.1–1990, the standard (public) instructions and

device specific (private) instructions. Some public instruc-

tions are mandatory for IEEE 1149.1 compliance. Optional

public instructions must be implemented in prescribed ways.

Although the TAP controller in this device follows the IEEE

1149.1 conventions, it is not IEEE 1149.1 compliant because

some of the mandatory instructions are not fully imple-

mented. The TAP on this device may be used to monitor all

input and I/O pads, but can not be used to load address,

data, or control signals into the RAM or to preload the I/O

buffers. In other words, the device will not perform IEEE

1149.1 EXTEST, INTEST, or the preload portion of the

SAMPLE/PRELOAD command.

When the TAP controller is placed in capture–IR state, the

two least significant bits of the instruction register are loaded

with 01. When the controller is moved to the shift–IR state,

the instruction register is placed between TDI and TDO. In

this state, the desired instruction is serially loaded through

the TDI input (while the previous contents are shifted out at

TDO). For all instructions, the TAP executes newly loaded

instructions only when the controller is moved to update–IR

state. The TAP instruction sets for this device are listed in the

following tables.

STANDARD (PUBLIC) INSTRUCTIONS

BYPASS

The BYPASS instruction is loaded in the instruction regis-

ter when the bypass register is placed between TDI and

TDO. This occurs when the TAP controller is moved to the

shift–DR state. This allows the board level scan path to be

shortened to facilitate testing of other devices in the scan

path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public

instruction. When the SAMPLE/PRELOAD instruction is

loaded in the instruction register, moving the TAP controller

into the capture–DR state loads the data in the RAMs input

and I/O buffers into the boundary scan register. Because the

RAM clock(s) are independent from the T AP clock (TCK), it is

possible for the TAP to attempt to capture the I/O ring con-

tents while the input buffers are in transition (i.e., in a metast-

able state). Although allowing the TAP to sample metastable

inputs will not harm the device, repeatable results can not be

expected. RAM input signals must be stabilized for long

enough to meet the TAPs input data capture setup plus hold

time (tCS plus tCH). The RAMs clock inputs need not be

paused for any other TAP operation except capturing the I/O

ring contents into the boundary scan register.

Moving the controller to shift–DR state then places the

boundary scan register between the TDI and TDO pins.

Because the PRELOAD portion of the command is not

implemented in this device, moving the controller to the

update–DR state with the SAMPLE/PRELOAD instruction

loaded in the instruction register has the same effect as the

pause–DR command. This functionality is not IEEE 1149.1

compliant.

EXTEST

EXTEST is an IEEE 1 149.1 mandatory public instruction. It

is to be executed whenever the instruction register , whatever

length it may be in the device, is loaded with all logic 0s.

EXTEST is not implemented in this device. Therefore, this

device is not IEEE 1149.1 compliant. Nevertheless, this RAM

TAP does respond to an all 0s instruction, as follows. With

the EXTEST (000) instruction loaded in the instruction

SAMPLE/PRELOAD instruction described above, except the

DQ pins are forced to High–Z any time the instruction is

loaded.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded

into the ID register when the controller is in capture–DR

mode and places the ID register between the TDI and TDO

pins in shift–DR mode. The IDCODE instruction is the default

instruction loaded in at power up and any time the controller

is placed in the test–logic–reset state.

DEVICE SPECIFIC (PUBLIC) INSTRUCTION

SAMPLE–Z

If the SAMPLE–Z instruction is loaded in the instruction

(High–Z) and the boundary scan register is connected

between TDI and TDO when the TAP controller is moved to

the shift–DR state.

DEVICE SPECIFIC (PRIVATE) INSTRUCTION

NO OP

Do not use these instructions; they are reserved for future

use.

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MCM69L736C•MCM69L818C

MOTOROLA FAST SRAM

STANDARD (PUBLIC) INSTRUCTION CODES

Instruction Code* Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

DQ pins to High–Z state. NOT IEEE 1149.1 COMPLIANT.

IDCODE 001** Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not

affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1

COMPLIANT.

BYPASS 111 Places bypass register between TDI and TDO. Does not affect RAM operation.

SAMPLE–Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

DQ pins to High–Z state.

*Instruction codes expressed in binary; MSB on left, LSB on right.

**Default instruction automatically loaded at power up and in test–logic–reset state.

STANDARD (PRIVATE) INSTRUCTION CODES

Instruction Code* Description

NO OP 011 Do not use these instructions; they are reserved for future use.

NO OP 101 Do not use these instructions; they are reserved for future use.

NO OP 110 Do not use these instructions; they are reserved for future use.

*Instruction codes expressed in binary, MSB on left, LSB on right.

CAPTURE–DR

EXIT1–DR

EXIT2–DR

UPDATE–DR

CAPTURE–IR

EXIT1–IR

EXIT2–IR

UPDATE–IR

SHIFT–IR

PAUSE–IRPAUSE–DR

TEST–LOGIC

RESET

RUN–TEST/

IDLE SELECT

DR–SCAN SELECT

IR–SCAN

NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.

SHIFT–IR 0

Figure 6. TAP Controller State Diagram

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MCM69L736C•MCM69L818C

20 MOTOROLA FAST SRAM

69L736C

MCM 69L818C XX X X

Motorola Memory Prefix

Part Number

Full Part Numbers —MCM69L736CZP5.5 MCM69L736CZP6.5 MCM69L736CZP7.5 MCM69L736CZP8.5

MCM69L818CZP5.5 MCM69L818CZP6.5 MCM69L818CZP7.5 MCM69L818CZP8.5

MCM69L736CZP5.5R MCM69L736CZP6.5R MCM69L736CZP7.5R MCM69L736CZP8.5R

MCM69L818CZP5.5R MCM69L818CZP6.5R MCM69L818CZP7.5R MCM69L818CZP8.5R

R = Tape and Reel, Blank = T ray

Package (ZP = PBGA)

Speed (5.5 = 5.5 ns, 6.5 = 6.5 ns,

7.5 = 7.5 ns, 8.5 = 8.5 ns)

ORDERING INFORMATION

(Order by Full Part Number)

ZP PACKAGE

7 X 17 BUMP PBGA

CASE 999–02

PACKAGE DIMENSIONS

16X

119X

TOP VIEW BOTTOM VIEW

SIDE VIEW

0.20

6X e

7654321

0.35 A

0.25 A

0.20 A

SEATING

PLANE

0.3 CA B

0.15 A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. ALL DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS THE MAXIMUM SOLDER BALL

DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINED BY

THE SPHERICAL CROWNS OF THE SOLDER

BALLS.

DIM MIN MAX

MILLIMETERS

A––– 2.40

A1 0.50 0.70

A2 1.30 1.70

A3 0.80 1.00

D22.00 BSC

D1 20.32 BSC

D2 19.40 19.60

E14.00 BSC

E1 7.62 BSC

E2 11.90 12.10

b0.60 0.90

e1.27 BSC

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Opportunity/Af firmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:

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