RT9053AZQW - Richtek - Product.Network

RT9053A

RT9053A-01 June 2011 www.richtek.com

Applications

z Mega Sim Card

z CDMA/GSM Cellular Handsets

z Portable Information Appliances

z La ptop, Palmtops, Notebook Computers

z Hand-Held Instruments

z Mini PCI& PCI-Express Cards

z PCMCIA & New Cards

General Description

The RT9053A is a high performance, 400mA LDO regulator

a nd ultra low dropout. The quiescent current is as low a s

42μA, further prolonging the battery life. The RT9053A also

works with low ESR ceramic capacitors, reducing the

a mount of board space necessary for power a pplications,

critical in handheld wireless devices.

The RT9053A consumes typically 0.7μA in shutdown

mode. The other features include low dropout voltage, high

output accuracy, and current limiting protection. The

RT9053A is available in SOT-23-5 and WDFN-6L 2x2

packages.

Features

z Adjustable Output Voltage Down to 0.8V

z Wide Operating Voltage Ranges : 2.2V to 5.5V

z Low Dropout : 230mV at 400mA

z Ultra Fast Response in Line/Load Transient

z Current Limiting Protection

z Thermal Shutdown Protection

z Output Only 1μμ

μμ

μF Capacitor Required for Stability

z RoHS Compliant and Halogen Free

Ordering Information

Note :

Richtek roducts are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

WDFN-6L 2x2SOT-23-5

Low Dropout, 400mA Adjustable Linear Regulator

GND FB

VOUTVIN 5

GND

VIN GND EN

VOUT FB

Marking Information

3Q= : Product Code

DNN : Date Code

RT9053AGB RT9053AGQW

3Q=DNN JH : Product Code

W : Date Code

JHW

J_HW

RT9053AZQW J_H : Product Code

W : Date Code

Package Type

B : SOT-23-5

QW : WDFN-6L 2x2 (W-Type)

RT9053A

Lead Plating System

G : Green (Halogen Free and Pb Free)

Z : ECO (Ecological Element with

Halogen Free and Pb free)

(for WDFN-6L 2x2 Only)

RT9053A

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Function Block Diagram

Functional Pin Description

Pin No.

SOT-23-5 WDFN-6L 2x2 Pin Nam e Pin F u nctio n

1 3 VIN Supply Input.

2 2, 7

(Exposed Pad) GND Ground. The exposed pad must be soldered to a large PC B and

conne cted to GND for maximum power dissip ation.

3 1 EN

Chip Enable ( Active High). W hen the EN goes to a logic low, the

device will be shutdow n mode.

4 6 FB Output Voltage Feedback.

5 4 VOUT Regulator Output.

-- 5 NC N o Internal Connection.

Typical Application Circuit

Chip Enable

RT9053A

VOUT

COUT

1µF

VOUT

GND

VIN CIN

1µF VIN

Current

Limit

MOS

Driver

POR

OTP

VIN

VOUT

GND

VREF

RT9053A

RT9053A-01 June 2011 www.richtek.com

(VIN = 3.7V, CIN = COUT = 1μF, IOUT = 20mA, TA = 25°C, unless otherwise specified)

Electrical Characteristics

Absolute Maximum Ratings (Note 1)

zSupply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 6V

zEN Input Voltage ----------------------------------------------------------------------------------------------------------- 6V

zPower Dissipation, PD @ TA = 25°C (Note 2)

SOT-23-5 -------------------------------------------------------------------------------------------------------------------- 0.4W

WDFN-6L 2x2 -------------------------------------------------------------------------------------------------------------- 0.606W

zPackage Thermal Resistance

SOT-23-5, θJA --------------------------------------------------------------------------------------------------------------- 250°C/W

W DFN-6L 2x2, θJA --------------------------------------------------------------------------------------------------------- 165°C/W

WDFN-6L 2x2, θJC--------------------------------------------------------------------------------------------------------- 8.2°C/W

zLead T emperature (Soldering 10sec.) -------------------------------------------------------------------------------- 260°C

zJunction T emperature----------------------------------------------------------------------------------------------------- 150°C

zStorage T emperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM -------------------------------------------------------------------------------------------------------------------------- 2kV

MM---------------------------------------------------------------------------------------------------------------------------- 200V

Parameter Symbol T es t Condi ti ons Min Typ Max Unit

FB Reference Volta ge V FB 0.792 0.8 0.808 V

Output Vol ta ge Accuracy ΔVOUT I

OUT = 10m A −1 0 1 %

Qui esc ent Curr ent I Q I

OUT = 0m A - - 42 57 μA

Shutdown Current ISHDN V

EN = 0V - - 0. 7 1. 5 μA

Curr ent Limit I LIM RLOAD = 0Ω,

2.2V ≤ VIN < 5.5V 400 650 -- mA

Dropout V ol tage V DROP I

OUT = 400mA - - 230 350 m V

Load R egulation ΔVLOAD 1m A < I OUT < 4 00mA

2.2V ≤ VIN < 5 .5V -- -- 1 %

Line Regul ati on ΔVLINE VIN = (VOUT + 0.5) to 5. 5V,

IOUT = 1mA -- 0. 01 0.2 %/V

Logic-High VIH 1.6 -- 5.5

EN Threshold

Voltage Logic-Low VIL 0 -- 0.6

Enab le Pi n Curr ent IEN -- 1 2 μA

FB Pi n Cu rrent I FB -- 0.1 1 μA

Therm al S hutdown

Tem peratur e TSD -- 150 -- °C

Recommended Operating Conditions (Note 4)

zSupply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 2.2V to 5.5V

zJunction T emperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C

To be continued

RT9053A

4RT9053A-01 June 2011www.richtek.com

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θJA is measured in natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3

thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter Symbol Test Conditions Min Typ Max Unit

f = 1kH z, IOU T = 10 mA -- −56 --

P owe r Su p ply Re je c tio n

Rate PSRR f = 10 k Hz, IOUT = 10m A - - −35 -- dB

Out put No ise Voltage VO N VOUT = 1. 5V, COUT = 1μF,

IOUT = 0 mA -- 30 -- μVRMS

RT9053A

RT9053A-01 June 2011 www.richtek.com

Typical Operating Characteristics

EN Threshold Voltage vs. Temperature

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

-50 -25 0 25 50 75 100 125

Temperature (°C)

EN Threshold Voltage ( V

)

Rising

VIN = 3.3V, No Load

Falling

Current Limit vs. Te m pe rature

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

-50-25 0 25 50 75100125

Temperature (°C)

Current Li m it (A)

VIN = 3.3V, VOUT = 1.8V

Current Limit vs . Input Voltage

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

2.02.53.03.54.04.55.05.5

In put Voltage (V)

Current Li m it (A)

VOUT = 1.8V

Quiescent Current vs. Temperature

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

Quiescent Cur rent ( µ A

)

VIN = VEN = 3.3V, No Load

Reference Voltage vs. Temperature

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

-50 -25 0 25 50 75 100 125

Temperature (°C)

Reference Volt age (V)

VIN = VEN = 3.3V, No Load

Dropout Voltage vs. Load Current

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0 50 100 150 200 250 300 350 400

Load Cu rrent (mA)

Dropout Voltage (V)

TA = 25°C

VEN = 3.3V, VOUT = 2.5V

TA = −40°C

TA = 125°C

RT9053A

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Power On from EN

Time (5μs/Div)

VEN

(2V/Div)

VOUT

(500mV/Div) VIN = 5V, VOUT = 2.5V, No Load

Load Transient Response

Time (100μs/Div)

VOUT

(5mV/Div)

IOUT

(200mA/Div)

VIN = 3.3V, VOUT = 2.5V, ILOAD = 200mA

to 400mA, CIN = C OUT = 1μF / X7R

Enable/Shutdown Response

Time (500μs/Div)

VOUT

(1V/Div)

VEN

(5V/Div)

VIN = 5V, VOUT = 2.5V, ILOAD = 15mA

PSRR vs. Frequency

-80

-70

-60

-50

-40

-30

-20

-10

10 100 1000 10000 100000 1000000

Frequency (Hz)

PSRR ( dB)

ILOAD = 10mA, CIN = COUT = 1μF/X7R

10k 100k

10 100 1k 1M

VIN = 3.3V, VOUT = 2.5V

RT9053A

RT9053A-01 June 2011 www.richtek.com

Output Voltage Setting

The output voltage divider R1 a nd R2 allows adjustment

of the output voltage for various application as shown in

Figure 1.

Figure 1. Output Voltage Setting

The output voltage is set according to the following equation :

OUT FB R1

VV1

⎛⎞

⎜⎟

⎝⎠

where VFB is the feedback reference voltage (0.8V typical).

OUT

PSRR 20 log V

⎛⎞

=×⎜⎟

⎝⎠

A low dropout regulator with a higher PSRR ca n provide

better line transient performance.

Current Limit

The RT9053A implements an independent current limit

circuit, which monitors and controls the pass element’s

gate voltage to limit the output current at 650mA (typ.). If

the current limit condition la sts for a long time, the regulator

temperature may increase high enough to damage the

regulator itself. Therefore, the RT9053A implements

current limit function and thermal protection function to

prevent the regulator from damage when the output is

shorted to ground.

Application Information

Input Capacitor Selection

Like any low dropout linear regulator, the external

capacitors used with the RT9053A must be carefully

selected for stability and performance. The input

capa cita nce is recommended to be at le ast 1μF, a nd ca n

be increased without limit. The input capacitor must be

located at a dista nce of le ss than 0.5 inch from the input

pin of the IC and returned to a clean ground plane. Any

high-quality ceramic capacitor or tantalum capacitor can

be used for the input ca pacitor. Using input ca pa citor with

larger capacitance and lower ESR (Equivalent Series

Resistance) can obtain better PSRR and line transient

response.

Output Capacitor Selection

The RT9053A is designed specifically to work with low

ESR ceramic output capacitor to save board space and

have better performance. The output capacitor is

recommended to be at lea st 1μF. Larger ca pacitance ca n

reduce noise and improve load transient response, stability

and PSRR. The RT9053A can operate with other types of

output capacitor due to its wide stable operation range.

The output ca p a citor should be pla ced less tha n 0.5 inch

from the VOUT pin and returned to a clea n ground plane.

VOUT

RT9053A

GND

Enable Function

The RT9053A features enable/shutdown function. The

voltage at the EN pin determines the enable/shutdown

state of the regulator . To ensure the regulator will switch

on, the enable control voltage must be greater than 1.6V .

The regulator will enter shutdown mode when the voltage

at the EN pin falls below 0.6V . If the enable function is not

needed, the EN pin should be pulled high or simply tied

to VIN to keep the regulator in a n on state.

PSRR

RT9053A features high Power Supply Rejection Ratio

(PSRR), which is defined as the ratio of output voltage

change against input voltage change.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA ) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the a mbient temperature, and θJA is the junction to ambient

thermal resistance.

RT9053A

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100

120

140

160

180

0 10203040506070

Copper Area ( m m 2)

Thermal Resistance (°C/W)

Figure 2. WDFN-6L 2x2 Thermal Resista nce θJA vs. PCB

Copper Area

As shown in Figure 3, we ca n also find the W DF N-6L 2x2

maximum power dissipation improvement by different

copper area design at ambient temperature TA = 25°C

operation.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 10203040506070

Copper Area (mm 2)

Maximum Power Di ssipation (W) 1

Figure 3. Maximum Power Dissipation PD vs. PCB

Copper Area

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. For the RT9053A packages, the derating

curves in Figure 4 allow the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

Figure 4. Derating Curves for RT9053A Packages

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0 25 50 75 100 125

Ambient Tem pera ture (°C)

Maximum Power Di ssipation (W ) 1

Copper Area

W DF N 2x2 70mm2

W DF N 2x2 15mm2

WDFN 2x2, Min. Layout

SOT-23-5, Min Layout

Single-Layer PCB

For recommended operating condition specifications of

the RT9053A, the maximum junction temperature is 125°C

and TA is the a mbient temperature. The junction to a mbient

thermal resista nce, θJA, is layout dependent. For WDFN-

6L 2x2 packages, the thermal resistance, θJA, is 165 °C/

W on a standard JEDEC 51-3 single-layer thermal test

board. For SOT-23-5 packages, the thermal resistance,

θJA, is 250°C/W on a sta ndard JEDEC 51-3 single-layer

thermal test board. The maximum power dissipation at

TA = 25°C ca n be calculated by the following formulas :

PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for

W DF N-6L 2X2 package

PD(MAX) = (125°C − 25°C) / (250°C/W) = 0.400W for

SOT-23-5 package

The thermal resistance θJA is determined by the package

architecture design and the PCB layout design. However,

the package architecture design had been already

designed. If possible, it's useful to increase thermal

performance by the PCB layout copper design. The thermal

resistance θJA can be decreased by adding copper area

under the exposed pad of WDFN series pa ckage.

As shown in Figure 2, we can find the relation between

the copper area and the thermal resistance θJA. The

thermal resistance will be reduced by adding more copper

area. When IC mounted to the standard footprint, the

thermal resistance θJA is 165°C/W. Adding copper area

of pad to 15mm2 under the package reduces the θJA to

150°C/W. Even further , increa sing the copper area of pad

to 70mm2 reduces the θJA to 130°C/W.

RT9053A

RT9053A-01 June 2011 www.richtek.com

Outline Dimension

AA1

SOT-23-5 Surface Mount Package

Dimensions In Millimeters Dimens io ns In Inches

Symbol Min Max Min Max

A 0.889 1.295 0.035 0.051

A1 0.000 0.152 0.000 0.006

B 1.397 1.803 0.055 0.071

b 0.356 0.559 0.014 0.022

C 2.591 2.997 0.102 0.118

D 2.692 3.099 0.106 0.122

e 0.838 1.041 0.033 0.041

H 0.080 0.254 0.003 0.010

L 0.300 0.610 0.012 0.024

RT9053A

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Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8862)86672399 Fax: (8862)86672377

Email: marketing@richtek.com

D im e n si on s In Millim e te rs Di m en s ion s In Inch e s

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250

0.007 0.010

b 0.200 0.350 0.008 0.014

D 1.950 2.050 0.077 0.081

D2 1.000 1.450 0.039 0.057

E 1.950 2.050 0.077 0.081

E2 0.500 0.850 0.020 0.033

e 0.650 0.026

L 0.300 0.400

0.012 0.016

W-Type 6L DFN 2x2 Package

SEE DETAIL A

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options