KAF-40000 7304 (H) x 5478 (V) Full Frame CCD Image Sensor Description The KAF-40000 Image Sensor is a high performance, 40-megapixel CCD. Based on the TRUESENSE 6.0 micron Full Frame CCD Platform, the sensor features ultra-high resolution, broad dynamic range, and a four-output architecture. A lateral overflow drain suppresses image blooming, while an integrated Pulse Flush Gate clears residual charge on the sensor with a single electrical pulse. A Fast Dump Gate can be used to selectively remove a line of charge to facilitate partial image readout. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. The sensor shares a common pin-out and electrical configuration with the KAF-50100 Image Sensor, allowing a single camera design to support both members of this sensor family. Table 1. GENERAL SPECIFICATIONS Parameter Figure 1. KAF-40000 CCD Image Sensor Features * TRUESENSE Transparent Gate Electrode Typical Value Architecture Full Frame CCD (Square Pixels) Total Number of Pixels 7410 (H) x 5566 (V) = 41.2 Mp Number of Effective Pixels 7336 (H) x 5510 (V) = 40.4 Mp Number of Active Pixels 7304 (H) x 5478 (V) = 40.0 Mp Pixel Size 6.0 mm (H) x 6.0 mm (V) Active Image Size 45.76 mm (H) x 35.34 mm (V) 54.78 mm (Diagonal), 645 1.3x Optical Format Aspect Ratio 4:3 Horizontal Outputs 4 Saturation Signal 42 ke- Output Sensitivity 31 mV/e- Quantum Efficiency (Peak R, G, B) 42%, 44%, 38% Read Noise (f = 18 MHz) 13 e- Dark Signal (T = 60C) 42 pA/cm2 Dark Current Doubling Temperature 5.5C Dynamic Range (f = 18 MHz) 70.2 dB Estimated Linear Dynamic Range (f = 18 MHz) 69.3 dB Charge Transfer Efficiency Horizontal Vertical www.onsemi.com * * * * for High Sensitivity Ultra-High Resolution Board Dynamic Range Low Noise Architecture Large Active Imaging Area Application * Digitization * Mapping/Aerial * Photography ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. 0.999995 0.999999 Blooming Protection (4 ms Exposure Time) 1400X Saturation Exposure Maximum Date Rate 18 MHz Package Ceramic PGA Cover Glass MAR Coated, 2 Sides NOTE: All Parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2015 September, 2015 - Rev. 3 1 Publication Order Number: KAF-40000/D KAF-40000 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAF-40000-FXA-JD-AA Gen2 Color (Bayer RGB), Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAF-40000-FXA-JD-AE Gen2 Color (Bayer RGB), Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KAF-40000-CXA-JD-AA* Gen1 Color (Bayer RGB), Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAF-40000-CXA-JD-AE* Gen1 Color (Bayer RGB), Microlens, Enhanced, ESD, Ceramic PGA, Clear Cover Glass with AR Coating (Both Sides), Engineering Sample Marking Code KAF-40000-FX Serial Number KAF-40000-CX Serial Number *Not recommended for new designs. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF-40000 DEVICE DESCRIPTION Architecture 1 Test Row 26 16 V1 V1 4 KAF-40000 7304 (H) x 5478 (V) 6.0 x 6.0 mm Pixels 4 28 16 16 28 4 1 Test Column PFG FDG LOD 1 Test Column V2 V2 4 (Last VCCD Phase = V2) H1L OGL H1R OG R 4 Blue + 12 Buffer Pixels 29 Dark Pixels RD L RG L VDD LA VOUT LA VSS L VSUB 1 10 4 1 4 28 16 3652 PFG FDG LOD RD R RG R VDD RA 3652 16 28 4 1 4 10 1 VOUT RA VSS R VSUB VOUT LB VDD LB 1 10 4 1 4 28 16 3652 3652 16 28 4 1 4 10 1 VOUT RB VDD RB XG H1B L H2 L H1A L H1A R H2R H1B R 3716 Pixels/Line/Output Figure 2. Block Diagram non-uniformities. For the leading 16 active column pixels, the first 4 pixels are covered with blue pigment while the remaining active buffer pixels are arranged in a Bayer pattern (R, GR, GB, B). Dark Reference Pixels Surrounding the periphery of the device is a border of light shielded pixels creating a dark region. Existing within this dark region are light shielded pixels that include 28 leading dark pixels on every line. There are also 29 full dark lines at the start and 26 full dark lines at the end of every frame. Under normal circumstances, these pixels do not respond to light and may be used as a dark reference. CTE Monitor Pixels Two CTE test columns, at the leading end of each output, and one CTE test row are included for manufacturing test purposes. Dummy Pixels Within each horizontal shift register there are 20 leading pixels. These are designated as dummy pixels and should not be used to determine a dark reference level. These pixels are noted on the block diagram as the leading pixels in a horizontal line sequence: 1 + 10 + 4 + 1 (CTE monitor pixel) + 4. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs (charge) within the device. These photon-induced electrons are collected locally by the formation of potential wells at each pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons are discharged into the lateral overflow drain (LOD) to prevent crosstalk or `blooming'. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. Active Buffer Pixels Forming the outer boundary of the effective active pixel region, there are 16 unshielded active buffer pixels between the photoactive area and the dark reference. These pixels are light sensitive but they are not tested for defects and www.onsemi.com 3 KAF-40000 Charge Transport in the Fast Dump Gate (FDG) row that are drained using the separate FDG pin. Draining is accomplished by first clocking V2 high while V1 is held low. This forces all charge into the V2 phase of the pixel. While V2 is high, PFG (or FDG) may be clocked high to begin draining the signal from the pixel to the LOD. Charge transfer out of the pixel is fully completed only after V2 has been clocked low plus some characteristic time. The integrated charge from each pixel in the Vertical CCD (VCCD) is transported to the output using a two-step process. Each remaining line (row) of charge is first transported from the VCCD to a dual parallel split horizontal register (HCCD) using the V1 and V2 register clocks. The transfer to the HCCD occurs on the falling edge of V2 while H1A is held high. This line of charge may be readout immediately (dual split) or may be passed through a transfer gate (XG) into a second (B) HCCD register while the next line loads into the first (A) HCCD register (dual parallel split). Readout of each line in the HCCD is always split at the middle and, thus, either two or four outputs are used. Left (or right) outputs carry image content from pixels in the left (or right) columns of the VCCD. A separate connection to the last H1 phase (H1L) is provided to improve the transfer speed of charge to the output amplifier. On each falling edge of H1L, a new charge packet is sensed by the output amplifier. Left and right HCCDs are electrically isolated from each other except for the common transfer gate (XG). Horizontal Register Output Structure The output consists of a floating diffusion connected to a three-stage source follower. Charge presented to the floating diffusion (FD) is converted into a voltage and is current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the FD. Once the signal has been sampled by the system electronics, the reset gate (RG) is clocked to remove the signal and FD is reset to the potential applied by reset drain (RD). Increased signal at the floating diffusion reduces the voltage seen at the output pin. To activate the output structure, an off-chip current source must be added to the VOUT pin of the device. See Figure 4. Pulsed Flush Gate/Fast Dump Gate The Pulsed Flush Gate (PFG) feature is used to drain the charge of all pixels prior to exposure. The exception is pixels H2 H1 H2 HCCD Charge Transfer HIL VDD OG RG RD Floating Diffusion VOUT VSUB VSS Source Follower #1 Source Follower #2 Source Follower #3 Figure 3. Output Architecture (Each Output) www.onsemi.com 4 KAF-40000 Output Load VDD = +15 V 0.1 mF IOUT = |5 mA| VOUT 2N3904 or Equivalent Buffered Video Output 140 W 1 kW NOTE: Component values may be revised based on operating conditions and other design considerations. Figure 4. Recommended Output Structure Load Diagram www.onsemi.com 5 KAF-40000 Physical Description Pin Description and Device Orientation DIRECTION OF TRANSFER DIRECTION OF TRANSFER To VOUTLA To VOUTRA To VOUTLB To VOUTRB PIN 1 Figure 5. Image Transfer Diagram Viewed from the Top (Cover Glass Side) VSUB FDG V1 V2 LOD LOD V2 V1 FDG VSUB D 1 2 3 4 5 8 9 10 11 12 D C 1 2 3 4 5 8 9 10 11 12 C LOD PFG V1 V2 PFG V2 V1 PFG LOD 7 6 PFG VSUB VSUB KAF-40000 XG VSUB VSUB NC B VOUTLA VOUTLB OGL RGL H1LL H1BL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B A 1 2 3 4 5 6 7 10 11 12 13 14 15 16 A VSUB VDDLA VSSL RDL VDDLB H1AL H2L H1BR H1LR RGR OGR VOUTRB VOUTRA H2R H1AR VDDRB RDR VSSR VDDRA VSUB Notes: 1. Pins with the same name are nominally tied together on the circuit board and have the same operating conditions. In addition, pins labeled with left (`L') and (`R') designations may also be tied together except for VOUT pins. 2. To achieve optimal output signal matching, electrical layout of the PCB should be made as symmetrical as possible relative to the left and right sides of the sensor. Figure 6. Pinout Diagram www.onsemi.com 6 KAF-40000 Table 3. PIN DESCRIPTION Pin Name A1 VSUB A2 VDDLA A3 VSSL A4 RDL A5 VDDLB A6 H1AL Pin Name Substrate C1 LOD Lateral Overflow Drain Output Amplifier Supply, Left A C2 PFG Pulse Flush Gate Output Amplifier Return, Left C3 V1 Vertical Phase 1 Reset Drain, Left C4 V2 Vertical Phase 2 Output Amplifier Supply, Left B C5 PFG Pulse Flush Gate Horizontal Phase 1, A Left C6 VSUB Substrate VSUB Substrate Description Description A7 H2L Horizontal Phase 2, Left C7 A10 H2R Horizontal Phase 2, Right C8 PFG Pulse Flush Gate Horizontal Phase 1, A Right C9 V2 Vertical Phase 2 Output Amplifier Supply, Right B C10 V1 Vertical Phase 1 A11 H1AR A12 VDDRB A13 RDR Reset Drain, Right C11 PFG Pulse Flush Gate A14 VSSR Output Amplifier Return, Right C12 LOD Lateral Overflow Drain A15 VDDRA A16 VSUB D1 VSUB D2 FDG Fast Dump Gate Output Amplified Supply, Right A Substrate Substrate B1 VOUTLA Video Output, Left A D3 V1 Vertical Phase 1 B2 VOUTLB Video Output, Left B D4 V2 Vertical Phase 2 B3 OGL Output Gate, Left D5 LOD Lateral Overflow Drain B4 RGL Reset Gate, Left D8 LOD Lateral Overflow Drain B5 H1LL Horizontal Phase 1, Last Gate, Left D9 V2 Vertical Phase 2 B6 H1BL Horizontal Phase 1, B Left D10 V1 Vertical Phase 1 B7 XG Fast Dump Gate Horizontal Transfer Gate D11 FDG D12 VSUB B8 VSUB Substrate B9 VSUB Substrate Substrate NOTE: The leads are on a 0.100 spacing. B10 NC B11 H1BR No Connection Horizontal Phase 1, B Right B12 H1LR Horizontal Phase 1, Last Gate, Right B13 RGR Reset Gate, Right B14 OGR Output Gate, Right B15 VOUTRB Video Output, Right B B16 VOUTRA Video Output, Right A www.onsemi.com 7 KAF-40000 IMAGING PERFORMANCE Table 4. TYPICAL OPERATIONAL CONDITIONS Test Condition - Unless Otherwise Noted Units 2093 ms Variable 33 200 250 1000 ms Variable 2126 (2093 + 33) 2293 (2093 + 200) 2343 (2093 + 250) 3093 (2093 + 1000) ms 364.3 ms 12 (as Tested) MHz Temperature - Room 20 C Room Temperature Temperature - Device 29 C Typical Device Operating Temperature at Test Room Temperature Description Readout Time (tREADOUT) Integration Time (tINT) Frame Time (tREADOUT + tINT) Line Time (tLINE) Horizontal Clock Frequency Operation Notes Includes 140 Overclock Pixels Includes 178 Overclock Lines Low Light Tests Saturation Tests Brightfield Tests Darkfield and Linearity Tests Low Light Tests Saturation Tests Brightfield Tests Darkfield and Linearity Tests Nominal Operating Levels Includes 140 Overclock Pixels Guaranteed for 18 MHz Operation Dual Parallel Split Mode Table 5. SPECIFICATIONS Description Symbol Min. Nom. Saturation Signal (Note 1) NSAT Ne-SAT Q/V 1075 1300 42 31 Photoresponse Non-Linearity (Note 2) PRNL 5 Photoresponse Non-Uniformity (Note 3) PRNU Max. Units Verification Plan15 mV e- mV/e- Die 10 % Die 8.5 25 % p-p Die VDARK,READ 18 20 mV/s Die VDARK,INT 3 10 mV/s Die DSNU 1 4 mV p-p Die Dark Signal Doubling Temperature (Note 4) DT 5.5 C Design Read Noise (Note 7) NR 13 e- rms Design Dynamic Range (Note 8) DR 70.2 dB Design DRLIN (Est.) 69.3 dB Design RGHueUnif BGHueUnif 5 % Die Readout Dark Signal (Note 4) Integration Dark Signal (Note 5) Dark Signal Non-Uniformity (Notes 6, 16) Estimated Linear Dynamic Range Red-Green Hue Shift Blue-Green Hue Shift (Note 9) Horizontal Charge Transfer Efficiency (Note 10) HCTE 0.999995 Vertical Charge Transfer Efficiency VCTE 0.999999 0.999998 XAB 800 1400 DC Offset, Output Amplifier (Note 12) VODC 6.0 7.5 Output Amplifier Bandwidth (Note 13) f-3dB Output Impedance, Amplifier ROUT Reset Feedthrough VRFT Blooming Protection (Note 11) 12 Die Die 9.5 220 100 145 0.5 www.onsemi.com 8 300 x ESAT Design V Die MHz Design W Die V Design KAF-40000 Table 5. SPECIFICATIONS (continued) Description Symbol Min. Nom. Max. - - - 39 45 37 - - - - - - 600 530 470 - - - - - - 37 41 37 - - - - - - 600 520 470 - - - Units Verification Plan15 % QE Design nm Design % QE Design nm Design KAF-40000-FXA CONFIGURATION GEN2 COLOR Peak Quantum Efficiency Red Green Blue Peak Quantum Efficiency Wavelength Red Green Blue QEMAX lQE KAF-40000-CXA CONFIGURATION GEN1 COLOR (Note 17) Peak Quantum Efficiency Red Green Blue Peak Quantum Efficiency Wavelength Red Green Blue QEMAX lQE 1. Increasing output load currents to improve bandwidth will decrease these values. 2. Worst-case deviation (from 15 mV & 90% NSAT min) relative to a linear fit applied between 0 and 65% of VSAT. 3. Difference between the maximum and minimum average signal levels of 168 x 168 blocks within the sensor on a per color basis as a % of average signal level. 4. T = 60C. tINT = 0. Average non-illuminated signal with respect to over-clocked horizontal register signal. 5. T = 60C. Average non-illuminated signal with respect to over-clocked vertical register signal. 6. T = 60C. Absolute difference between the maximum and minimum average signal levels of 168 x 168 blocks within the sensor. 7. rms deviation of horizontal over-clocked pixels measured in the dark. 8. 20Log (Ne-SAT / NR) 9. Gradual variations in hue (red with respect to green pixels and blue with respect to green pixels) in regions of interest (168 x 168 blocks) within the sensor. The specification refers to the largest value of the response difference. 10. Measured per transfer above and below (~70% VSAT min) saturation exposure levels. Typically, no degradation in HCCD CTE is observed up to 18 MHz. 11. XAB is the number of times above the VSAT illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the imager height. XAB is measured at 4 ms. 12. Video level offset with respect to ground. 13. Last stage only. Assumes 5 pF off-chip load. 14. Amplitude of feed-through in VOUT during RG clocking. 15. A "die" parameter is measured on every sensor during production testing. A "design" parameter is quantified during design verification and not guaranteed by specification. 16. tINT = 1000 ms. 17. This color filter set configuration (Gen1) is not recommended for new designs. www.onsemi.com 9 KAF-40000 TYPICAL PERFORMANCE CURVES KAF-40000 Average Quantum Efficiency 50 45 35 30 25 20 15 10 5 0 350 400 450 500 550 600 650 700 750 800 850 Wavelength (nm) Figure 7. Spectral Response KAF-40000 Response Difference (GR-GB) QE Response Difference (GR-GB) Absolute Quantum Effeciency (%) 40 Wavelength (nm) Figure 8. Typical GR-GB QE Difference www.onsemi.com 10 900 950 1000 1050 1100 KAF-40000 KAF-40000 Anti-Blooming Performance 6000 5000 XAB 4000 3000 2000 1000 0 0 5 10 15 20 Integration Time (ms) Figure 9. Minimum Expected Anti-Blooming Performance www.onsemi.com 11 25 KAF-40000 DEFECT DEFINITIONS Operating Conditions Bright defect tests performed at T = 25C, tINT = 250 ms and tREADOUT = 2093 ms. Dark defect tests performed at T = 25C, tINT = 1,000 ms and tREADOUT = 2093 ms. Table 6. SPECIFICATIONS Classification Points Clusters Single Columns Includes Dead Columns Standard Grade < 4,000 < 50 < 20 Yes A column that deviates by more that 1.5% above or below neighboring columns under illuminated conditions. Point Defects A pixel that deviates by more than 36 mV above neighboring pixels under non-illuminated conditions. A pixel that deviates by more than 7% above or 11% below neighboring pixels under illuminated conditions Column defects are separated by no less than 4 good columns. No multiple column defects (double or more) will be permitted. Cluster Defect A grouping of not more than 10 adjacent point defects. Column and cluster defects are separated by at least 4 good columns in the x direction. Cluster defects are separated by no less than 4 good pixels in any direction. Dead Column A column that deviates by more than 50% below neighboring columns under illuminated conditions. Column Defect A grouping of more than 10 point defects along a single column. Saturated Column A column that deviates by more than 120 mV above neighboring columns under non-illuminated conditions. No saturated columns are allowed. A column that deviates by more that 1.2 mV above neighboring columns under non-illuminated conditions. www.onsemi.com 12 KAF-40000 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Diode Pin Voltages (Notes 1, 2) VDIODE -0.5 20 V Gate Pin Voltages (Notes 1, 3) VGATE1 -14.3 14.5 V RG Pin Voltage (Note 1) VRG -0.5 14.5 V Overlapping Gate Voltages (Note 4) V1-2 -14.3 14.5 V Non-Overlapping Gate Voltages (Note 5) Vq-q -14.3 14.5 V Output Bias Current (Note 6) IOUT -30 mA LOD Diode Voltage (Note 1) VLODT -0.5 13.5 V TOP 0 60 C Operating Temperature (Note 7) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Referenced to pin VSUB. 2. Includes pins: RD, VDD, VSS, VOUT. 3. Includes pins: V1, V2, H1A, H1B, H1L, H2, OG, PFG, FDG, XG. 4. Voltage difference between overlapping gates. Includes: V1 to V2, H1/H1L to H2, H1L to OG, V1 to H2, PFG to V1/V2, FDG to V1/V2, XG to H1A/H1B/H2. 5. Voltage difference between non-overlapping gates. Includes: V1 to H1A/H1B/H1L, V2 to XG, H2 to PFG/FDG, PFG to FDG. 6. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF (Mean Time to Failure). 7. Noise performance will degrade at higher temperatures. Power-up Sequence 1. Connect the ground pins (VSUB). 2. Supply the appropriate biases and clocks to the remaining pins. The sequence chosen to perform an initial power-up is not critical for device reliability. A coordinated sequence may minimize noise and the following sequence is recommended: Table 8. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) Reset Drain (Note 1) VRD 11.3 11.5 11.7 V IRD = 0.01 Output Amplifier Return (Note 1) VSS 0.5 0.7 1.0 V ISS = 3.0 Output Amplifier Supply (Note 1) VDD 14.5 15.0 15.5 V IOUT + ISS Substrate VSUB V 0.01 Output Gate (Note 1) VOG -2.2 -2.0 -1.8 V 0.01 Lateral Drain (Note 1) VLOD 9.8 10.0 10.2 V 0.01 Video Output Current (Note 2) IOUT 5 10 mA Description 0 1. Subscripts (L, R, LA, LB, RA, RB, T, B) have not been included in the symbol list. 2. An output load sink must be applied to VOUT to activate output amplifier - see Figure 4. www.onsemi.com 13 KAF-40000 AC Operating Conditions Table 9. CLOCK LEVELS Description Symbol Level Minimum Nominal Maximum Units V1 V1L Low -9.2 -9.0 -8.8 V V1H High 2.3 2.5 2.7 V V2 H1A H1B H1L H2 RG PFG FDG XG V2L Low -9.2 -9.0 -8.8 V V2H High 3.3 3.5 3.7 V H1L Low -4.2 -4.0 -3.8 V H1H High 1.8 2.0 2.2 V H1L Low -4.2 -4.0 -3.8 V H1H High 1.8 2.0 2.2 V H1LLOW Low -6.2 -6.0 -5.8 V H1LHIGH High 1.8 2.0 2.2 V H2L Low -4.2 -4.0 -3.8 V H2H High 1.8 2.0 2.2 V VRGL Low 0.8 1.0 1.2 V VRGH High 7.8 8.0 8.2 V PFGL Low -9.2 -9.0 -8.8 V PFGH High 4.8 5.0 5.2 V FDGL Low -9.2 -9.0 -8.8 V FDGH High 4.8 5.0 5.2 V XGL Low -4.7 -4.5 -4.3 V XGH High 2.8 3.0 3.2 V 1. Subscripts (L, R) have not been included in this symbol column. 2. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate). 3. Capacitance values of left/right combined. www.onsemi.com 14 KAF-40000 Capacitance Model PFG H1A VDD 258 nF V1 439 pF H1B VSS 455 nF V2 484 pF H2 917 pF H1L 20 pF RG 16 pF FDG 76 pF RD 517 nF LOD 7 pF 17 pF 15 pF XG 120 pF 237 pF VOUT (Each) OG 13 pF 7 pF Figure 10. Lumped Capacitance Value Model - KAF-40000 NOTE: A simplified pin capacitance model is provided by ON Semiconductor as a guideline for circuit design and tends to overstate the effective capacitance experienced by the clock driver. This model should be used as a reference. Although it is a moderately accurate target, it does not represent the values required for any automated circuit analysis. www.onsemi.com 15 KAF-40000 TIMING Table 10. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units H1, H2 Clock Frequency (Note 1, 2) fH 18 MHz V1, V2 Clock Frequency (Note 1, 2) fV 25 kHz V1-V2 Cross-over VVCR 0 1.0 2.7 V H1-H2 Cross-over VHCR -2.0 -1.0 0 V H1, H2 Setup Time tHS 5 ms V2-H1A Delay tD1 5 ms H1A-XG Delay tD2 30 ms XG-V2 Delay tD3 5 ms H1, H2 Rise, Fall Times (Note 5, 6) tH1r, tH1f 5 H1L Rise - H2 Fall Crossover (Note 9) VH1LCR -2.0 V1, V2 Rise, Fall Times (Note 5) tV1r, tV1f 5 RG Clock Pulse Width (Note 7) tRGw 5 tRGr, tRGf 5 tVw 16 te 55.56 RG Rise, Fall Times (Note 5) V1, V2 Clock Pulse Width (Notes 2, 3, 4) Pixel Period (1 Count) (Note 2) -1.0 10 % 1.0 V 10 % ns 10 20 % ms ns H1L-VOUT Delay tHV 10 ns RG-VOUT Delay tRV 5 ns Readout Time (Note 8) tREADOUT - DS tREADOUT - DPS 1.35 0.76 s tF - DS tF - DPS 0.7 1.3 fps Line Rate (Note 8) tLINEDS - DS tLINEDP - DPS 242.2 274.4 ms PFG Holdoff Time tPFG 180 ms FDG Holdoff Time tFDG 20 ms Frame Rate (Note 8) 1. 2. 3. 4. 5. 6. 7. 8. 9. 50% duty cycle values. CTE will degrade above the maximum frequency. Longer times will degrade noise performance. Measured where VCLOCK is at 0 V. Relative to the pulse width (based on 50% of high/low levels). The maximum specification or 10 ns whichever is greater based on the frequency of the horizontal clocks. RG should be clocked continuously. DS = Dual Split DPS = Dual Parallel Split. The charge capacity near the output could be degraded if the voltage at the clock crossover point is outside this range. www.onsemi.com 16 KAF-40000 Edge Alignment Horizontal Clock H1AL/H1AR/H1BL/H1BR H2L/H2R VHCR H1LL/H1LR H2L/H2R VH1LCR Vertical Clock V2 V1 VVCR Figure 11. Timing Edge Alignment www.onsemi.com 17 KAF-40000 Frame Timing Dual-Parallel Split timing reads pixels out of all four outputs with even lines reading out of VOUTLA and VOUTRA and odd lines reading out of VOUTLB and VOUTRB. Dual split timing reads the pixels out of VOUTLA and VOUTRA. H1B may be grounded in this operating mode. Frame Timing - Dual Split tINT V1 V2 tREADOUT Line 1 2 5565 3 5566 H1A/B/L H2 XG Frame Timing - Dual-Parallel Split tINT V1 V2 tREADOUT Line Pair 1 3 2 2782 2783 H1A XG H1B/L H2 Figure 12. Frame Timing Frame Timing Detail Vertical Clocks V1 V1HIGH 90% tV 10% V1LOW tV1r tV1f V2 V2HIGH 90% tV 10% V2LOW tV2r tV2f Figure 13. Frame Timing Detail www.onsemi.com 18 KAF-40000 Line Timing (Each Output) H1A (tD2), and then passed through XG (tD3) and into H1B. During this time, a second, full resolution, row will load into H1A at the second falling edge of V2 following the characteristic delay tHD. XG is held low unless the Dual-Parallel Split timing is required. While operating in Dual-Parallel Split mode, full resolution rows are passed from V2 (tD1), through Line Timing - Dual Split t LINE tV tV t HS V1 V2 H1A/B/L 3716 Cnts H2 XG Line Timing - Dual-Parallel Split t LINE tV tV tV t D3 t HS V1 V2 H1A XG t D1 H1B/L t D2 tV 3716 Cnts H2 Figure 14. Line Timing www.onsemi.com 19 KAF-40000 Pixel Timing te H1A/B/L H2 RG VOUT Figure 15. Pixel Timing Pixel Timing Detail Reset Clock RGHIGH RGL/RGR 90% tRGw VRG 10% RGLOW tRGr tRGf Horizontal Clocks H1AHIGH/ H1BHIGH/ H2HIGH H1AR/H1BR/H2R/ H1AL/H1BL/H2L 90% 50% te / 2 10% tHr tHf H1LHIGH H1LR/H1LL H1ALOW/ H1BLOW/ H2LOW 90% 50% te / 2 10% tHr tHf Figure 16. Pixel Timing Detail www.onsemi.com 20 H1LLOW KAF-40000 MODE OF OPERATION Pulse Flush Gate Timing The PFG clock resets all pixels in the array (except the FDG row). Charge transfer out of the pixel is fully completed only after V2 has been clocked low as shown. Frame Timing - Pulse Flush Operation tFLUSH tINT tREADOUT V1 V2 tV PFG tPFG Figure 17. Pulse Flush Gate Timing Fast Dump Gate (FDG) Timing The FDG clock only resets pixels that happen to be in the FDG row. Charge transfer out of the pixel is fully completed only after V2 has been clocked low plus the characteristic time period (tFDG). The position of the FDG row is illustrated in Figures 19-21, including the timing required for a simple 1 line dump operation. Row# 4 3 2 Fast Dump Gate Row 1 Bottom LOD Contact Row HCCD Register A HCCD Register B Figure 18. Fast Line Dump Layout Line Timing - Fast Dump Gate tFDG V1 V2 FDG H1 3716 Cnts H2 t0 t1 t2 t3 t4 t5 Figure 19. One Line Dump Timing Example www.onsemi.com 21 KAF-40000 Line Timing - Fast Dump Gate (3 Line Dump) tV tV tFDG V1 V2 FDG H1 3716 Cnts H2 Figure 20. Line Dump Timing Example t0 V2 4 VCCD 4 3 FDG LOD 2 1 V1 V2 V1 V2 V1 V2 V1 V2 t1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR2 B2 GR2 B2 R1 GB1 R1 GB1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR2 R1 B2 GB1 t3 t2 GR2 R1 GR4 B4 GR4 B4 R3 GB3 R3 GB3 GR4 B4 GR4 B4 R3 GB3 R3 GB3 B2 t5 t4 GR4 B4 GR4 B4 R3 GB3 R3 GB3 R1 GB1 R1 GB1 GB1 R1 GB1 R1 B4 GR4 B4 R3 GB3 R3 GB3 R1 GB1 R1 GB1 GB1 R1 V1 V2 HCCD A GB1 R1 GB1 XG HCCD B NOTE: Areas highlighted in yellow represent pixels drained of charge. Figure 21. One Line Dump Pixel Illustration Using Color Filter Designation www.onsemi.com 22 GR4 KAF-40000 STORAGE AND HANDLING Table 11. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Storage Temperature (Note 1) TST -20 70 C 1. Long-term storage toward the maximum temperature will accelerate color filter degradation. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 23 KAF-40000 MECHANICAL DRAWINGS Completed Assembly Figure 22. Completed Assembly Drawing www.onsemi.com 24 KAF-40000 Alignment Marks The 98 + 48 mark should be used if alignment to die surface is required. Figure 23. Individual Alignment Mark "98 + 48" (1 of 4) 2 2 3 3 Diagonal: Image Center X-Y: Die Center 1 4 1 4 NOTE: Image center is -0.55 mm (X) and 34.05 mm (Y) from Die center. Figure 24. Location of Recommended Alignment Marks (4 Locations) www.onsemi.com 25 KAF-40000 Locations of marked alignment marks are listed in the table below with respect to the die center. Locations are listed in mm from the die center. Table 12. Alignment Mark X Location Y Location 1 -22700 -16340 2 -22700 16340 3 22700 16340 4 22700 -16340 Locations of marked alignment marks are listed in the table below with respect to the image center. Locations are listed in mm from the image center. Table 13. Alignment Mark X Location Y Location 1 -22699.45 -16374.05 2 -22699.45 16305.95 3 22700.55 16305.95 4 22700.55 -16374.05 Cover Glass Specification 1. Substrate material Schott D263T eco or equivalent. 2. 10 mm max. scratch/dig specification on the glass. No defect in the glass that exceeds 10 mm in any X-Y dimension. 3. Multilayer anti-reflective coating. Table 14. Wavelength Total Reflectance 420-450 2% 450-630 1% 630-680 2% ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 26 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAF-40000/D