1/40
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© 2009 ROHM Co., Ltd. All rights reserved.
Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
BR24L□□-W Series,BR24S□□□-W Series
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides
a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
BR24L□□-W Series assort 1Kbit～64Kbit. BR24S□□□-W Series are possible to operate at high speed in low voltage
and assort 8Kbit～256Kbit.
Contents
BR24L□□-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
・・・・P2
BR24S□□□-W Series
BR24S08-W, BR24S16-W, BR24S32-W, BR24S64-W,
BR24S128-W, BR24S256-W
・・・P20
No.09001EDT04
Technical Note
2/40
www.rohm.com 2009.09 - Rev.D
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
BR24L□□-W Series
●Description
BR24L□□-W series is a serial EEPROM of I2C BUS interface method.
●Features
1) Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 1.8V~5.5V *1 single power source action most suitable for battery use
4) Page write mode useful for initial value write at factory shipment
5) Highly reliable connection by Au pad and Au wire
6) Auto erase and auto end function at data rewrite
7) Low current consumption
At write operation (5V) : 1.2mA (Typ.)
*2
At read operation (5V) : 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
9) Write mistake prevention function at low voltage
10) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package *3
11) Data rewrite up to 1,000,000 times
12) Data kept for 40 years
13) Noise filter built in SCL / SDA terminal
14) Shipment data all address FFh
*1 BR24L02-W, BR24L16-W, BR24L32-W : 1.7～5.5V
*2 BR24L32-W, BR24L64-W : 1.5mA
*3 Refer to following list
●Page write
Number of
Pages 8Byte 16Byte 32Byte
Product
number
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
●BR24L series
Capacity Bit
format Type Power source
Voltage SOP8 SOP-J8 SSOP-B8 TSSOP-B8 MSOP8 TSSOP-B8J VSON008
X2030
1Kbit 128×8 BR24L01A-W 1.8～5.5V ● ● ● ● ● ● ●
2Kbit 256×8 BR24L02-W 1.7～5.5V ● ● ● ● ● ● ●
4Kbit 512×8 BR24L04-W 1.8～5.5V ● ● ● ● ● ● ●
8Kbit 1K×8 BR24L08-W 1.8～5.5V ● ● ● ● ● ● ●
16Kbit 2K×8 BR24L16-W 1.7～5.5V ● ● ● ● ● ●
32Kbit 4K×8 BR24L32-W 1.7～5.5V ● ● ● ●
64Kbit 8K×8 BR24L64-W 1.8～5.5V ● ●
Technical Note
3/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Limits Unit
Impressed voltage VCC -0.3～+6.5 V
Permissible dissipation Pd
450 (SOP8)
*1
mW
450 (SOP-J8)
*2
300 (SSOP-B8)
*3
330 (TSSOP-B8)
*4
310 (MSOP8)
*5
310 (TSSOP-B8J)
*6
300 (VSON008X2030)
*7
Storage temperature range Tstg -65～+125 ℃
Action temperature range Topr -40～+85 ℃
Terminal voltage - -0.3～Vcc+1.0 V
When using at Ta=25℃ or higher, 4.5mW(*1,*2),
3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,*6) to be reduced per 1℃
●Memory cell characteristics (Ta=25℃, Vcc=1.8～5.5V)*1
Parameter Limits Unit
Min. Typ. Max.
Number of data rewrite times
*2
1,000,000 - - Times
Data hold years
*2
40 - - Years
○Shipment data all address FFh
*1 BR24L02/16/32-W : 1.7~5.5V
*2 Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage Vcc 1.8～5.5 *1 V
Input voltage VIN 0～Vcc
*1 BR24L02/16/32-W : 1.7~5.5V
●Electrical characteristics (Unless otherwise specified, Ta=-40～+85℃, VCC=1.8～5.5V) *1
Parameter Symbol Limits Unit Conditions
Min. Typ. Max.
“HIGH” input voltage 1 VIH1 0.7Vcc - Vcc +1.0
*2 V 2.5≦Vcc≦5.5V
“LOW” input voltage 1 VIL1 -0.3
*2 - 0.3 Vcc V 2.5≦Vcc≦5.5V
“HIGH” input voltage 2 VIH2 0.8Vcc - Vcc +1.0
*2 V 1.8≦Vcc＜2.5V
“LOW” input voltage 2 VIL2 -0.3
*2 - 0.2 Vcc V 1.8≦Vcc＜2.5V
“HIGH” input voltage 3 *3 VIH3 0.8Vcc - Vcc +1.0 V 1.7≦Vcc＜1.8V
“HIGH” input voltage 3 *4 VIH3 0.9Vcc - Vcc +1.0 V 1.7≦Vcc＜1.8V
“LOW” input voltage 3 *2 VIL3 -0.3 - 0.1 Vcc V 1.7≦Vcc＜1.8V
“LOW” output voltage 1 VOL1 - - 0.4 V IOL=3.0mA, 2.5V≦Vcc≦5.5V, (SDA)
“LOW” output voltage 2 VOL2 - - 0.2 V IOL=0.7mA, 1.7V≦Vcc＜2.5V, (SDA)
Input leak current ILI -1 - 1 μAVIN=0V～Vcc
Output leak current ILO -1 - 1 μAVOUT=0V～Vcc, (SDA)
Current consumption at
action
ICC1 - -
2.0 *5 mA Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
3.0 *6
ICC2 - - 0.5 mA Vcc=5.5V,fSCL=400kHz
Random read, current read,sequential read
Standby current ISB - - 2.0 μAVcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
◎Radiation resistance design is not made.
*1 BR24L02/16/32-W : 1.7～5.5V, *2 BR24L16/32-W, *3 BR24L02/16-W, *4 BR24L32-W
*5 BR24L01A/02/04/08/16-W, *6 BR24L32/64-W
Technical Note
4/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Action timing characteristics (Unless otherwise specified, Ta=-40～+85℃, VCC=1.8～5.5V)*1
Parameter Symbol
FAST-MODE
2.5V≦Vcc≦5.5V
STANDARD-MODE
1.8V≦Vcc≦5.5V Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency fSCL - - 400 - - 100 kHz
Data clock “HIGH“ time tHIGH 0.6 - - 4.0 - - μs
Data clock “LOW“ time tLOW 1.2 - - 4.7 - - μs
SDA, SCL rise time *2 tR - - 0.3 - - 1.0 μs
SDA, SCL fall time *2 tF - - 0.3 - - 0.3 μs
Start condition hold time tHD:STA 0.6 - - 4.0 - - μs
Start condition setup time tSU:STA 0.6 - - 4.7 - - μs
Input data hold time tHD:DAT 0 - - 0 - - ns
Input data setup time tSU:DAT 100 - - 250 - - ns
Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs
Output data hold time tDH 0.1 - - 0.2 - - μs
Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs
Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs
Internal write cycle time tWR - - 5 - - 5 ms
Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs
WP hold time tHD:WP 0 - - 0 - - ns
WP setup time tSU:WP 0.1 - - 0.1 - - μs
WP valid time tHIGH:W
P 1.0 - -- 1.0 - - μs
*1 BR24L02/16/32-W : 1.7～5.5V
*2 Not 100% tested
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action
at high speed is not carried out, therefore, at Vcc=2.5V～5.5V , 400kHz, namely, action is made in FASTMODE. (Action is
made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE.
Technical Note
5/40
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BR24L□□-W Series,BR24S□□□-W Series
●Sync data input / output timing
SDA
tSU:STA tSU:STOtHD:STA
START BIT STOP BIT
SCL
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing
SDA
Write data
(n-th address) Stop condition Start condition
SCL
ｔWR
ACK
D0
Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution
tHIGH:WP
WP
SDA D1 D0 ACK ACK
DATA(1) DATA(n)
tWR
SCL
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cance
SCL
SDA
WP
ｔHD：WP
ストップコンディション
ｔWR
D1 D0
A
CK
A
CK
DATA(1) DATA(n)
tSU：WP
Stop condition
SD
A
(入力)
SDA
(出力)
tHD:STA tHD:DAT
tSU:DAT
tBUF tPD tDH
tLOW
tHIGHtR tF
SCL
(input)
(output)
Technical Note
6/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Block diagram
Fig.2 Block diagram
●Pin assignment and description
Terminal
name
Input /
output
Function
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
A0 Input Slave address setting Not connected Slave address setting
A1 Input Slave address setting Not connected Slave address setting
A2 Input Slave address setting Not used Slave address setting
GND - Reference voltage of all input / output, 0V
SDA Input /
output Slave and word address, Serial data input serial data output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc - Connect the power source.
1Kbit~64Kbit EEPROM arra
y
Control circuit
High voltage
generating circuit Power source
voltage detection
7bit
8bit
9bit
10bit
11bit
12bit
13bit
Address
decoder
Slave - word
address register
Data
register
8bit
7bit
8bit
9bit
10bit
11bit
12bit
13bit
START STOP
ACK
*1
*1
1
2
3
4
8
7
6
5 SDA
SCL
WP
Vcc
A1
A0
A2
GND
*2
*2
*2
＊1 7bit : BR24L01A-W
8bit : BR24L02-W
9bit : BR24L04-W
10bit : BR24L08-W
11bit : BR24L16-W
12bit : BR24L32-W
13bit : BR24L64-W
＊2 A0=N.C. : BR24L04-W
A0, A1=N.C. : BR24L08-W
A0, A1= N.C. A2=Don’t Use : BR24L16-W
1
1
1
2
1
3
1
4
1
8
1
6
1
5
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
A0
1
7
A1
A2
GND
Vcc
WP
SCL
SDA
Technical Note
7/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Characteristic data (The following values are Typ. ones.)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
ICC2[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=-40℃
Ta=85℃
SPEC
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
ILI[μA]
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC
0
1
2
3
4
5
6
0123456
Vcc[V]
VIH1,2[V]
Ta=85℃
Ta=-40℃
Ta=25℃
SPEC
0
1
2
3
4
5
6
0123456
Vcc[V]
VIL1,2[V]
Ta=85℃
Ta=-40℃
Ta=25℃
SPEC
0
0.2
0.4
0.6
0.8
1
0123456
IOL2[mA]
VOL2[V]
Ta=-40℃
Ta=85℃ Ta=25℃
SPEC
Fig.3 H input voltage VIH1,2 Fig.4 L input voltageVIL1,2　(SCL,SDA,WP)
Fig.6 L output voltage VOL2-IOL2　(VCC=1.8V)
0
0.2
0.4
0.6
0.8
1
0123456
IOL1[mA]
VOL1[V]
Ta=25℃
Ta=-40℃
Ta=85℃
SPEC
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
ILO[μA]
SPEC
Ta=85℃
Ta=25℃
Ta=-40℃
Fig.5 L output voltage　VOL1-IOL1　(VCC=2.5V)
Fig.7 Input leak current ILI　(SCL,WP) Fig.8 Output leak current　ILO(SDA)
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ICC1[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=85℃
Ta=-40℃
SPEC
[BR24L01/02/04/08/16 series]
0
0.5
1
1.5
2
2.5
3
3.5
0123456
Vcc[V]
ICC1[mA]
SPEC
Ta=25℃
Ta=85℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
[BR24L32/64 series]
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ISB[μA]
Ta=-40℃
Ta=85℃
Ta=25℃
SPEC
1
10
100
1000
10000
0123456
Vcc[V]
fSCL[kHz]
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC2
SPEC1
0
1
2
3
4
5
0123456
Vcc[V]
tHIGH [μs]
SPEC2
Ta=-40℃
Ta=25℃
Ta=85℃ SPEC1
0
1
2
3
4
5
0123456
Vcc[V]
tLOW[μs]
SPEC2
SPEC1
Ta=85℃
Ta=25℃
Ta=-40℃
0
1
2
3
4
5
0123456
Vcc[V]
tHD:STA[μs]
SPEC2
SPEC1
Ta=85℃
Ta=25℃
Ta=-40℃
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
ICC2[mA]
SPEC
fSCL=100kHz
DATA=AAh
Ta=-40℃
Ta=85℃
Ta=25℃
Fig.10 Current consumption at WRITE action ICC1
(fSCL=400kHz)
Fig.11 Current consumption at READ action ICC2
(fSCL=400kHz)
Fig.13 Current consumption at WRITE action ICC1
(fSCL=100kHz)
Fig.14 Current consumption at READ action ICC2
(fSCL=100kHz)
Fig.15 Standby current　ISB Fig.16 SCL frequency　fSCL Fig.17 Data clock "H" time tHIGH
Fig.18 Data clock "L" time tLOW Fig.19 Start condition hold time　tHD:STA
0
1
2
3
4
5
6
0123456
Vcc[V]
tSU:STA[μs]
SPEC2
SPEC1
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.20 Start condition setup time tSU:STA
0
0.5
1
1.5
2
2.5
3
3.5
0123456
Vcc[V]
ICC1[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=85℃
Ta=-40℃
SPEC
[BR24L32/64 series]
Fig.9 Current consumption at WRITE action ICC1
(fscl=400kHz)
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ICC1[mA]
SPEC
Ta=25℃
Ta=85℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
[BR24L01/02/04/08/16 series]
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
Technical Note
8/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Characteristic data (The following values are Typ. ones).
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SDA H)[μs]
SPEC1,2
Ta=25℃ Ta=-40℃
Ta=85℃
0
1
2
3
4
0123456
Vcc[V]
tPD1[μs]
SPEC1
SPEC2
SPEC2
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1
0
1
2
3
4
0123456
Vcc[V]
tPD0[μs]
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC2
SPEC1
SPEC2
SPEC1
-200
-150
-100
-50
0
50
0123456
Vcc[V]
tHD:DAT(HIGH)[ns]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=85℃
-200
-150
-100
-50
0
50
0123456
Vcc[V]
tHD:DAT(LOW)[ns]
SPEC1,2
Ta=-40℃
Ta=85℃
Ta=25℃
-200
-100
0
100
200
300
0123456
Vcc[V]
tSU:DAT(LOW)[ns]
Ta=-40℃
Ta=85℃
Ta=25℃
SPEC1
SPEC2
-200
-100
0
100
200
300
0123456
Vcc[V]
tSU:DAT(HIGH)[ns]
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1
SPEC2
Fig.21 Input data hold time tHD:DAT(HIGH) Fig.22 Input data hold time　tHD:DAT(LOW) Fig.23 Input data setup time　tSU:DAT(HIGH)
Fig.24 Input data setup time tSU:DAT(LOW) Fig.25 Output data delay time tPD0 Fig.26 Output data delay time　tPD1
0
1
2
3
4
5
0123456
Vcc[V]
tBUF[μs]
SPEC2
SPEC1
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
6
0123456
Vcc[V]
tWR[ms]
SPEC1,2
Ta=25℃
Ta=-40℃
Ta=85℃
Fig.27 Bus release time before transfer start tBUF Fig.28 Internal write cycle time　tWR
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SCL H)[μs]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SCL L)[μs]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SDA L)[μs]
SPEC1
Ta=-40℃
Ta=85℃
Ta=25℃
-0.6
-0.4
-0.2
0
0.2
0123456
Vcc[V]
tSU:WP[μs]
SPEC1,2
Ta=85℃
Ta=-40℃
Ta=25℃
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
tHIGH:WP[μs]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.29 Noise removal valid time tI(SCL H)
Fig.30 Noise removal valid time tI(SCL L) Fig.31 Noise removal valid time tI(SDA H) Fig.32 Noise removal valid time tI(SDA L)
Fig.33 WP setup time　tSU:WP Fig.34 WP valid time　tHIGH:WP
Technical Note
9/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●I2C BUS communication
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices
connected by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
Fig.35 Data transfer timing
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is
as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
PS, P0～P2 are page select bits.
Note) Up to 4 units BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Type Slave address
Maximum number of
connected buses
BR24L01A-W 1 0 1 0 A2 A1 A0 R/W
―
8
BR24L02-W 1 0 1 0 A2 A1 A0 R/W
―
8
BR24L04-W 1 0 1 0 A2 A1 PS R/W
―4
BR24L08-W 1 0 1 0 A2 P1 P0 R/W
―
2
BR24L16-W 1 0 1 0 P2 P1 P0 R/W
―
1
BR24L32-W 1 0 1 0 A2 A1 A0 R/W
―
8
BR24L64-W 1 0 1 0 A2 A1 A0 R/W
―
8
89 89 89
S P
condition condition
ACK STOPACKDATA DATAADDRES
S
START R/W ACK
1-7
SDA
SCL 1-7 1-7
Technical Note
10/40
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BR24L□□-W Series,BR24S□□□-W Series
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
Fig.37 Byte write cycle (BR24L32/64-W)
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
Fig.39 Page write cycle (BR24L32/64-W)
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W)
: Up to 16bytes (BR24L04-W, BR24L08-W,BR24L16-W)
: Up to 32bytes (BR24L32-W, BR24L64-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.)
・As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of
word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W,
after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the
address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data
up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written.
・As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word
address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
Fig.40 Difference of slave address of each type
W
R
I
T
E
S
T
A
R
T
R
/
W
C
K
S
T
O
P
WORD
ADDRESS(n) DAT
A
(n)
SDA
LINE
C
K
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
7 D0D7 D0
WA
0
Note) *1
*2
A1 A2 WA
7 D7
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 WA
0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note) *1
*1 As for WA7, BR24L01A-W becomes Don’t care.
A1 A2 1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
12
WA
11
* WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
* * *1 As for WA12, BR24L32-W becomes Don’t care.
*1 As for WA7, BR24L01A-W becomes Don’t care.
*2 As for BR24L01A/02-W becomes (n+7).
*1 As for WA12, BR24L32-W becomes Don’t care.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st W ORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 D0
Note) *1
DATA(n)
D0D7
A
C
K
2nd WORD
ADDRESS(n)
WA
0
WA
12
WA
11
* * *
10 0
1A0
A1
A2
*1 *2 *3
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
Technical Note
11/40
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BR24L□□-W Series,BR24S□□□-W Series
○Notes on write cycle continuous input
*1 BR24L01A-W becomes Don’t care.
*2 BR24L04-W, BR24L08-W, and BR24L16-W become (n+15).
*3 BR24L32-W and BR24L64-W become (n+31).
Fig.41 Page write cycle
Note)
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and in BR24L16-W, A0 becomes P0.
Fig.42 Difference of each type of slave address
○Notes on page write cycle
List of numbers of page write
Number of Pages 8Byte 16Byte 32Byte
Product
number
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24L02-W, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.).
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS（ｎ） DATA(n)
SDA
LINE
A
C
K
DATA(n+7)
A
C
K
SLAVE
ADDRESS
10 0 1A0 A1 A2 WA
7
D0D7 D0
*1
A
C
K
Note)
WA
0 1 100
Next command
tWR(maximum : 5ms)
Command is not accepted for this period.
At STOP (stop bit),
write starts.
*2
*3
S
T
A
R
T
10 0
1A0
A1
A2
*1 *2 *3
Technical Note
12/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
○Internal address increment
Page write mode (in the case of BR24L02-W)
For example, when it is started from address 06h,therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
＊ 06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level.
Do not use it open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
WA7 ----- WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0
0 ----- 0 0 0 0 1
0 ----- 0 0 0 1 0
0 ----- 0 0 1 1 0
0 ----- 0 0 1 1 1
0 ----- 0 0 0 0 0
---------
---------
---------
06h
Significant bit is fixed.
No digit up
Increment
Technical Note
13/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used
when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address
data can be read in succession.
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
Fig.44 Random read cycle (BR24L32/64 -W)
Fig.45 Current read cycle
Fig.46 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at
SCL signal 'H'.
Note)
Fig.47 Difference of slave address of each type
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 WA
7 A0 D0
SLAVE
ADDRESS
10 0
1A1A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
N
ote
)
*1
It is necessary to input 'H' to
the last ACK.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS（ｎ）
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1
A2 D7 D0
*
2nd WORD
ADDRESS（ｎ）
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
100
1A2
A1
R
/
W
R
E
A
D
A0
WA
0
Note) *1
WA
12
WA
11
**
*1 As for WA12, BR24L32-W become Don’t care.
*1 As for WA7, BR24L01A-W become Don’t care.
S
T
A
R
T
S
T
O
P
SDA
LINE
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 D0 D7
R
/
W
R
E
A
D
Note)
It is necessary to input 'H' to
the last ACK.
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
10 0
1A0
A1
A2 D0 D7 D0D7
Note）
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
10 0
1A0
A1
A2
*1 *2 *3
Technical Note
14/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48(a), Fig.48(b), and Fig.48(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Fig.48-(a) The case of dummy clock +START+START+ command input
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
* Start command from START input.
Fig.48-(c) START×9+ command input
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
Fig.49 Case to continuously write by acknowledge polling
1 2 13
14
SCL
Dummy clock×14 Start×2
2
1 8 9
Dummy clock×9 Start
Start
Normal command
Normal command
Normal command
Normal command
Start×9
SDA
1 2 3 8 9
7 Normal command
Normal command
SCL
SDA
SCL
SDA
Slave
address
Word
address
…
S
T
A
R
T
First write command
A
C
K
H
A
C
K
L
Slave
address
Slave
address
Slave
address Data
Write command
During internal write,
ACK = HIGH is sent back.
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
tWR
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
Technical Note
15/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise
of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.50.) After
execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Fig.50 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
Fig.51 Case of cancel by start, stop condition during slave address input
・Rise of D0 taken clock
SCL
D0 ACK
Enlarged view
SCL
SDA
Enlarged view
ACK
D0
・Rise of SDA
SDA
WP
WP cancel invalid area WP cancel valid area
Write forced end
Data is not written. Data not guaranteed
D7 D6 D5 D4 D3 D2 D1 D0 Data tWR
SDA D1
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
Word
address
Slave
address
SCL
SDA 1 1
0 0
Start condition Stop condition
Technical Note
16/40
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BR24L□□-W Series,BR24S□□□-W Series
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential ○
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2Vcc.
VCC - ILRPU - 0.2Vcc ≧ VIH
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
from (2)
≦ 300 [kΩ]
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX ≦ VIL-0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with N.C.PIN BR24L16/F/FJ/FV/FVT/FVM/FVJ-W A0, A1, A2
BR24L08/F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1
BR24L04/F/FJ/FV/FVT/FVM/FVJ/NUX-W A0
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
∴ R
PU ＝ 0.8Vcc-VIH
IL
RPU ≧ 3-0.4
3×10 -3
≧ 867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
VC-VOL
IOL
VCC-VOL
RPU ≦ I
OL ∴ RPU ≦
Fig.52 I/O circuit diagram
RPU
A
BR24LXX
SDA terminal
IL IL
Microcontroller
Bus line
capacity
CBUS
RPU ≦ 0.8×3-0.7×3
10×10-6
Technical Note
17/40
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BR24L□□-W Series,BR24S□□□-W Series
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential ○
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
(VCC－VOL)×RS + VOL+0.1VCC≦VIL
RPU+RS
∴RS≦VIL－VOL－0.1VCC ×RPU
1.1VCC－VIL
Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ
from(2), RS≦0.3×3－0.4－0.1×3 × 20×103
1.1×3－0.3×3
≦1.67［kΩ］
VCC ≦I
RS
∴RS≧VCC
I
Example)When VCC=3V, I=10mA
RS≧3
10×10-3
≧300［Ω］
Microcontroller EEPROM
'L' output
R
S
R
PU
'H' output
Over currentⅠ
Fig.55 I/O circuit diagram
RPU
Microcontroller
RS
EEPROM
Fig.53 I/O circuit diagram
Fig.54 Input / output collision timing
A
CK
'L' output of EEPROM
'H' output of microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
SCL
SDA
RPU
Microcontroller
RS
EEPROM
IOL
A
Bus line
capacity CBUS
VOL
VCC
VIL
Fig.56 I/O circuit diagram
Technical Note
18/40
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BR24L□□-W Series,BR24S□□□-W Series
●I2C BUS input / output circuit
○Input (A0,A2,SCL)
○Input / output (SDA)
○Input (A1, WP)
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
Recommended conditions of tR, tOFF,Vbot
tR tOFF Vbot
10ms or below 10ms or longer 0.3V or below
100ms or below 10ms or longer 0.2V or below
Fig.57 Input pin circuit diagram
Fig.58 Input / output pin circuit diagram
Fig.59 Input pin circuit diagram
tOFF
tR
Vbot
0
VCC
Fig.60 Rise waveform diagram
Technical Note
19/40
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BR24L□□-W Series,BR24S□□□-W Series
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC
as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
tLOW
tSU:DAT
tDH
A
fter Vcc becomes stable
SCL
VCC
SDA
A
fter Vcc becomes stable
tSU:DAT
Fig.61 When SCL= 'H' and SDA= 'L' Fig.62 When SCL='L' and SDA='L'
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
BR24S□□□-W Series
●Description
BR24S□□□-W series is a serial EEPROM of I2C BUS interface method.
●Features
1) Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL)
and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.7～5.5V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.7～5.5V
5) Page write mode useful for initial value write at factory shipment.
6) Highly reliable connection by Au pad and Au wire.
7) Auto erase and auto end function at data rewrite.
8) Low current consumption
At write operation (5V) : 0.5mA (Typ.)
At read operation (5V) : 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
9) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
10) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package
11) Data rewrite up to 1,000,000 times
12) Data kept for 40 years
13) Noise filter built in SCL / SDA terminal
14) Shipment data all address FFh
●Page write
Number of pages 16Byte 32Byte 64Byte
Product number BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
●BR24S series
Capacity Bit
format Type Power source
voltage SOP8 SOP-J8 SSOP-B8 TSSOP-B8 MSOP8 TSSOP-B8J VSON008
X2030
8Kbit 1K×8 BR24S08-W 1.7～5.5V ● ● ● ● ● ● ●
16Kbit 2K×8 BR24S16-W 1.7～5.5V ● ● ● ● ● ● ●
32Kbit 4K×8 BR24S32-W 1.7～5.5V ● ● ● ● ● ● ●
64Kbit 8K×8 BR24S64-W 1.7～5.5V ● ● ● ● ● ●
128Kbit 16K×8 BR24S128-W 1.7～5.5V ● ● ● ●
256Kbit 32K×8 BR24S256-W 1.7～5.5V ● ●
Technical Note
21/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Limits Unit
Impressed voltage VCC -0.3～+6.5 V
Permissible dissipation Pd
450 (SOP8) *1
mW
450 (SOP-J8) *2
300 (SSOP-B8) *3
330 (TSSOP-B8) *4
310 (MSOP8) *5
310 (TSSOP-B8J) *6
300 (VSON008X2030) *7
Storage temperature range Tstg -65～+125 ℃
Action temperature range Topr -40～+85 ℃
Terminal voltage - -0.3～Vcc+1.0 V
*When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,*6) to be reduced per 1℃
●Memory cell characteristics (Ta=25℃, Vcc=1.7～5.5V)
Parameter Limits Unit
Min. Typ. Max.
Number of data rewrite times *1 1,000,000 - - Times
Data hold years *1 40 - - Years
*1 Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage Vcc 1.7～5.5 V
Input voltage VIN 0～Vcc
●Electrical characteristics
(Unless otherwise specified, T=-40～+85℃, Vcc=1.7～5.5V)
Parameter Symbol Limits Unit Condition
Min Typ. Max.
"H" Input Voltage1 VIH1 0.7Vcc - Vcc+1.0 V
"L" Input Voltage1 VIL1 -0.3 - 0.3Vcc V
"L" Output Voltage1 VOL1 - - 0.4 V IOL=3.0mA , 2.5V≦Vcc≦5.5V (SDA)
"L" Output Voltage2 VOL2 - - 0.2 V IOL=0.7mA , 1.7V≦Vcc≦2.5V (SDA)
Input Leakage Current ILI -1 - 1 μA VIN=0～Vcc
Output Leakage Current ILO -1 - 1 μA VOUT=0～Vcc (SDA)
Current consumption
at action
ICC1
- - 2.0
mA
Vcc=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write BR24S08/16/32/64-W
- - 2.5 Vcc=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write BR24S128/256-W
ICC2 - - 0.5 mA
Vcc=5.5V , fSCL =400kHz
Random read, Current read, Sequential read
Standby Current ISB - - 2.0 μA Vcc=5.5V , SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
○Radiation resistance design is not made.
Technical Note
22/40
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BR24L□□-W Series,BR24S□□□-W Series
●Action timing characteristics
(Unless otherwise specified, T=-40～+85℃, Vcc=1.7～5.5V)
Parameter Symbol
Limits Unit
Min. Typ. Max.
SCL Frequency fSCL - - 400 kHz
Data clock "High" time tHIGH 0.6 - - μs
Data clock "Low" time tLOW 1.2 - - μs
SDA, SCL rise time *1 tR - - 0.3 μs
SDA, SCL fall time *1 tF - - 0.3 μs
Start condition hold time tHD:STA 0.6 - - μs
Start condition setup time tSU:STA 0.6 - - μs
Input data hold time tHD:DAT 0 - - ns
Input data setup time tSU:DAT 100 - - ns
Output data delay time tPD 0.1 - 0.9 μs
Output data hold time tDH 0.1 - - μs
Stop condition data setup time tSU:STO 0.6 - - μs
Bus release time before transfer start tBUF 1.2 - - μs
Internal write cycle time tWR - - 5 ms
Noise removal valid period (SDA,SCL terminal) tI - - 0.1 μs
WP hold time tHD:WP 0 - - ns
WP setup time tSU:WP 0.1 - - μs
WP valid time tHIGH:WP 1.0 - - μs
*1 : Not 100% TESTED
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
●Sync data input/output timing
SDA
tSU:STA tSU:STOtHD:STA
START BIT STOP BIT
SCL
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing Fig.1-(b) Start - stop bit timing
SDA
SC
L
D0 ACK
STOP
CONDITION
START
CONDITION
t
WR
WRITE DATA
(
n
)
Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancel
●Block diagram
8
7
6
5 4
3
2
1
SDA
SCL
WP
Vcc
GND
A
2
A
1
A
0
A
dddress
decoder
Slave - word
address register Da ta
register
Control circuit
High voltage
generating circuit Power source
volta
g
e detection
10bit
11 b i t
12bit
13bit
14bit
15bit
8bit
A
CK
STA RT STOP
8Kbit～256Kbit EEPROM array
10bit
11 b i t
12bit
13bit
14bit
15bit
*1
*1
*2
*2
*2
Fig.2 Block diagram
SD
A
(入力)
SDA
(出力)
tHD:STA tHD:DAT
tSU:DAT
tBUF tPD tDH
tLOW
tHIGHtR tF
SCL
(Input)
(Output)
SCL
SDA
WP
ｔHD：WP
ストップコンディション
ｔWR
D1 D0
A
CK
A
CK
DATA(1) DATA(n)
tSU：WP
Stop condition
tHIGH:WP
WP
SDA D1 D0 ACK ACK
DATA(1) DATA(n)
tWR
SCL
tWR
＊2 A0, A1= Don’t use: BR24S08-W
A0, A1, A2= Don’t use: BR24S16-W
＊1 10bit: BR24S08-W
11bit: BR24S16-W
12bit: BR24S32-W
13bit: BR24S64-W
14bit: BR24S128-W
15bit: BR24S256-W
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
●Pin assignment and description
●Characteristic data (The following values are Typ. ones.)
Terminal
name
Input/
Output
Function
BR24S08-W BR24S16-W BR24S32/64/128/256-W
A0 Input Don't use Don't use Slave address setting
A1 Input Don't use Don't use Slave address setting
A2 Input Slave address setting Don't use Slave address setting
GND - Reference voltage of all input / output, 0V.
SDA Input / Output Slave and word address,
Serial data input serial data output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc - Connect the power source.
Vcc
SCL
GND
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
1
2
3
4 5
6
7
8
WP
SDA
A2
A1
A0
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLYVOLTAGE : Vcc[V]
INPUT LEAK CURRENT : I
LI
[uA]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.2
0.4
0.6
0.8
1
0123456
L OUTPUT CURRENT : I
OL
[mA]
L OUTPUT VOLTAGE : V
OL
[V]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLY VOLTAGE : Vcc[V]
OUTPUT LEAK CURRENT : ILO[uA]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc[V]
H INPUT VOLTAGE : V
IH
[V]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0
0.2
0.4
0.6
0.8
1
012345678
L OUTPUT CURRENT : IOL[mA]
L OUTPUT VOLTAGE : VOL[V]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.5 'L' output voltage V
OL
-I
OL
(Vcc=1.7V)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc[V]
L INPUT VOLTAGE : VIL[V]
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.6　'L' output voltage V
OL
-I
OL
(Vcc=2.5V) Fig.7　Input leak current I
LI
(A0,A,A2,SCL,WP)
Fig.8　Output leak current I
LO
(SDA)
SPEC
Fig.4　'L' input voltage V
IL
(A0,A1,A2,SCL,SDA,WP)
Fig.3　'H' input voltage V
IH
(A0,A1,A2,SCL,SDA,WP)
Technical Note
25/40
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BR24L□□-W Series,BR24S□□□-W Series
●Characteristic data (The following values are Typ. ones.)
-200
-100
0
100
200
300
0123456
SUPPLY VOLTAGE : Vcc[V]
INPUT DATA SET UP TIME : t
SU : DAT
[ns]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0
1
2
3
4
0123456
SUPPLY VOLTAGE : Vcc[V]
OUTPUT DATA DELAY TIME : t
PD
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.5
1
1.5
2
2.5
3
3.5
0123456
SUPPLY VOLTAGE : Vcc[V]
CURRENT CONSUMPTION
AT WRITING : Icc1[mA]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.5
1
1.5
2
2.5
0123456
SUPPLY VOLTAGE : Vcc[V]
STANBY CURRENT : I
SB
[uA]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
-0.2
0
0.2
0.4
0.6
0.8
0123456
SUPPLY VOLTAGE : Vcc[V]
START CONDITION
SET UP TIME : tSU:STA[us]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0.1
1
10
100
1000
10000
0123456
SUPPLY VOLTAGE : Vcc[V]
SCL FREQUENCY : fｓｃｌ[ｋHZ]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
-200
-150
-100
-50
0
50
0123456
SUPPLY VOLTAGE : Vcc[V]
INPUT DATA HOLD TIME : t
HD: STA
[ns]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.2
0.4
0.6
0.8
1
0123456
SUPPLY VOLTAGE : Vcc[V]
DATA CLK H TIME : t
HIGH
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0
0.5
1
1.5
2
2.5
0123456
SUPPLY VOLTAGE : Vcc[V]
CURRENT CONSUMPTION
AT WRITING : Icc1[mA]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.9 Current consumption at WRITE operation I
CC
1
(f
SCL
=400kHz BR24S16/32/64-W)
Fig.10　Current consumption at WRITE operation Icc1
(f
SCL
=400kHz BR24S128/256-W)
Fig.12　Stanby operation I
SB
Fig.14 Data clock High Period t
HIGH
0
1
2
3
4
5
0123456
SUPPLY VOLTAGE : Vcc[V]
ＤＡＴＡ CLK L TIME : t
LOW
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.15 Data clock Low Period　t
LOW
0
1
2
3
4
5
0123456
SUPPLY VOLTAGE : Vcc[V]
START CONDITION HOLD TIME : t
HD : STA
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.16 Start Condition Hold Time t
HD : STA
Fig.17　Start Condition Setup Time　t
SU : STA
Fig.18　Input Data Hold Time t
HD : DAT
（HIGH） Fig.19　Input Data Hold Time ｔ
HD : DAT
(LOW） Fig.20　Input Data Setup Time ｔ
SU: DAT
(HIGH)
Fig.21　Input Data setup time t
SU : DAT
(LOW)
0
1
2
3
4
0123456
SUPPLY VOLTAGE : Vcc[V]
OUTPUT DATA DELAY TIME : t
PD
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.22　'L' Data output delay time t
PD
0Fig.23 'H' Data output delay time ｔ
PD
1
-200
-150
-100
-50
0
50
0123456
SUPPLY VOLTAGE : Vcc[V]
INPUT DATA HOLD TIME : t
HD :DAT
[ns]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
-200
-100
0
100
200
300
0123456
SUPPLY VOLTAGE : Vcc[V]
INPUT DATA SET UP TIME : t
SU: DAT
[ns]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Fig.13　SCL frequency f
SCL
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc[V]
CURRENT CONSUMPTION
AT READING : Icc2[mA]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Fig.11 Current consumption at READ operation I
CC
2
(f
SCL
=400kHz)
Technical Note
26/40
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BR24L□□-W Series,BR24S□□□-W Series
●Characteristic data (The following values are Typ. ones.)
0
1
2
3
4
5
0123456
SUPPLY VOLTAGE : Vcc[V]
BUS OPEN TIME
BEFORE TRANSMISSION : t
BUF
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.24 BUS open time before transmission　ｔ
BUF
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc[V]
INTERNAL WRITING
CYCLE TIME : t
WR
[ms]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.25 Internal writing cycle time　ｔ
WR
0
0.2
0.4
0.6
0.8
1
0123456
SUPPLY VOLTAGE : Vcc[V]
NOISE REDUCTION
EFECTIVE TIME : t
l
(SCL H) [us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.26 Noise reduction efection time t
l
（SCL H）
Fig.27　Noise reduction efective time　t
l
（SCL L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc[V]
NOISE REDUCTION
EFECTIVE TIME : t
l
(SCL L)[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.28　Noise resuction efecctive time　ｔ
ｌ
（SDA H）
0
0.1
0.2
0.3
0.4
0.5
0.6
0246
SUPPLY VOLATGE : Vcc[V]
NOISE REDUCTION
EFECTIVE TIME : t
l
(SDA H)[us]
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Fig.29 Noise reduction efective time t
l
（SDA L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc[V]
NOISE REDUCTION
EFFECTIVE TIME : t
l
(SAD L)[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.30 WP setup time t
SU : WP
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0123456
SUPPLY VOLTAGE : Vcc[V]
WP SET UP TIME : t
SU : WP
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.31 WP efective time t
HIGH : WP
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLYVOLTAGE : Vcc[V]
WP EFFECTIVE TIME : t
HIGH : WP
[us]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Technical Note
27/40
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BR24L□□-W Series,BR24S□□□-W Series
Vcc
SCL
GND
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
1
2
3
4 5
6
7
8
WP
SDA
A2
A1
A0
●I2C BUS communication
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH'
is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read
command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus
according to the number of device addresses.
・The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R/W to 0 --- write (setting 0 to word address setting of random read)
Setting R/W to 1 --- read
P0～P2 are page select bits.
Note) Up to 2 units of BR24S08-W, up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Type Slave address
Maximum number of
connected buses
BR24S08-W 1 0 1 0 A2 P1 P0 R/W
―
2
BR24S16-W 1 0 1 0 P2 P1 P0 R/W
―
1
BR24S32-W, BR24S64-W
BR24S128-W, BR24S256-W 1 0 1 0 A2 A1 A0 R/W
―
8
89 89 89
S P
condition condition
ACK STOPACKDATA DATAADDRES
S
START R/W ACK
1-7
SDA
SCL 1-7 1-7
Fig.32 Data transfer timing
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.
Up to 64 arbitrary bytes can be written. (In the case of BR24S128/256-W)
Fig.33 Byte write cycle (BR24S08/16-W)
Fig.34 Byte write cycle (BR24S32/64/128/256-W)
Fig.35 Page write cycle (BR24S08/16-W)
Fig.36 Page write cycle (BR24S32/64/128/256-W)
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 16 bytes (BR24S08-W, BR24S16-W)
: Up to 32 bytes (BR24S32-W, BR24S64-W)
: Up to 64 bytes (BR24S128-W, BR24S256-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment of "Notes on page write cycle" in P24/32.)
・As for page write command of BR24S08-W and, BR24S16-W, after page select bit(PS) of slave address is designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data
up to 16 bytes can be written.
・As for page write cycle of BR24S32-W and BR24S64-W , after the significant 7 bits (in the case of BR24S32-W) of word
address, or the significant 8 bits (in the case of BR24S64-W) of word address are designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
・As for page write cycle of BR24S128-W and BR24S256-W, after the significant 9 bit (in the case of BR24S128-W) of word
address, or the significant 10bit (in the case of BR24S256-W) of word address are designated arbitrarily, by continuing
data input of 64 bytes or more.
Note)
Fig.37 Difference of slave address each type
A1 A2 WA
7 D7
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 WA
0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
A1 A2 WA
14
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
13
WA
12
WA
11
＊ WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st W ORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
14 D0
Note) *1
DATA(n)
D0D7
A
C
K
2nd WORD
ADDRESS(n)
WA
0
WA
13
WA
12
WA
11
＊
*2
*1 As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
*1 As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
*2 As for BR24S128/256-W becomes (n+63).
10 0
1A0
A1
A2
*1 *2 *3 *1 In BR24S16-W, A2 becomes P2
*2 In BR24S08/16-W, A1 becomes P1
*3 In BR24S08/16-W, A0 becomes P0
W
R
I
T
E
S
T
A
R
T
R
/
W
C
K
S
T
O
P
WORD
ADDRESS(n) DAT
A
(n)
SDA
LINE
C
K
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
7 D0 D7 D0
WA
0
注) *1
*2
Note)
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
○Notes on write cycle continuous input
○Notes on page write cycle
List of numbers of page write
Number of pages 16Byte 32Byte 64Byte
Product number BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
In the case of BR24S256-W, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte = 320ms(Max.).
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS（ｎ） DATA(n)
SDA
LINE
A
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
10 0 1P0 P1 P2 WA
7 D0 D7 D0
A
C
K
WA
0 1 100
Next command
tWR(maximum：5ms)
Command is not accepted for this
period.
At STOP (stop bit)
write starts.
S
T
A
R
T
note)
Fig.38 Page write cycle(BR24S08/16-W)
Fig.39 Page write cycle(BR24S32/64/128/256-W)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st W ORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
14 D0
*1
DATA(n)
D0 D7
A
C
K
2nd WORD
ADDRESS(n)
WA
0
WA
13
WA
12
WA
11
＊
*2
1 0 1 0
Next command
tWR(maximum : 5ms)
Command is not accepted for
this period.
At STOP (stop bit)
write starts.
S
T
A
R
T
note)
*1 As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
*2 As for BR24S128/256-W becomes (n+63).
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
○Internal address increment
Page write mode (in the case of BR24S16-W)
For example, when it is started from address 0Eh, therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･, which please note.
* 0Eh･･･16 in hexadecimal, therefore, 00001110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of
all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
0Eh
---------
---------
Significant bit is fixed.
No digit up
WA7 ----- WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0
0 ----- 0 0 0 0 1
0 ----- 0 0 0 1 0
0 ----- 0 1 1 1 0
0 ----- 0 1 1 1 1
0 ----- 0 0 0 0 0
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BR24L□□-W Series,BR24S□□□-W Series
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
Fig.44 Difference of slave address of each type
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 WA
7 A0 D0
SLAVE
ADDRESS
10 0
1A1 A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
Note)
Fig.40 Random read cycle (BR24S08/16-W)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS（ｎ）
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1
A2 WA
14 D7 D0
2nd WORD
ADDRESS（ｎ）
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
100
1A2A1
R
/
W
R
E
A
D
A0
WA
0
Note) *1
WA
13
WA
12
WA
11
＊
Fig.41 Random read cycle (BR24S32/64/128/256-W)
Fig.42 Current read cycle
S
T
A
R
T
S
T
O
P
SDA
LINE
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 D0 D7
R
/
W
R
E
A
D
Note)
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
10 0
1A0
A1
A2 D0 D7 D0 D7
Note）
Fig.43 Sequential read cycle (in the case of current read cycle)
It is necessary to input 'H'
to the last ACK.
*1 As for WA12, BR24S32-W become Don't care.
As for WA13, BR24S32/64-W become Don't care.
As for WA14, BR24S32/64/128-W become Don't care.
It is necessary to input 'H'
to the last ACK.
10 0
1A0
A1
A2
*1 *2 *3 *1 BR24S16-W A2 becomes P2.
*2 BR24S08/16-W A1 becomes P1.
*3 BR24S08/16-W A0 becomes P0.
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BR24L□□-W Series,BR24S□□□-W Series
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.45(a), Fig.45(b), Fig.45(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may
be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data so forth.
Fi
g
.45-
(
b
)
The case of START+9 Dumm
y
clock + START + command in
p
ut
SCL 2
1 8 9
Dummy clock×9 Start
Start
Normal command
Normal command
SDA
Slave
address
Word
address
…
…
S
T
A
R
T
First write command
A
C
K
H
A
C
K
L
Slave
address
Slave
address
Slave
address Data
Write command
During internal write,
ACK = HIGH is sent back.
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
tWR
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
Fig.46 Case to continuously write by acknowledge polling
Normal command
1 2 13
14
SCL Normal command
Dummy clock×14 Start×2
* Start command from START input.
Fig.45-(c) START × 9 + command input
SDA
Start×9
SCL 1 2 3 8 9 7
SDA
Normal command
Normal command
Fig.45-(a) The case of 14 Dummy clock + START + START+ command input
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BR24L□□-W Series,BR24S□□□-W Series
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After
execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 48.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
Fig.48 Case of cancel by start, stop condition during slave address input
Fig.47 WP valid timing
・Rise of D0 taken clock
SCL
D0 ACK
Enlarged view
SCL
SDA
Enlarged view
ACK
D0
・Rise of SDA
SDA
WP
WP cancel invalid area
WP cancel valid area Write forced end
Data is not written. Data not guaranteed
Slave
address D7 D6 D5 D4 D3 D2 D1 D0 Data
tWR
SDA D1
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
Word
address
SCL
SDA 1 1
0 0
Start condition
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BR24L□□-W Series,BR24S□□□-W Series
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential○
A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2Vcc.
Vcc - ILRPU - 0.2Vcc ≧ V
IH
∴ RPU ≦ 0.8VCC - VIH
IL
Ex.) When Vcc = 3V, IL=10μA, VIH = 0.7Vcc
from(2)
RPU ≦ 0.8×3 - 0.7×3
10×10-6
≦
300 ［kΩ］
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V
and IOLMAX=3mA.
VCC - VOL ≦IOL
RPU
∴ RPU ≧ VCC - VOL
IOL
(2)VOLMAX =0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX ≦ V
IL-0.1 Vcc
Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from(1),
RPU ≧ 3－0.4
3×10
≧ 867 ［Ω］
And
VOL=0.4［V］
V
IL=0.3×3
=0.9［V］
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins(Don't use PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with Don't use PIN BR24S08F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1
BR24S16F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1, A2
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
Bus line
capacity
CBUS
Fig.49 I/O circuit diagram
BR24SXX
Microcontroller
Technical Note
35/40
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BR24L□□-W Series,BR24S□□□-W Series
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential○
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
(VCC－VOL)×RS +VOL+0.1VCC≦VIL
RPU+RS
∴RS≦VIL－VOL－0.1VCC × RPU
1.1VCC－VIL
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ
from(2), RS≦0.3×3－0.4－0.1×3 × 20×103
1.1×3－0.3×3
≦1.67［kΩ］
VCC ≦I
RS
∴RS ≧VCC
I
Example）When VCC=3V, I=10mA
RS ≧ 3
10×10-3
RPU
Microcontre
RS
EEPROM
Fig.51 Input/output collision timing
RPU
Microcontroller
RS
EEPROM
IOL
A
Bus line
capacity CBUS
VOL
VCC
VIL
Fig.52 I/O circuit diagram
Microcontroller EEPROM
'L' output
R
S
R
PU
'H' output
Over currentⅠ
Fig.53 I/O circuit diagram
Fig.50 I/O circuit diagram
A
CK
'L' output of EEPROM
'H' output of microcontroller
Over current flows to SDA line by 'H' output of
microcontroller and 'L' output of EEPROM.
SCL
SDA
Technical Note
36/40
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)
○Input/Output (SDA)
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P26).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
Recommended conditions of tR,tOFF,Vbot
tR tOFF Vbot
10ms or below 10ms or longer 0.3V or below
100ms or below 10ms or longer 0.2V or below
Fig.54 Input pin circuit diagram
Fig.55 Input /output pin circuit diagram
tOFF
tR
Vbot
0
VCC
Fig.56 Rise waveform diagram
tLOW
tSU:DATtDH
After Vcc becomes stable
SCL
VCC
SDA
Fig.57 When SCL='H' and SDA='L'
tSU:DAT
After Vcc becomes stable
Fig.58 When SCL='H' and SDA='L'
Technical Note
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BR24L□□-W Series,BR24S□□□-W Series
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC
as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Technical Note
38/40
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BR24L□□-W Series,BR24S□□□-W Series
●Ordering part number
B R 2 4 S 2 5 6 F - W E 2
Part No.
BUS type
24：I2C
Operating
temperature/
Power source
voltage
L: -40℃~+85℃/
1.8V ~ 5.5V
S: -40℃~+85℃/
1.7V ~ 5.5V
Capacity
01=1K 16=16K
02=2K 32=32K
04=4K 64=64K
08=8K 128=128K
256=256K
Package
F : SOP8
FJ : SOP-J8
FV : SSOP-B8
FVM : MSOP8
FVT :TSSOP-B8
FVJ :TSSOP-B8J
NUX :
VSON008X2030
Double cell Packaging and
forming specification
E2: Embossed tape and reel
TR: Embossed tape and reel
●Package specifications
(Unit : mm)
SOP8
0.9±0.15
0.3MIN
4
°
+
6
°
−
4
°
0.17 +0.1
-
0.05
0.595
6
43
8
2
5
1
7
5.0±0.2
6.2±0.3
4.4±0.2
(MAX 5.35 include BURR)
1.27
0.11
0.42±0.1
1.5±0.1
S
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
(Unit : mm)
SOP-J8
4°+6°
−4°
0.2±0.1
0.45MIN
234
5678
1
4.9±0.2
0.545
3.9±0.2
6.0±0.3
(MAX 5.25 include BURR)
0.42±0.1
1.27
0.175
1.375±0.1
0.1 S
S
Technical Note
39/40
www.rohm.com 2009.09 - Rev.D
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
(Unit : mm)
TSSOP-B8
0.08 S
0.08
M
4 ± 4
234
8765
1
1.0±0.05
1PIN MARK
0.525
0.245+0.05
–0.04
0.65
0.145+0.05
–0.03
0.1±0.05
1.2MAX
3.0±0.1
4.4±0.1
6.4±0.2
0.5±0.15
1.0±0.2
(MAX 3.35 include BURR)
S
Direction of feed
Reel ∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
3000pcs
E2
()
1pin
(Unit : mm)
TSSOP-B8J
0.08
M
0.08 S
S
4 ± 4
(MAX 3.35 include BURR)
578
1234
6
3.0±0.1
1PIN MARK
0.95±0.2
0.65
4.9±0.2
3.0±0.1
0.45±0.15
0.85±0.05
0.145
0.1±0.05
0.32
0.525
1.1MAX
+0.05
–0.03
+0.05
–0.04
Direction of feed
Reel
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
1pin
(Unit : mm)
SSOP-B8
0.08
M
1234
5678
0.1
+0.06
-
0.04
0.22
0.3MIN
0.65
(0.52)
3.0±0.2
0.15±0.1
6.4±0.3
1.15±0.1 4.4±0.2
(MAX 3.35 include BURR)
S
0.1
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
Technical Note
40/40
www.rohm.com 2009.09 - Rev.D
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
(Unit : mm)
MSOP8
0.08 S
S
4.0±0.2
8
3
2.8±0.1
1
6
2.9±0.1
0.475
4
57
(MAX 3.25 include BURR)
2
1PIN MARK
0.9MAX
0.75±0.05
0.65
0.08±0.05
0.22 +0.05
–0.04
0.6±0.2
0.29±0.15
0.145 +0.05
–0.03
4°
+6°
−4°
Direction of feed
Reel
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
3000pcs
TR
()
1pin
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
4000pcs
TR
()
Direction of feed
Reel 1pin
(Unit : mm)
VSON008X2030
5
1
8
4
1.4±0.1
0.25
1.5±0.1
0.5
0.3±0.1
0.25 +0.05
–0.04
C0.25
0.6MAX
(0.12)
0.02+0.03
–0.02 3.0±0.1
2.0±0.1
1PIN MARK
0.08 S
S
R0039
A
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which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
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However, should you incur any damage arising from any inaccuracy or misprint of such
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