Serial EEPROM Series High Reliability Series EEPROMs I2C BUS BR24L-W Series,BR24S-W Series No.09001EDT04 ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold wires are used for internal connections, pushing the boundaries of reliability to the limit. BR24L-W Series assort 1Kbit64Kbit. BR24S-W Series are possible to operate at high speed in low voltage and assort 8Kbit256Kbit. Contents BR24L-W Series BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W P2 BR24S-W Series BR24S08-W, BR24S16-W, BR24S32-W, BR24S64-W, BR24S128-W, BR24S256-W P20 www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 1/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Serial EEPROM Series High Reliability Series EEPROMs I2C BUS BR24L-W Series Description 2 BR24L-W series is a serial EEPROM of I C BUS interface method. Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA) 2) Other devices than EEPROM can be connected to the same port, saving microcontroller port *1 3) 1.8V~5.5V single power source action most suitable for battery use 4) Page write mode useful for initial value write at factory shipment 5) Highly reliable connection by Au pad and Au wire 6) Auto erase and auto end function at data rewrite 7) Low current consumption *2 At write operation (5V) : 1.2mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) 8) Write mistake prevention function Write (write protect) function added 9) Write mistake prevention function at low voltage 10) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package *3 11) Data rewrite up to 1,000,000 times 12) Data kept for 40 years 13) Noise filter built in SCL / SDA terminal 14) Shipment data all address FFh *1 BR24L02-W, BR24L16-W, BR24L32-W : 1.75.5V *2 BR24L32-W, BR24L64-W : 1.5mA *3 Refer to following list Page write Number of Pages Product number 8Byte 16Byte 32Byte BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W BR24L series Capacity Bit format Type Power source Voltage SOP8 SOP-J8 1Kbit 128x8 BR24L01A-W 1.85.5V 2Kbit 256x8 BR24L02-W 1.75.5V 4Kbit 512x8 BR24L04-W 1.85.5V MSOP8 TSSOP-B8J VSON008 X2030 SSOP-B8 TSSOP-B8 8Kbit 1Kx8 BR24L08-W 1.85.5V 16Kbit 2Kx8 BR24L16-W 1.75.5V 32Kbit 4Kx8 BR24L32-W 1.75.5V 64Kbit 8Kx8 BR24L64-W 1.85.5V www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 2/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Absolute maximum ratings (Ta=25) Parameter Impressed voltage symbol VCC Permissible dissipation Limits -0.3+6.5 *1 450 (SOP8) 450 (SOP-J8) *2 300 (SSOP-B8) *3 330 (TSSOP-B8) *4 310 (MSOP8) *5 310 (TSSOP-B8J) *6 300 (VSON008X2030) *7 -65+125 -40+85 -0.3Vcc+1.0 Pd Storage temperature range Action temperature range Terminal voltage Tstg Topr - Unit V mW V When using at Ta=25 or higher, 4.5mW(*1,*2), 3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,*6) to be reduced per 1 Memory cell characteristics (Ta=25, Vcc=1.85.5V)*1 Limits Parameter Min. Typ. Number of data rewrite times *2 1,000,000 Data hold years *2 40 - Max. - Unit Times Years Shipment data all address FFh *1 BR24L02/16/32-W : 1.7~5.5V *2 Not 100% TESTED Recommended operating conditions Parameter Power source voltage Input voltage Symbol Vcc VIN Limits 1.85.5 *1 0Vcc Unit V *1 BR24L02/16/32-W : 1.7~5.5V Electrical characteristics (Unless otherwise specified, Ta=-40+85, VCC=1.85.5V) *1 Limits Parameter Symbol Unit Min. Typ. Max. "HIGH" input voltage 1 VIH1 "LOW" input voltage 1 VIL1 0.7Vcc -0.3 *2 - Vcc +1.0 *2 V 2.5Vcc5.5V - 0.3 Vcc V 2.5Vcc5.5V *2 "HIGH" input voltage 2 VIH2 0.8Vcc - Vcc +1.0 V 1.8Vcc2.5V "LOW" input voltage 2 VIL2 -0.3 *2 - 0.2 Vcc V 1.8Vcc2.5V "HIGH" input voltage 3 *3 VIH3 0.8Vcc - Vcc +1.0 V 1.7Vcc1.8V "HIGH" input voltage 3 *4 Conditions VIH3 0.9Vcc - Vcc +1.0 V 1.7Vcc1.8V "LOW" input voltage 3 *2 VIL3 -0.3 - 0.1 Vcc V 1.7Vcc1.8V "LOW" output voltage 1 VOL1 - - 0.4 V IOL=3.0mA, 2.5VVcc5.5V, (SDA) "LOW" output voltage 2 VOL2 - - 0.2 V IOL=0.7mA, 1.7VVcc2.5V, (SDA) Input leak current ILI -1 - 1 A VIN=0VVcc Output leak current ILO -1 - A VOUT=0VVcc, (SDA) mA Vcc=5.5V,fSCL=400kHz, tWR=5ms, Byte write, Page write Current consumption at action Standby current 1 2.0 *5 ICC1 - - ICC2 - - 0.5 mA ISB - - 2.0 A 3.0 *6 Vcc=5.5V,fSCL=400kHz Random read, current read,sequential read Vcc=5.5V, SDASCL=Vcc A0, A1, A2=GND, WP=GND Radiation resistance design is not made. *1 BR24L02/16/32-W : 1.75.5V, *2 BR24L16/32-W, *3 BR24L02/16-W, *4 BR24L32-W *5 BR24L01A/02/04/08/16-W, *6 BR24L32/64-W www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 3/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Action timing characteristics (Unless otherwise specified, Ta=-40+85, VCC=1.85.5V)*1 FAST-MODE STANDARD-MODE 2.5VVcc5.5V 1.8VVcc5.5V Parameter Symbol Unit Min. Typ. Max. Min. Typ. Max. SCL frequency fSCL - - 400 - - 100 Data clock "HIGH" time tHIGH 0.6 - - 4.0 - - s Data clock "LOW" time tLOW 1.2 - - 4.7 - - s SDA, SCL rise time *2 tR - - 0.3 - - 1.0 s SDA, SCL fall time *2 kHz tF - - 0.3 - - 0.3 s tHD:STA 0.6 - - 4.0 - - s Start condition setup time tSU:STA 0.6 - - 4.7 - - s Input data hold time tHD:DAT 0 - - 0 - - ns Input data setup time tSU:DAT 100 - - 250 - - ns Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 s Output data hold time tDH 0.1 - - 0.2 - - s Start condition hold time Stop condition setup time tSU:STO 0.6 - - 4.7 - - s Bus release time before transfer start tBUF 1.2 - - 4.7 - - s Internal write cycle time tWR - - 5 - - 5 ms Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 s WP hold time tHD:WP 0 - - 0 - - ns WP setup time tSU:WP tHIGH:W P 0.1 - - 0.1 - - s 1.0 - -- 1.0 - - s WP valid time *1 BR24L02/16/32-W : 1.75.5V *2 Not 100% tested FAST-MODE and STANDARD-MODE FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out, therefore, at Vcc=2.5V5.5V , 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 4/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Sync data input / output timing tR tF tHIGH SCL SCL tSU:DAT tHD:STA tLOW tHD:DAT tSU:STA SDA () (input) tHD:STA tSU:STO SDA tPD tBUF tDH SDA START BIT () (output) STOP BIT Input read at the rise edge of SCL Data output in sync with the fall of SCL Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing SCL DATA(1) SCL SDA SDA D0 D1 D0 Stop condition Stop condition WP W R (n-th address) ACK WR ACK Write data DATA(n) ACK Start condition tSUWP Fig.1-(c) Write cycle timing HDWP Fig.1-(d) WP timing at write execution SCL DATA(n) DATA(1) SDA D1 D0 ACK ACK tHIGH:WP tWR WP At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP="LOW". By setting WP "HIGH" in the area, write can be cancelled. When it is set WP="HIGH" during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Fig.1-(e) WP timing at write cance www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 5/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Block diagram *2 A0 1Kbit~64Kbit EEPROM array 1 8 Vcc 7 WP 6 SCL 5 SDA *1 7bit 11bit 8bit 12bit 9bit 13bit 10bit *2 *2 A1 2 A2 3 8bit Address decoder *1 7bit 11bit 8bit 12bit 9bit 13bit 10bit Data register Slave - word address register START STOP Control circuit ACK GND High voltage generating circuit 4 1 Power source voltage detection 7bit : BR24L01A-W 10bit : BR24L08-W 8bit : BR24L02-W 11bit : BR24L16-W 9bit : BR24L04-W 12bit : BR24L32-W 13bit : BR24L64-W 2 A0=N.C. A0, A1=N.C. A0, A1= N.C. A2=Don't Use : BR24L04-W : BR24L08-W : BR24L16-W Fig.2 Block diagram Pin assignment and description A0 Terminal name A0 A1 A2 GND SDA SCL WP Vcc Input / output Input Input Input Input / output Input Input - 1 1 A1 2 A2 3 GND 4 1 1 1 BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W 8 Vcc 7 1 WP 6 SCL 5 SDA 1 1 1 Function BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W Slave address setting Not connected Slave address setting Not connected Slave address setting Not used Reference voltage of all input / output, 0V www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. BR24L32-W BR24L64-W Slave address setting Slave address setting Slave address setting Slave and word address, Serial data input serial data output Serial clock input Write protect terminal Connect the power source. 6/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series 6 5 5 4 4 SPEC 3 2 Ta=85 Ta=-40 Ta=25 1 1 0.8 Ta=85 Ta=-40 Ta=25 3 VOL1[V] 6 VIL1,2[V] VIH1,2[V] Characteristic data (The following values are Typ. ones.) 2 SPEC 1 2 3 4 5 Vcc[V] Fig.3 H input voltage VIH1,2 Ta=25 SPEC Ta=-40 0 0 0 6 0 1 0 3 4 5 6 IOL1[mA] Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V) 2 3 4 5 6 Vcc[V] Fig.4 L input voltageVIL1,2 (SCL,SDA,WP) 1 1.2 0.8 1 1 0.8 0.8 1 0.4 SPEC SPEC ILO[A] ILI[A] VOL2[V] Ta=25 Ta=85 0.6 0.4 0.2 0 0 1 2 3 4 IOL2[mA] 5 1 2 3 Vcc[V] 4 5 0 6 Fig.7 Input leak current ILI (SCL,WP) 3 SPEC fSCL=400kHz DATA=AAh 1 2 1.5 3 4 5 6 Vcc[V] Fig.9 Current consumption at WRITE action ICC1 (fscl=400kHz) 0.1 1 2 3 Vcc[V] 4 5 6 1 2 3 4 5 6 Vcc[V] Fig.11 Current consumption at READ action ICC2 (fSCL=400kHz) 3.5 0.6 [BR24L32/64 series] [BR24L01/02/04/08/16 series] SPEC 3 fSCL=100kHz DATA=AAh SPEC fSCL=100kHz DATA=AAh 2.5 ICC1[mA] 1.5 1 Ta=25 Ta=85 Ta=-40 0.5 0.5 SPEC ICC2[mA] 2 2 1.5 1 0.4 0.3 1 2 3 Vcc[V] 4 5 6 2.5 Ta=85 0.2 0.1 Ta=-40 0 0 0 1 2 3 Vcc[V] 4 5 0 1 2 3 4 5 6 Vcc[V] Fig.14 Current consumption at READ action ICC2 (fSCL=100kHz) 6 Fig.13 Current consumption at WRITE action ICC1 (fSCL=100kHz) Fig.12 Current consumption at WRITE action ICC1 (fSCL=100kHz) fSCL=100kHz DATA=AAh Ta=25 Ta=25 Ta=85 Ta=-40 0.5 0 0 Ta=-40 0 Fig.10 Current consumption at WRITE action ICC1 (fSCL=400kHz) 2.5 Ta=25 0.2 0 0 2 5 10000 SPEC2 SPEC 1.5 1 100 Ta=-40 2 3 Vcc[V] SPEC2 4 5 0 1 Fig.15 Standby current ISB 2 4 5 0 6 SPEC2 SPEC1 3 2 Ta=85 Ta=25 Ta=-40 1 SPEC1 0 1 2 3 4 5 Vcc[V] Fig.18 Data clock "L" time tLOW 6 www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 3 Vcc[V] 4 5 6 4 3 2 Ta=-40 Ta=25 Ta=85 1 0 0 2 SPEC2 5 tSU:STA[s] tHD:STA[s] 2 1 Fig.17 Data clock "H" time tHIGH 4 3 SPEC1 6 SPEC2 4 tLOW[s] 3 Vcc[V] 5 Ta=85 Ta=25 Ta=-40 Ta=-40 Ta=25 Ta=85 Fig.16 SCL frequency fSCL 5 1 2 0 1 6 3 1 Ta=25 0 1 SPEC1 10 Ta=85 0 Ta=85 Ta=25 Ta=-40 tHIGH [s] 4 1000 fSCL[kHz] ISB[A] 2 0.5 6 Ta=85 0.3 0 1 5 fSCL=400kHz DATA=AAh 0.4 Ta=25 Ta=85 Ta=-40 0.5 0 4 SPEC 0.5 SPEC 1 Ta=25 Ta=85 Ta=-40 0 3 Vcc[V] Fig.8 Output leak current ILO(SDA) ICC2[mA] ICC1[mA] 2.5 1.5 0.5 2 [BR24L32/64 series] [BR24L01/02/04/08/16 series] fSCL=400kHz DATA=AAh 1 0.6 3.5 2 Ta=85 Ta=25 Ta=-40 0.2 0 0 Fig.6 L output voltage VOL2-IOL2 (VCC=1.8V) ICC1[mA] 0.4 0 6 2.5 ICC1[mA] 0.6 Ta=85 Ta=25 Ta=-40 0.2 Ta=-40 2 1.2 SPEC 0.6 Ta=85 0.4 0.2 1 0 0.6 SPEC1 0 0 1 2 3 Vcc[V] 4 5 Fig.19 Start condition hold time tHD:STA 7/40 6 0 1 2 3 Vcc[V] 4 5 6 Fig.20 Start condition setup time tSU:STA 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Characteristic data (The following values are Typ. ones). 300 50 50 SPEC1,2 -50 -100 -50 Ta=85 Ta=25 -100 -150 -150 -200 1 2 3 Vcc[V] 4 5 6 SPEC1 100 0 -200 0 3 4 5 6 Vcc[V] Fig.22 Input data hold time tHD:DAT(LOW) Fig.21 Input data hold time tHD:DAT(HIGH) 300 1 2 0 2 Ta=85 Ta=25 Ta=-40 SPEC1 1 Ta=-40 -100 Ta=-40 Ta=25 Ta=85 2 3 Vcc[V] 4 5 6 Fig.24 Input data setup time tSU:DAT(LOW) 3 Vcc[V] 4 5 0 6 1 Fig.25 Output data delay time tPD0 2 3 Vcc[V] 4 5 6 Fig.26 Output data delay time tPD1 0.6 SPEC1,2 SPEC2 5 0.5 Ta=25 4 2 Ta=-40 Ta=25 Ta=85 1 Ta=-40 3 tI(SCL H)[s] 3 tWR[ms] tBUF[s] 2 6 4 Ta=85 2 SPEC1 1 0 1 2 3 Vcc[V] 4 5 Fig.27 Bus release time before transfer start tBUF 0.3 Ta=85 0.2 SPEC1,2 1 2 3 Vcc[V] 4 5 6 0 Fig.28 Internal write cycle time tWR 0.5 0.5 0.3 Ta=-40 0.2 Ta=25 Ta=25 tI(SDA L)[s] 0.6 0.5 tI(SDA H)[s] 0.6 0.4 1 Ta=-40 0.3 Ta=85 0.2 0.1 3 Vcc[V] 4 5 6 0.4 Ta=-40 0.3 Ta=25 Ta=85 0.2 SPEC1,2 Ta=85 2 Fig.29 Noise removal valid time tI(SCL H) 0.6 0.4 Ta=-40 Ta=25 0 0 6 0.4 0.1 0 0 tI(SCL L)[s] 1 SPEC1 SPEC1 0 0 5 6 SPEC2 0 1 5 1 SPEC1 0 4 2 SPEC2 Ta=25 -200 3 Vcc[V] SPEC2 3 tPD1[s] tPD0[s] Ta=85 0 SPEC2 3 100 2 4 SPEC2 SPEC1 1 Fig.23 Input data setup time tSU:DAT(HIGH) 4 200 Ta=85 Ta=25 Ta=-40 -100 Ta=-40 -200 0 tSU:DAT(LOW)[ns] tSU:DAT(HIGH)[ns] Ta=-40 Ta=25 Ta=85 SPEC2 200 0 0 tHD:DAT(LOW)[ns] tHD:DAT(HIGH)[ns] SPEC1,2 SPEC1 0.1 0.1 SPEC1 0 0 0 1 2 3 Vcc[V] 4 5 6 0 0 Fig.30 Noise removal valid time tI(SCL L) 1 2 3 Vcc[V] 4 5 6 Fig.31 Noise removal valid time tI(SDA H) 0 1 2 3 4 5 6 Vcc[V] Fig.32 Noise removal valid time tI(SDA L) 1.2 0.2 1 SPEC1,2 SPEC1,2 tHIGH:WP[s] tSU:WP[s] 0 -0.2 Ta=85 -0.4 Ta=25 0.8 0.6 0.4 Ta=-40 Ta=25 Ta=85 0.2 Ta=-40 -0.6 0 0 1 2 3 Vcc[V] 4 5 Fig.33 WP setup time tSU:WP www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 6 0 1 2 3 Vcc[V] 4 5 6 Fig.34 WP valid time tHIGH:WP 8/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series I2C BUS communication 2 I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, 2 and acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by address peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver". SDA 1-7 SCL S START ADDRESS condition 8 9 R/W ACK 1-7 8 DATA 9 ACK 1-7 8 DATA 9 ACK P STOP condition Fig.35 Data transfer timing Start condition (Start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. Stop condition (stop bit recongnition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop cindition (stop bit), and ends read action. And this IC gets in status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R / W to 0 ------- write (setting 0 to word address setting of random read) Setting R / W to 1 ------- read Type BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W Maximum number of connected buses Slave address 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 A2 A1 A0 A2 A1 A0 A2 A1 PS A2 P1 P0 P2 P1 P0 A2 A1 A0 A2 A1 A0 8 R/W 8 4 2 1 8 8 R/W R/W R/W R/W R/W R/W PS, P0P2 are page select bits. Note) Up to 4 units BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected. Device address is set by 'H' and 'L' of each pin of A0, A1, and A2. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 9/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W) S T A R T W R I T E SLAVE ADDRESS SDA LINE WORD ADDRESS WA 7 1 0 1 0 A2 A1 A0 Note) S T O P DATA *1 As for WA7, BR24L01A-W becomes Don't care. WA 0 D7 D0 A C K R A *1 / C W K A C K Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W) S T A R T SLAVE ADDRESS SDA LINE W R I T E 1 0 1 0 A2 A1 A0 Note) 2nd WORD ADDRESS 1st WORD ADDRESS * * * WAWA 12 11 R A / C W K WA 0 *1 As for WA12, BR24L32-W becomes Don't care. D0 D7 A C K A C K *1 S T O P DATA A C K Fig.37 Byte write cycle (BR24L32/64-W) S T A R T SDA L IN E W R I T E SLAVE ADDRESS W ORD A D D R E S S (n ) WA 7 1 0 1 0 A 2A 1A 0 WA 0 R A / C *1 W K N o te ) D A TA (n ) D A TA (n +1 5 ) D7 D0 A C K S T O P *2 *1 As for WA7, BR24L01A-W becomes Don't care. *2 As for BR24L01A/02-W becomes (n+7). D0 A C K A C K Fig.38 Page write cycle (BR24L01A/02/04/08/16-W) S T A R T SDA L IN E SLAVE ADDRESS W R I T E 1 0 1 0 A 2A 1A 0 N ote ) 1 st W O R D A D D R E S S (n ) * R A / C W K * * 2nd W ORD A D D R E S S (n ) 1 2 11 *1 D A T A (n ) WA 0 WA WA A C K D7 A C K S T O P D A TA (n + 3 1 ) D0 *1 As for WA12, BR24L32-W becomes Don't care. D0 A C K A C K Fig.39 Page write cycle (BR24L32/64-W) Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W) : Up to 16bytes (BR24L04-W, BR24L08-W,BR24L16-W) : Up to 32bytes (BR24L32-W, BR24L64-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.) As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W, after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written. As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. Note) *1 *2 *3 1 0 1 0 A 2A 1A 0 *1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0. Fig.40 Difference of slave address of each type www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 10/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Notes on write cycle continuous input At STOP (stop bit), write starts. S T A R T SDA LINE W R I T E SLAVE ADDRESS *1 WA 7 1 0 1 0 A2A1A0 Note) WORD ADDRESS WA 0 R A / C W K *2 DATA(n) D7 DATA(n+7)*3 D0 A C K S T A R T S T O P D0 A C K 1 0 1 0 A C K Next command tWR(maximum : 5ms) Command is not accepted for this period. *1 BR24L01A-W becomes Don't care. *2 BR24L04-W, BR24L08-W, and BR24L16-W become (n+15). *3 BR24L32-W and BR24L64-W become (n+31). Fig.41 Page write cycle Note) *1 *2 *3 1 0 1 0 A 2A 1A 0 *1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and in BR24L16-W, A0 becomes P0. Fig.42 Difference of each type of slave address Notes on page write cycle List of numbers of page write Number of Pages 8Byte Product number BR24L01A-W BR24L02-W 16Byte BR24L04-W BR24L08-W BR24L16-W 32Byte BR24L32-W BR24L64-W The above numbers are maximum bytes for respective types. Any bytes below these can be written. In the case BR24L02-W, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. It does not stand 5ms at maximum x 8byte=40ms(Max.). www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 11/40 2009.09 - Rev.D BR24L-W Series,BR24S-W Series Technical Note Internal address increment Page write mode (in the case of BR24L02-W) WA7 ----0 ----0 ----0 ----- WA4 0 0 0 ------------- 0 0 0 WA1 0 0 1 WA0 0 1 0 Increment --------- 0 0 0 WA2 0 0 0 --------- --------- 06h WA3 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up For example, when it is started from address 06h,therefore, increment is made as below, 06h 07h 00h 01h ---, which please note. 06h06 in hexadecimal, therefore, 00000110 becomes a binary number. Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 12/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession. S T A R T W R I T E SLAVE ADDRESS SDA L IN E S T A R T W ORD A D D R E S S (n ) WA 7 1 0 1 0 A 2 A 1A 0 WA 0 R A *1 / C W K N o te ) R E A D SLAVE ADDRESS D A TA (n ) 1 0 1 0 A 2 A 1A 0 A C K It is necessary to input 'H' to the last ACK. S T O P D0 D7 A C K R A / C W K *1 As for WA7, BR24L01A-W become Don't care. Fig.43 Random read cycle (BR24L01A/02/04/08/16-W) S T A R T SDA LINE SLAVE ADDRESS W R I T E * * * WA 0 WAWA 12 11 R A / C W K Note) 2nd WORD ADDRESS 1st WORD ADDRESS 1 0 1 0 A2A1A0 S T A R T A C K *1 R E A D SLAVE ADDRESS 1 0 1 0 A2 A1A0 A C K S T O P DATA(n) D7 D0 R A / C W K A C K *1 As for WA12, BR24L32-W become Don't care. Fig.44 Random read cycle (BR24L32/64 -W) S T A R T SDA L IN E R E A D S LA V E ADDRESS S T O P D A TA (n ) 1 0 1 0 A 2 A 1A 0 D7 D0 A C K R A / C W K N o te) It is necessary to input 'H' to the last ACK. Fig.45 Current read cycle S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2 A1A0 Note D7 S T O P DATA(n+x) DATA(n) D0 R A / C W K D7 A C K D0 A C K A C K Fig.46 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' . When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. Note) *1 *2 *3 1 0 1 0 A 2A 1A 0 *1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0. Fig.47 Difference of slave address of each type www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 13/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48(a), Fig.48(b), and Fig.48(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clockx14 1 SCL 2 Startx2 13 Normal command 14 SDA Normal command Fig.48-(a) The case of dummy clock +START+START+ command input Dummy clockx9 Start 1 SCL 2 Start 8 9 Normal command SDA Normal command Fig.48-(b) The case of START +9 dummy clocks +START+ command input Startx9 SCL 2 1 7 3 8 9 Normal command SDA Normal command * Start command from START input. Fig.48-(c) STARTx9+ command input Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data output and so forth. During internal write, ACK = HIGH is sent back. First write command S T A R T Write command S T O P S T Slave A R address T S T Slave A R address T A C K H A C K H tWR Second write command ... S T Slave A R address T A C K H S T Slave A R address T A C Word K address L A C K L Data A C K L S T O P tWR After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession. Fig.49 Case to continuously write by acknowledge polling www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 14/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.50.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum). Rise of D0 taken clock SCL SCL Rise of SDA SDA D1 D0 ACK ACK D0 Enlarged view SDA Enlarged view SDA S T Slave A address R T A C Word K address L A C D7 D6 D5 D4 D3 D2 D1 D0 K L WP cancel invalid area A C K L Data A C K L S T O P tWR WP cancel valid area Write forced end Data is not written. Data not guaranteed WP Fig.50 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 51) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Fig.51 Case of cancel by start, stop condition during slave address input www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 15/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A to be determined by input leak total (IL) of device connected to bus at output of 'H' to (2)The bus electric potential SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. Microcontroller BR24LXX VCC - ILRPU - 0.2Vcc VIH RPU 0.8Vcc-VIH IL RPU Ex. ) When VCC =3V, IL=10A, VIH=0.7 VCC, from (2) RPU SDA terminal A IL 0.8x3-0.7x3 10x10-6 IL Bus line capacity CBUS 300 [k] Fig.52 I/O circuit diagram Minimum value of RPU The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VCC-VOL IOL RPU RPU VC-VOL IOL (2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 VCC Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC from (1) 3-0.4 RPU 3x10 -3 867 [] And VOL = 0.4 [V] VIL = 0.3x3 = 0.9 [V] Therefore, the condition (2) is satisfied. Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. A0, A1, A2, WP process Process of device address terminals (A0,A1,A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'. Types with N.C.PIN BR24L16/F/FJ/FV/FVT/FVM/FVJ-W A0, A1, A2 BR24L08/F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1 BR24L04/F/FJ/FV/FVT/FVM/FVJ/NUX-W A0 Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 16/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Cautions on microcontroller connection Rs 2 In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used. ACK SCL RPU RS SDA 'H' output of microcontroller Microcontroller 'L' output of EEPROM Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. EEPROM Fig.53 I/O circuit diagram Fig.54 Input / output collision timing Maximum value of Rs The maximum value of Rs is determined by the following relations. (1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus (2)The bus electric potential should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc. VCC (VCCVOL)xRS RPU+RS RPU A RS VOL RS 1.1VCCVIL x RPU Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20k Bus line capacity CBUS from(2), RS 0.3x30.40.1x3 1.1x30.3x3 EEPROM Microcontroller VOL+0.1VCCVIL VILVOL0.1VCC IOL VIL + x 20x103 1.67k Fig.55 I/O circuit diagram Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. RPU 'L' output RS Over current VCC RS I RS VCC I Example)When VCC=3V, I=10mA 'H' output RS Microcontroller EEPROM 3 -3 10x10 300 Fig.56 I/O circuit diagram www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 17/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series I2C BUS input / output circuit Input (A0,A2,SCL) Fig.57 Input pin circuit diagram Input / output (SDA) Fig.58 Input / output pin circuit diagram Input (A1, WP) Fig.59 Input pin circuit diagram Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. tR VCC Recommended conditions of tR, tOFF,Vbot tR tOFF tOFF Vbot Vbot 10ms or below 10ms or longer 0.3V or below 100ms or below 10ms or longer 0.2V or below 0 Fig.60 Rise waveform diagram www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 18/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. VCC tLOW SCL SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT tSU:DAT Fig.61 When SCL= 'H' and SDA= 'L' Fig.62 When SCL='L' and SDA='L' b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. Notes for use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 19/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Serial EEPROM Series High Reliability Series EEPROMs I2C BUS BR24S-W Series Description BR24S-W series is a serial EEPROM of I2C BUS interface method. Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) 2) Other devices than EEPROM can be connected to the same port, saving microcontroller port. 3) 1.75.5V single power source action most suitable for battery use. 4) FAST MODE 400kHz at 1.75.5V 5) Page write mode useful for initial value write at factory shipment. 6) Highly reliable connection by Au pad and Au wire. 7) Auto erase and auto end function at data rewrite. 8) Low current consumption At write operation (5V) : 0.5mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) 9) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage 10) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package 11) Data rewrite up to 1,000,000 times 12) Data kept for 40 years 13) Noise filter built in SCL / SDA terminal 14) Shipment data all address FFh Page write Number of pages Product number 16Byte 32Byte 64Byte BR24S08-W BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W BR24S series Capacity Bit format Type Power source voltage SOP8 SOP-J8 8Kbit 1Kx8 BR24S08-W 16Kbit 1.75.5V 2Kx8 BR24S16-W 1.75.5V 32Kbit 4Kx8 BR24S32-W 1.75.5V 64Kbit 8Kx8 BR24S64-W 1.75.5V 128Kbit 16Kx8 BR24S128-W 1.75.5V 256Kbit 32Kx8 BR24S256-W 1.75.5V www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 20/40 MSOP8 TSSOP-B8J VSON008 X2030 SSOP-B8 TSSOP-B8 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Absolute maximum ratings (Ta=25) Parameter symbol Impressed voltage VCC Limits Unit -0.3+6.5 V 450 (SOP8) *1 450 (SOP-J8) *2 300 (SSOP-B8) *3 Permissible dissipation 330 (TSSOP-B8) *4 Pd 310 (MSOP8) mW *5 310 (TSSOP-B8J) *6 300 (VSON008X2030) *7 Storage temperature range Tstg -65+125 Action temperature range Topr -40+85 - -0.3Vcc+1.0 V Terminal voltage *When using at Ta=25 or higher, 4.5mW(*1,*2), 3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,*6) to be reduced per 1 Memory cell characteristics (Ta=25, Vcc=1.75.5V) Limits Parameter Number of data rewrite times *1 Data hold years Unit Min. Typ. Max. 1,000,000 - - Times 40 - - Years *1 *1 Not 100% TESTED Recommended operating conditions Parameter Symbol Limits Power source voltage Vcc 1.75.5 Input voltage VIN 0Vcc Electrical characteristics (Unless otherwise specified, T=-40+85, Vcc=1.75.5V) Limits Parameter Symbol Min Typ. Max. Unit Unit V Condition "H" Input Voltage1 VIH1 0.7Vcc - Vcc+1.0 V "L" Input Voltage1 VIL1 -0.3 - 0.3Vcc V "L" Output Voltage1 VOL1 - - 0.4 V IOL=3.0mA , 2.5VVcc5.5V (SDA) "L" Output Voltage2 VOL2 - - 0.2 V IOL=0.7mA , 1.7VVcc2.5V (SDA) Input Leakage Current ILI -1 - 1 A VIN=0Vcc Output Leakage Current ILO -1 - 1 A VOUT=0Vcc (SDA) - - 2.0 - - 2.5 ICC2 - - 0.5 mA ISB - - 2.0 A Current consumption at action Standby Current ICC1 mA Vcc=5.5V , fSCL =400kHz, tWR=5ms Byte Write, Page Write BR24S08/16/32/64-W Vcc=5.5V , fSCL =400kHz, tWR=5ms Byte Write, Page Write BR24S128/256-W Vcc=5.5V , fSCL =400kHz Random read, Current read, Sequential read Vcc=5.5V , SDASCL=Vcc A0, A1, A2=GND, WP=GND Radiation resistance design is not made. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 21/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Action timing characteristics (Unless otherwise specified, T=-40+85, Vcc=1.75.5V) Parameter Symbol Limits Min. Typ. Max. Unit SCL Frequency fSCL - - 400 kHz Data clock "High" time tHIGH 0.6 - - s tLOW 1.2 - - s tR - - 0.3 s Data clock "Low" time SDA, SCL rise time SDA, SCL fall time *1 tF - - 0.3 s Start condition hold time *1 tHD:STA 0.6 - - s Start condition setup time tSU:STA 0.6 - - s Input data hold time tHD:DAT 0 - - ns Input data setup time tSU:DAT 100 - - ns Output data delay time tPD 0.1 - 0.9 s Output data hold time tDH 0.1 - - s tSU:STO 0.6 - - s Bus release time before transfer start tBUF 1.2 - - s Internal write cycle time tWR - - 5 ms Stop condition data setup time Noise removal valid period (SDA,SCL terminal) tI - - 0.1 s WP hold time tHD:WP 0 - - ns WP setup time tSU:WP 0.1 - - s WP valid time tHIGH:WP 1.0 - - s *1 : Not 100% TESTED www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 22/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Sync data input/output timing tR tF tHIGH SCL SCL tSU:DAT tHD:STA tLOW tHD:DAT tSU:STA tHD:STA tSU:STO SDA () (Input) SDA tPD tBUF tDH SDA () (Output) START BIT STOP BIT Input read at the rise edge of SCL Data output in sync with the fall of SCL Fig.1-(a) Sync data input / output timing Fig.1-(b) Start - stop bit timing SCL SCL DATA(1) SDA D0 ACK WRITE DATA(n) SDA tWR STOP CONDITION D1 DATA(n) D0 ACK ACK WR START CONDITION Stop condition WP tSUWP Fig.1-(c) Write cycle timing HDWP Fig.1-(d) WP timing at write execution SCL DATA(n) DATA(1) SDA D1 D0 ACK ACK tHIGH:WP tWR tWR WP At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP= 'LOW'. By setting WP "HIGH" in the area, write can be cancelled. When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Fig.1-(e) WP timing at write cancel Block diagram *2 A0 1 8Kbit256Kbit EEPROM array 8 Vcc 7 WP 6 SCL 5 SDA *1 10bit 11bi t 12bit 13bit 14bit 15bit *2 *2 A1 2 A2 3 Adddress decoder 8bit *1 10bit 11bit 12bit 13bit 14bit 15bit Data register Slave - word address register START STOP Control circuit ACK GND High voltage generating circuit 4 1 10bit: BR24S08-W 11bit: BR24S16-W 12bit: BR24S32-W 13bit: BR24S64-W 14bit: BR24S128-W 15bit: BR24S256-W Power source voltage detection 2 A0, A1= Don't use: BR24S08-W A0, A1, A2= Don't use: BR24S16-W Fig.2 Block diagram www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 23/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Pin assignment and description A0 1 A1 2 A2 3 GND 4 BR24S08-W BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W 8 Vcc 7 WP 6 SCL 5 SDA Function Terminal name Input/ Output BR24S08-W BR24S16-W BR24S32/64/128/256-W A0 Input Don't use Don't use Slave address setting A1 Input Don't use Don't use Slave address setting A2 Input Slave address setting Don't use Slave address setting GND - SDA Input / Output SCL Input Reference voltage of all input / output, 0V. Slave and word address, Serial data input serial data output Serial clock input WP Input Write protect terminal Vcc - Connect the power source. Characteristic data (The following values are Typ. ones.) 6 5 4 3 SPEC 2 1 1 L OUTPUT VOLTAGE : VOL[V] Ta=-40 Ta=25 Ta=85 L INPUT VOLTAGE : VIL[V] H INPUT VOLTAGE : VIH[V] 6 Ta=-40 Ta=25 Ta=85 5 4 3 2 1 SPEC 0 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 1 3 4 5 6 0 SPEC 0.2 0 2 3 4 5 L OUTPUT CURRENT : IOL[mA] 6 Fig.6 'L' output voltage VOL-IOL(Vcc=2.5V) www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 2 3 4 5 6 7 L OUTPUT CURRENT : IOL[mA] 8 Fig.5 'L' output voltage VOL-IOL(Vcc=1.7V) SPEC 1 0.8 0.6 Ta=-40 Ta=25 Ta=85 0.4 0.2 SPEC 1 0.8 0.6 Ta=-40 Ta=25 Ta=85 0.4 0.2 0 0 1 1 1.2 OUTPUT LEAK CURRENT : ILO[uA] 0.8 0 SPEC 0.2 Fig.4 'L' input voltage VIL (A0,A1,A2,SCL,SDA,WP) INPUT LEAK CURRENT : ILI[uA] L OUTPUT VOLTAGE : VOL[V] 2 1.2 0.4 0.4 SUPPLY VOLTAGE : Vcc[V] 1 Ta=-40 Ta=25 Ta=85 0.6 0 0 Fig.3 'H' input voltage VIH (A0,A1,A2,SCL,SDA,WP) 0.6 Ta=-40 Ta=25 Ta=85 0.8 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc[V] Fig.7 Input leak current ILI (A0,A,A2,SCL,WP) 24/40 6 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 Fig.8 Output leak current ILO(SDA) 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Characteristic data (The following values are Typ. ones.) SPEC Ta=-40 Ta=25 Ta=85 0.5 2.5 2 Ta=-40 Ta=25 Ta=85 1.5 1 0.5 0 1 2 3 4 5 Fig.9 Current consumption at WRITE operation ICC1 (fSCL=400kHz BR24S16/32/64-W) 1 0.2 0.1 6 0 1.5 Ta=-40 Ta=25 Ta=85 1000 SPEC 100 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Ta=-40 Ta=25 Ta=85 10 0 1 SPEC 4 3 Ta=-40 Ta=25 Ta=85 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 START CONDITION HOLD TIME : tHD : STA[us] 5 INPUT DATA HOLD TIME : tHD :DAT[ns] -50 Ta=-40 Ta=25 Ta=85 4 3 Ta=-40 Ta=25 Ta=85 2 1 4 5 0 1 2 3 4 5 SPEC 0 -50 Ta=-40 Ta=25 Ta=85 0 6 Fig.18 Input Data Hold Time tHD : DATHIGH 200 SPEC 100 Ta=-40 Ta=25 Ta=85 -200 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Ta=-40 Ta=25 Ta=85 0.2 0 0 1 1 6 Fig.21 Input Data setup time tSU : DAT(LOW) www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 200 SPEC 100 0 SPEC 2 1 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Fig.22 'L' Data output delay time tPD0 25/40 Ta=-40 Ta=25 Ta=85 -100 -200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V] Ta=-40 Ta=25 Ta=85 0 6 300 6 4 3 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Fig.17 Start Condition Setup Time tSU : STA Fig.19 Input Data Hold Time HD : DAT(LOW OUTPUT DATA DELAY TIME : tPD[us] 300 -100 0.4 6 50 SUPPLY VOLTAGE : Vcc[V] 0 SPEC 0.6 Fig.20 Input Data Setup Time SU: DAT(HIGH) OUTPUT DATA DELAY TIME : tPD[us] 3 6 -0.2 0 -200 -200 2 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 0.8 SPEC -150 1 0 Fig.14 Data clock High Period tHIGH -100 -150 0 0 Fig.16 Start Condition Hold Time tHD : STA 0 -100 0.2 6 5 Fig.15 Data clock Low Period tLOW SPEC SPEC 0.4 SUPPLY VOLTAGE : Vcc[V] 50 6 0.6 Fig.13 SCL frequency fSCL Fig.12 Stanby operation ISB 2 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Ta=-40 Ta=25 Ta=85 0.8 0.1 6 START CONDITION SET UP TIME : tSU:STA[us] 0.5 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 1 INPUT DATA SET UP TIME : tSU: DAT[ns] 1 1 Fig.11 Current consumption at READ operation ICC2 (fSCL=400kHz) DATA CLK H TIME : tHIGH[us] 2 Ta=-40 Ta=25 Ta=85 0.3 10000 SPEC SCL FREQUENCY : f[HZ] STANBY CURRENT : ISB[uA] 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] Fig.10 Current consumption at WRITE operation Icc1 (fSCL=400kHz BR24S128/256-W) 2.5 CLK L TIME : tLOW[us] 0.4 0 0 6 SUPPLY VOLTAGE : Vcc[V] INPUT DATA HOLD TIME : tHD: STA[ns] 0.5 0 0 INPUT DATA SET UP TIME : tSU : DAT[ns] CURRENT CONSUMPTION AT READING : Icc2[mA] SPEC CURRENT CONSUMPTION AT WRITING : Icc1[mA] 1.5 1 SPEC 3 2 CURRENT CONSUMPTION AT WRITING : Icc1[mA] 0.6 3.5 2.5 6 4 Ta=-40 Ta=25 Ta=85 3 SPEC 2 1 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V] Fig.23 'H' Data output delay time PD1 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Characteristic data (The following values are Typ. ones.) 1 4 3 2 SPEC 1 SPEC 5 4 3 2 Ta=-40 Ta=25 Ta=85 1 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 0 6 Fig.24 BUS open time before transmission BUF 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 0.4 0.3 0.2 SPEC 0.1 0 1 2 3 4 5 0.4 0.3 0.2 SPEC 0.1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 0.5 0.4 0.3 Ta=-40 Ta=25 Ta=85 0.2 SPEC 0.1 0 0 2 SUPPLY VOLTAGE : Vcc[V] 4 6 SUPPLY VOLATGE : Vcc[V] Fig.28 Noise resuction efecctive time SDA H Fig.27 Noise reduction efective time tlSCL L 1 0.6 Ta=-40 Ta=25 Ta=85 0.5 6 0.2 Fig.26 Noise reduction efection time tlSCL H 0 0 0.4 0 NOISE REDUCTION EFFECTIVE TIME : tl(SAD L)[us] 0.5 Ta=-40 Ta=25 Ta=85 0.6 6 0.6 Ta=-40 Ta=25 Ta=85 NOISE REDUCTION EFECTIVE TIME : tl(SDA H)[us] NOISE REDUCTION EFECTIVE TIME : tl(SCL L)[us] 1 Fig.25 Internal writing cycle time WR 0.6 SPEC 0.8 0 0 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V] Fig.29 Noise reduction efective time tlSDA L 1.2 WP EFFECTIVE TIME : tHIGH : WP[us] 0.2 WP SET UP TIME : tSU : WP[us] NOISE REDUCTION EFECTIVE TIME : tl(SCL H) [us] 6 Ta=-40 Ta=25 Ta=85 INTERNAL WRITING CYCLE TIME : tWR[ms] BUS OPEN TIME BEFORE TRANSMISSION : tBUF[us] 5 SPEC 0.1 0 -0.1 Ta=-40 Ta=25 Ta=85 -0.2 -0.3 -0.4 -0.5 -0.6 SPEC 1 0.8 0.6 0.4 Ta=-40 Ta=25 Ta=85 0.2 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 Fig.30 WP setup time tSU : WP www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc[V] 6 Fig.31 WP efective time tHIGH : WP 26/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series I2C BUS communication 2 I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by addresses peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver". SDA 1-7 SCL S START ADDRESS condition 8 9 R/W ACK 1-7 8 DATA 1-7 9 ACK 8 9 DATA ACK P STOP condition Fig.32 Data transfer timing Start condition (start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. Stop condition (stop bit recognition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R/W to 0 --- write (setting 0 to word address setting of random read) Setting R/W to 1 --- read Type Maximum number of connected buses Slave address A0 1 A1 2 2 1 A2 3 8 GND 4 BR24S08-W 1 0 1 0 A2 P1 P0 R/W BR24S16-W 1 0 1 0 P2 P1 P0 R/W BR24S32-W, BR24S64-W BR24S128-W, BR24S256-W 1 0 1 0 A2 A1 A0 R/W BR24S08-W BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W 8 Vcc 7 WP 6 SCL 5 SDA P0P2 are page select bits. Note) Up to 2 units of BR24S08-W, up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected. Device address is set by 'H' and 'L' of each pin of A0, A1, and A2. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 27/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 64 arbitrary bytes can be written. (In the case of BR24S128/256-W) S T A R T SDA LINE W R I T E SLAVE ADDRESS WORD ADDRESS WA 7 1 0 1 0 A2 A1 A0 DATA WA 0 D7 D0 A C K R A / C W K Note) S T O P A C K Fig.33 Byte write cycle (BR24S08/16-W) S T A R T SDA LINE W R I T E SLAVE ADDRESS WA WA WAWA 14 13 12 11 1 0 1 0 A2 A1 A0 R A / C W K Note) 2nd WORD ADDRESS 1st WORD ADDRESS WA 0 *1 D0 D7 A C K A C K *1 S T O P DATA As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care. A C K Fig.34 Byte write cycle (BR24S32/64/128/256-W) S T A R T SDA L IN E W R I T E SLAVE ADDRESS W ORD A D D R E S S (n ) WA 7 1 0 1 0 A 2A 1A 0 WA 0 R A / C *1 W K ) Note) D A T A (n ) D7 D A T A (n + 1 5 ) D0 A C K S T O P *2 D0 A C K A C K Fig.35 Page write cycle (BR24S08/16-W) S T A R T SDA L IN E SLAVE ADDRESS W R I T E R A / C W K *1 D A T A (n ) WA 0 A C K S T O P *2 2nd W ORD A D D R E S S (n ) W A W AW A W A 1 4 13 1 2 11 1 0 1 0 A 2A 1A 0 N o te ) 1 st W O R D A D D R E S S (n ) D7 D A TA (n + 3 1 ) D0 A C K D0 A C K A C K *1 As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care. *2 As for BR24S128/256-W becomes (n+63). Fig.36 Page write cycle (BR24S32/64/128/256-W) Data is written to the address designated by word address (n-th address). By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk: Up to 16 bytes (BR24S08-W, BR24S16-W) : Up to 32 bytes (BR24S32-W, BR24S64-W) : Up to 64 bytes (BR24S128-W, BR24S256-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment of "Notes on page write cycle" in P24/32.) As for page write command of BR24S08-W and, BR24S16-W, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. As for page write cycle of BR24S32-W and BR24S64-W , after the significant 7 bits (in the case of BR24S32-W) of word address, or the significant 8 bits (in the case of BR24S64-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. As for page write cycle of BR24S128-W and BR24S256-W, after the significant 9 bit (in the case of BR24S128-W) of word address, or the significant 10bit (in the case of BR24S256-W) of word address are designated arbitrarily, by continuing data input of 64 bytes or more. Note) *1 *2 *3 1 0 1 0 A 2A 1A 0 *1 *2 *3 In BR24S16-W, A2 becomes P2 In BR24S08/16-W, A1 becomes P1 In BR24S08/16-W, A0 becomes P0 Fig.37 Difference of slave address each type www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 28/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Notes on write cycle continuous input At STOP (stop bit) write starts. S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 0 P2 P1 P0 WORD ADDRESS DATA(n) WA 0 WA 7 R A / C W K note) DATA(n+15) D7 D0 A C K Fig.38 S T A R T S T O P D0 A C K 1 0 1 0 A C K Next command tWR(maximum5ms) Command is not accepted for this period. Page write cycle(BR24S08/16-W) A t S TO P (stop bit) w rite starts. SDA L IN E S T A R T SLAVE ADDRESS W R I T E 1 0 1 0 A 2A 1A 0 note ) 1 st W O R D A D D R E S S (n ) 2nd W ORD A D D R E S S (n ) WA 0 W A W AW A W A 14 13 12 11 R A / C W K *1 A C K *2 D A TA (n+ 31 ) D A T A (n ) D7 A C K D0 S T A R T S T O P As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care. 1 0 1 0 D0 *2 As for BR24S128/256-W becomes (n+63). A C K A C K *1 N e xt co m m a n d tW R (ma ximu m : 5 m s) C o m m an d is n ot a ccep te d for th is period . Fig.39 Page write cycle(BR24S32/64/128/256-W) Notes on page write cycle List of numbers of page write Number of pages 16Byte 32Byte Product number BR24S08-W BR24S16-W BR24S32-W BR24S64-W 64Byte BR24S128-W BR24S256-W The above numbers are maximum bytes for respective types. Any bytes below these can be written. In the case of BR24S256-W, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write. It does not stand 5ms at maximum x 64byte = 320ms(Max.). www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 29/40 2009.09 - Rev.D BR24L-W Series,BR24S-W Series Technical Note Internal address increment Page write mode (in the case of BR24S16-W) WA7 ----0 ----0 ----0 ----- WA4 0 0 0 WA3 0 0 0 WA2 WA1 0 0 0 0 0 1 --------- --------- 0Eh 0 0 0 ------------- WA0 0 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up For example, when it is started from address 0Eh, therefore, increment is made as below, 0Eh0Fh00h01h, which please note. * 0Eh16 in hexadecimal, therefore, 00001110 becomes a binary number. Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 30/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession. S T A R T W R I T E SLAVE ADDRESS SDA L IN E S T A R T W ORD A D D R E S S (n) WA 7 1 0 1 0 A 2 A 1A 0 WA 0 R A / C W K N o te) R E A D S LA V E ADDRESS D A TA (n) 1 0 1 0 A 2 A 1A 0 A C K S T O P It is necessary to input 'H' to the last ACK. D0 D7 A C K R A / C W K Fig.40 Random read cycle (BR24S08/16-W) S T A R T SLAVE ADDRESS SDA LINE W R I T E 1st WORD ADDRESS 1 0 1 0 A2A1A0 Note) A C K *1 R E A D SLAVE ADDRESS S T O P DATA(n) *1 WA 0 WA WA WAWA 14 13 12 11 R A / C W K S T A R T 2nd WORD ADDRESS 1 0 1 0 A2A1A0 A C K D7 D0 R A / C W K As for WA12, BR24S32-W become Don't care. As for WA13, BR24S32/64-W become Don't care. As for WA14, BR24S32/64/128-W become Don't care. A C K Fig.41 Random read cycle (BR24S32/64/128/256-W) S T A R T SDA L IN E R E A D S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0 D A TA (n ) D7 D0 A C K R A / C W K N ote ) It is necessary to input 'H' to the last ACK. S T O P Fig.42 Current read cycle S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 A1A0 Note D7 D0 R A / C W K S T O P DATA(n+x) DATA(n) D7 A C K D0 A C K A C K Fig.43 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'. When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. Note) *1 *2 *3 1 0 1 0 A2 A1A0 *1 *2 *3 BR24S16-W A2 becomes P2. BR24S08/16-W A1 becomes P1. BR24S08/16-W A0 becomes P0. Fig.44 Difference of slave address of each type www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 31/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.45(a), Fig.45(b), Fig.45(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clockx14 SCL 1 2 13 Startx2 Normal command 14 Normal command SDA Fig.45-(a) The case of 14 Dummy clock + START + START+ command input Start 1 SCL Start Dummy clockx9 2 8 Normal command 9 Normal command SDA Fig.45-(b) The case of START+9 Dummy clock + START + command input Startx9 SCL 1 2 3 7 8 9 Normal command SDA Normal command * Start command from START input. Fig.45-(c) START x 9 + command input Acknowledge polling During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data so forth. During internal write, ACK = HIGH is sent back. First write command S T A R T Write command S T O P S T A R T Slave address S T A Slave R address T A C K H A C K H ... tWR Second write command ... S T Slave A R address T A C K H S T Slave A R address T A C K L Word address A C K L Data A C K L S T O P tWR After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession. Fig.46 Case to continuously write by acknowledge polling www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 32/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum). Rise of D0 taken clock SCL SCL Rise of SDA SDA D0 D1 SDA ACK Enlarged view SDA S T Slave A R address T ACK D0 Enlarged view A A C Word C K address K D7 D6 D5 D4 D3 D2 D1 D0 L L WP cancel invalid area A C K L Data A C K L WP cancel valid area S T O P tWR Write forced end WP Data is not written. Data not guaranteed Fig.47 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 48.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Fig.48 Case of cancel by start, stop condition during slave address input www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 33/40 2009.09 - Rev.D BR24L-W Series,BR24S-W Series Technical Note I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. Microcontroller BR24SXX Vcc - ILRPU - 0.2Vcc VIH 0.8VCC - VIH RPU IL Ex.) When Vcc = 3V, IL=10A, VIH = 0.7Vcc from(2) 0.8x3 - 0.7x3 RPU -6 10x10 300 k Minimum value of RPU The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VCC - VOL IOL RPU RPU Bus line capacity CBUS Fig.49 I/O circuit diagram VCC - VOL IOL (2)VOLMAX =0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 Vcc Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from(1), 30.4 RPU 3x10 867 And VOL=0.4V VIL=0.3x3 =0.9V Therefore, the condition (2) is satisfied. Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. A0, A1, A2, WP process Process of device address terminals (A0,A1,A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins(Don't use PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'. Types with Don't use PIN BR24S08F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1 BR24S16F/FJ/FV/FVT/FVM/FVJ/NUX-W A0, A1, A2 Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 34/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Cautions on microcontroller connection Rs 2 In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used. ACK SCL RPU RS SDA 'H' output of microcontroller 'L' output of EEPROM Microcontre Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. EEPROM Fig.50 I/O circuit diagram Fig.51 Input/output collision timing Maximum value of Rs The maximum value of Rs is determined by following relations. (1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below. And AC timing should be satisfied even when SDA rise time is late. A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should (2)The bus electric potential sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc. VCC RPU RS (VCCVOL)xRS RPU+RS A VOL RS VILVOL0.1VCC 1.1VCCVIL IOL from(2), RS EEPROM Microcontroller x ExampleWhen VCC=3V, VIL=0.3VCC, VOL=0.4V, Bus line capacity CBUS VIL VOL+0.1VCCVIL + 0.3x30.40.1x3 1.1x30.3x3 1.67k RPU RPU=20k x 20x103 Fig.52 I/O circuit diagram Maximum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. RPU I RS VCC I 'L' output RS ExampleWhen VCC=3V, I=10mA Over current RS 'H' output Microcontroller VCC RS 3 10x10-3 EEPROM Fig.53 I/O circuit diagram www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 35/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series I2C BUS input / output circuit Input (A0, A1, A2, SCL, WP) Fig.54 Input pin circuit diagram Input/Output (SDA) Fig.55 Input /output pin circuit diagram Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following condition at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. Recommended conditions of tR,tOFF,Vbot tR VCC tOFF Vbot 0 tR tOFF Vbot 10ms or below 10ms or longer 0.3V or below 100ms or below 10ms or longer 0.2V or below Fig.56 Rise waveform diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. VCC tLOW SCL SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT tSU:DAT Fig.57 When SCL='H' and SDA='L' Fig.58 When SCL='H' and SDA='L' b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P26). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 36/40 2009.09 - Rev.D BR24L-W Series,BR24S-W Series Technical Note Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. Notes for use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 37/40 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series Ordering part number B R 2 Part No. 4 S BUS type 2 Operating temperature/ Power source voltage 2 24I C 5 6 Capacity 01=1K 02=2K 04=4K L: -40~+85/ 08=8K 1.8V ~ 5.5V S: -40~+85/ 1.7V ~ 5.5V F - Package 16=16K 32=32K 64=64K 128=128K 256=256K F : SOP8 FJ : SOP-J8 FV : SSOP-B8 FVM : MSOP8 FVT :TSSOP-B8 FVJ :TSSOP-B8J NUX : VSON008X2030 W E 2 Double cell Packaging and forming specification E2: Embossed tape and reel TR: Embossed tape and reel Package specifications SOP8 <Tape and Reel information> 7 6 5 +6 4 -4 6.20.3 4.40.2 0.3MIN 8 1 2 3 0.90.15 5.00.2 (MAX 5.35 include BURR) Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 0.595 1.50.1 +0.1 0.17 -0.05 0.11 S 1.27 0.420.1 1pin Reel (Unit : mm) Direction of feed Order quantity needs to be multiple of the minimum quantity. SOP-J8 <Tape and Reel information> 4.90.2 (MAX 5.25 include BURR) +6 4 -4 6 5 0.45MIN 7 3.90.2 6.00.3 8 1 2 3 Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 0.545 0.20.1 0.175 1.3750.1 S 1.27 0.420.1 0.1 S 1pin Reel (Unit : mm) www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 38/40 Direction of feed Order quantity needs to be multiple of the minimum quantity. 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series SSOP-B8 <Tape and Reel information> 3.0 0.2 (MAX 3.35 include BURR) 0.3MIN 4.40.2 6.40.3 8 76 5 Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 1.150.1 1 23 4 0.15 0.1 0.1 S 0.1 +0.06 0.22 -0.04 (0.52) 0.08 M 0.65 1pin Reel (Unit : mm) Direction of feed Order quantity needs to be multiple of the minimum quantity. TSSOP-B8 <Tape and Reel information> 3.0 0.1 (MAX 3.35 include BURR) 8 7 6 44 3000pcs 2 3 4 1PIN MARK E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 1.00.2 0.50.15 6.40.2 4.40.1 1 +0.05 0.145 -0.03 S 0.10.05 1.2MAX Embossed carrier tape Quantity Direction of feed 0.525 1.00.05 Tape 5 0.08 S +0.05 0.245 -0.04 0.08 Direction of feed M 1pin 0.65 Reel (Unit : mm) Order quantity needs to be multiple of the minimum quantity. TSSOP-B8J <Tape and Reel information> 3.0 0.1 (MAX 3.35 include BURR) 5 4.90.2 0.450.15 2 3 4 1PIN MARK Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 0.950.2 6 +0.05 0.145 - 0.03 0.525 S 0.10.05 0.850.05 1 1.1MAX 7 3.00.1 8 44 0.08 S +0.05 0.32 -0.04 0.08 M 1pin 0.65 Reel (Unit : mm) www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 39/40 Direction of feed Order quantity needs to be multiple of the minimum quantity. 2009.09 - Rev.D Technical Note BR24L-W Series,BR24S-W Series MSOP8 <Tape and Reel information> 2.80.1 4.00.2 8 7 6 5 0.60.2 +6 4 -4 0.290.15 2.90.1 (MAX 3.25 include BURR) Tape Embossed carrier tape Quantity 3000pcs Direction of feed TR The direction is the 1pin of product is at the upper right when you hold ( reel on the left hand and you pull out the tape on the right hand ) 1 2 3 4 1PIN MARK 1pin +0.05 0.145 -0.03 0.475 +0.05 0.22 -0.04 0.080.05 0.750.05 0.9MAX S 0.08 S Direction of feed 0.65 Reel (Unit : mm) Order quantity needs to be multiple of the minimum quantity. VSON008X2030 <Tape and Reel information> 3.00.1 2.00.1 0.6MAX 1PIN MARK 0.25 TR The direction is the 1pin of product is at the upper right when you hold ( reel on the left hand and you pull out the tape on the right hand ) (0.12) +0.03 0.02 -0.02 4000pcs 0.5 1 4 8 5 1.40.1 0.30.1 C0.25 1.50.1 Embossed carrier tape Quantity Direction of feed S 0.08 S Tape +0.05 0.25 -0.04 1pin Reel (Unit : mm) www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. 40/40 Direction of feed Order quantity needs to be multiple of the minimum quantity. 2009.09 - Rev.D Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved. R0039A