FM16W08
64-Kbit (8 K × 8) Wide Voltage Bytewide
F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-86210 Rev. *F Revised September 8, 2015
64-Kbit (8 K × 8) Wide Voltage By tewide F-RAM Memory
Features
■64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8 K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (see the Data Retention and
Endurance table)
❐NoDelay™ writes
❐Advanced high-reliability ferroelectric process
■SRAM and EEPROM compatible
❐Industry-standard 8 K × 8 SRAM and EEPROM pinout
❐70-ns access time, 130-ns cycle time
■Superior to battery-backed SRAM modules
❐No battery concerns
❐Monolithic reliability
❐True surface mount solution, no rework steps
❐Superior for moisture, shock, and vibration
❐Resistant to negative voltage undershoots
■Low power consumption
❐Active current 12 mA (max)
❐Standby current 20 A (typ)
■Wide voltage operation: VDD = 2.7 V to 5.5 V
■Industrial temperature: –40 C to +85 C
■28-pin small outline integrated circuit (SOIC) package
■Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM16W08 is a 8 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM16W08 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM16W08 ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
Address Latch and Decoder
CE
Control
Logic
WE
A
I/O Latch & Bus Driver
OE
DQ
8 K x 8
F-RAM Array
12-0
7-0
A12-0
FM16W08
Document Number: 001-86210 Rev. *F Page 2 of 18
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
Memory Architecture ................................................... 4
Memory Operation .......................................................4
Read Operation ...........................................................4
Write Operation ........................................................... 4
Pre-charge Operation ..................................................4
Endurance .........................................................................4
F-RAM Design Considerations .............. ... ................. ... ...5
Maximum Ratings .............................................................7
Operating Range ..................... .. ................. ... ................. ...7
DC Electrical Characteristics ......................... .................7
Data Retention and Endurance .......................................7
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Conditions ............. ................. ................ ... .........8
AC Switching Characterist ics .......... ... .. ................. ... ......9
SRAM Read Cycle ......................................................9
SRAM Write Cycle ..................................................... 10
Power Cycle Timing .......................................................12
Functional Truth Table .................... ... ... ................. ... .....13
Ordering Information ......................................................14
Ordering Code Definitions ......................................... 14
Package Diagram ............................................................15
Acronyms ........................................................................ 16
Document Conventions ...................................... ... ........16
Units of Measure ....................................................... 16
Document History Page .............................. .. .................17
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
FM16W08
Document Number: 001-86210 Rev. *F Page 3 of 18
Pinout Figure 1. 28-pin SOIC pinout
Pin Definitions
Pin Name I/O Type Description
A12–A0Input Address inputs: The 13 address lines select one of 8,192 bytes in the F-RAM array.
DQ7–DQ0Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. Asserting WE LOW causes the FM16W08 to
write the contents of the data bus to the address location latched by the falling edge of CE.
CE Input Chip Enable: The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
OE Input Output Enable: When OE is LOW, the FM16W08 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
DQ4
DQ5
DQ6
DQ7
OE
A8
NC
WE
A9
A10
A11
VDD
CE
DQ3
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A12
A7
A6
A5
A428-pin SOIC
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
16
15
19
18
17
21
20
24
23
22
26
25
28
27
FM16W08
Document Number: 001-86210 Rev. *F Page 4 of 18
Device Operation
The FM16W08 is a bytewide F-RAM memory logically organized
as 8,192 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM16W08 requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 13 for a complete description of
read and write modes.
Memory Architecture
Users access 8,192 memory locations, each with 8 data bits
through a parallel interface. The complete 13-bit address
specifies each of the 8,192 bytes uniquely. The F-RAM array is
organized as 1024 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance section.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic and timing
circuits. Likewise the access time is the same for read and write
memory operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that VDD remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between VDD and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing” on page 12.
Memory Operation
The FM16W08 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the performance is comparable but the bytewide
interface operates in a slightly different manner as described
below. For users familiar with EEPROM, the differences result
from the higher write performance of F-RAM technology
including NoDelay writes and much higher write endurance.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
The FM16W08 will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM16W08, writes occur in the same interval as reads. The
FM16W08 supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM16W08 will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the page 11 and
page 12.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM16W08, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
FM16W08
Document Number: 001-86210 Rev. *F Page 5 of 18
accessed data is located in different rows. Regardless, F-RAM
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 1014 cycles will allow
150,000 accesses per second to the same row for over 20 years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
falling edge of CE, users cannot ground it as they might with
SRAM.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in Figure 2 below. Also shown is a common SRAM signal
relationship that will not work for the FM16W08.
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
A second design consideration relates to the level of VDD during
operation. Battery-backed SRAMs are forced to monitor VDD in
order to switch to battery backup. They typically block user
access below a certain VDD level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
F-RAM memories do not need this system overhead. The
memory will not block access at any VDD level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when VDD is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track VDD during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below VDD min. (2.7 V).
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 2. Chip Enable and Memory Address Relationships
Valid Strobing of CE
F-RAM
Signaling
CE
Address A1 A2
Data D1 D2
Invalid Strobing of CE
SRAM
Signaling
CE
Address A1 A2
Data D1 D2
Figure 3. Use of Pull-up Resistor on CE
MCU / MPU
CE
WE
OE
A12-0
DQ 7-0
FM16W08
VDD
FM16W08
Document Number: 001-86210 Rev. *F Page 6 of 18
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If the chip is enabled
and WE is LOW during power cycles, data will be corrupted.
Figure 4 shows a pull-up resistor on WE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the WE pin tracks VDD to a high
enough value, so that the current drawn when WE is LOW is not
an issue.
Figure 4. Use of Pull-up Resistor on WE
MCU / MPU
CE
WE
OE
A12-0
DQ 7-0
FM16W08
VDD
FM16W08
Document Number: 001-86210 Rev. *F Page 7 of 18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.7 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [1] Max Unit
VDD Power supply voltage 2.7 3.3 5.5 V
IDD VDD supply current VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
––12mA
ISB Standby current VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
–2050µA
ILI Input leakage current VIN between VDD and VSS ––+1µA
ILO Output leakage current VOUT between VDD and VSS ––+1µA
VIH Input HIGH voltage 0.7 × VDD –V
DD + 0.3 V
VIL Input LOW voltage – 0.3 – 0.3 × VDD V
VOH1 Output HIGH voltage IOH = –1.0 mA, VDD > 2.7 V 2.4 – – V
VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V
VOL1 Output LOW voltage IOL = 2 mA, VDD > 2.7 V – – 0.4 V
VOL2 Output LOW voltage IOL = 150 µA – – 0.2 V
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention At +85 C 10 – Years
At +75 C38–
At +65 C151–
NVCEndurance Over operating temperature 1014 – Cycles
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
FM16W08
Document Number: 001-86210 Rev. *F Page 8 of 18
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times (10%–90%) ........................... < 5 ns
Input and output timing reference levels ...................0.5 VDD
Output load capacitance............................................. 100 pF
Capacitance
Parameter Description Test Conditions Max Unit
CI/O Input/Output capacitance (DQ) TA = 25 C, f = 1 MHz, VDD = VDD(Typ) 8 pF
CIN Input capacitance 6pF
Thermal Resist ance
Parameter Description Test Conditions 28-pin SOIC Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
58 C/W
JC Thermal resistance
(junction to case)
26 C/W
Figure 5. AC Test Loads
FM16W08
Document Number: 001-86210 Rev. *F Page 9 of 18
AC Switching Characteristics
Over the Operating Range
Parameters [2]
Description VDD = 2.7 V to 3.0 V VDD = 3.0 V to 5.5 V Unit
Cypress
Parameter Alt Parameter Min Max Min Max
SRAM Read Cycle
tCE tACE Chip enable access time – 80 – 70 ns
tCA –Chip enable active time 80 – 70 – ns
tRC –Read cycle time 145 – 130 – ns
tPC –Pre-charge time 65 – 60 – ns
tAS tSA Address setup time 0–0–ns
tAH tHA Address hold time 15 – 15 – ns
tOE tDOE Output enable access time – 15 – 12 ns
tHZ[3, 4] tHZCE Chip Enable to output HI-Z – 15 – 15 ns
tOHZ[3, 4] tHZOE Output enable HIGH to output HI-Z – 15 – 15 ns
Notes
2. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% and 90% of VDD, output loading of the
specified IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. This parameter is characterized but not 100% tested.
FM16W08
Document Number: 001-86210 Rev. *F Page 10 of 18
SRAM Write Cycle
tWC tWC Write cycle time 145 – 130 – ns
tCA –Chip enable active time 80 – 70 – ns
tCW tSCE Chip enable to write enable HIGH 80 – 70 – ns
tPC –Pre-charge time 65 – 60 – ns
tWP tPWE Write enable pulse width 50 – 40 – ns
tAS tSA Address setup time 0–0–ns
tAH tHA Address hold time 15 – 15 – ns
tDS tSD Data input setup time 40 – 30 – ns
tDH tHD Data input hold time 0–0–ns
tWZ[5, 6] tHZWE Write enable LOW to output HI-Z – 15 – 15 ns
tWX[6] –Write enable HIGH to output driven 10 –10 –ns
tHZ[5] –Chip enable to output HI-Z –15 –15 ns
tWS[7] –Write enable to CE LOW setup time 0 – 0 – ns
tWH[7] –Write enable to CE HIGH hold time 0 – 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [2]
Description VDD = 2.7 V to 3.0 V VDD = 3.0 V to 5.5 V Unit
Cypress
Parameter Alt Parameter Min Max Min Max
Notes
5. tWZ and tHZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
6. This parameter is characterized but not 100% tested.
7. The relationship between CE and WE determines if a CE or WE controlled write occurs.
FM16W08
Document Number: 001-86210 Rev. *F Page 11 of 18
Figure 6. Read Cycle Timing
Figure 7. Write Cycle Timing 1 (CE Controlled)
tAS
tOHZ
CE
OE
DQ
tAH
tCE
tOE
tCA
tRC
tPC
tHZ
7-0
A12-0
CE
WE
tAS
tAH
tCA
tWC
tPC
OE
tWS
tDS tDH
tWH
A12-0
DQ 7-0
FM16W08
Document Number: 001-86210 Rev. *F Page 12 of 18
Figure 8. Write Cycl e Timing 2 (WE Controlled)
tWS
tDH
tWH
CE
WE
tAS
tAH
tCA
tWC
tPC
OE
tDS
tWP
tWZ tWX
tC W
A12-0
DQ7-0(out)
DQ7-0(in)
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up (after VDD min. is reached) to first access time 10 –ms
tPD Last write (WE HIGH) to power down time 0 – µs
tVR[8] VDD power-up ramp rate 30 –µs/V
tVF[8] VDD power-down ramp rate 30 –µs/V
Figure 9. Power Cycle Timing
VDD tVF
VDD min
min
VDD
tVR
tPU
tPD
Access Allowed
VIL (max)
VIH (min)
Note
8. Slope measured at any point on the VDD waveform.
FM16W08
Document Number: 001-86210 Rev. *F Page 13 of 18
Functional Truth Table
CE WE Operation [9, 10]
H X Standby/Pre-charge
↓X Latch Address (and begin write if WE = LOW)
L H Read
L↓Write
Notes
9. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH.
10. The OE pin controls only the DQ output buffers.
FM16W08
Document Number: 001-86210 Rev. *F Page 14 of 18
Ordering Code Definitions
Ordering Information
Ordering Code Package Di-
agram Package Type Operating
Range
FM16W08-SG 51-85026 28-pin SOIC Industrial
FM16W08-SGTR 51-85026 28-pin SOIC
All the above parts are Pb-free.
Option:
blank = Standard; TR = Tape and Reel
Package Type:
SG = 28-pin SOIC
I/O Width: × 8
Voltage: 2.7 V to 5.5 V
64-kbit Parallel F-RAM
Cypress
16FM W 08 - SG TR
FM16W08
Document Number: 001-86210 Rev. *F Page 15 of 18
Package Diagram Figure 10. 28-pin SOIC Package Outline, 51-85026
51-85026 *H
FM16W08
Document Number: 001-86210 Rev. *F Page 16 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
CPU Central Processing Unit
CMOS Complementary Metal Oxide Semiconductor
JEDEC Joint Electron Devices Engineering Council
JESD JEDEC Standards
EIA Electronic Industries Alliance
F-RAM Ferroelectric Random Access Memory
I/O Input/Output
MCU Microcontroller Unit
MPU Microprocessor Unit
RoHS Restriction of Hazardous Substances
R/W Read and Write
SOIC Small Outline Integrated Circuit
SRAM Static Random Access Memory
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
Mmegaohm
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM16W08
Document Number: 001-86210 Rev. *F Page 17 of 18
Document History Page
Document Title: FM16W08, 64-Kbit (8 K × 8) Wide Voltage Bytewide F-RAM Memory
Document Number: 001-86210
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 3912933 GVCH 02/25/2013 New spec
*A 4000965 GVCH 05/15/2013 Added Appendix A - Errata for FM16W08
*B 4045491 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*C 4274813 GVCH 03/10/2014 Converted to Cypress standard format
Changed datasheet status from “Preliminary” to “Final”.
Replaced A14-A0 with A12-A0 in all instances across the document.
Updated Maximum Ratings:
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance.
Added Thermal Resistance.
Removed Package Marking Scheme (top mark)
*D 4562106 GVCH 11/05/2014 Added related documentation hyperlink in page 1.
Updated package diagram 51-85026 to current version.
*E 4591214 GVCH 12/09/2014 Fixed typo:
Changed title of Figure 6 from “Read Cycle Timing 1” to “Read Cycle Timing”.
Changed title of Figure 7 from “Read Cycle Timing 2 (CE Controlled)” to
“Write Cycle Timing 1 (CE Controlled)”.
*F 4881509 ZSK / PSR 09/08/2015 Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
Document Number: 001-86210 Rev. *F Revised September 8, 2015 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
FM16W08
© Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
Memory cypress.com/go/memory
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC® Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support