This is information on a product in full production.
November 2012 Doc ID 5711 Rev 15 1/46
1
M95320-W M95320-R
M95320-DF
32-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet − production data
Features
■Compatible with the Serial Peripheral Interface
(SPI) bus
■Memory array
– 32 Kb (4 Kbytes) of EEPROM
– Page size: 32 bytes
■Write
– Byte Write within 5 ms
– Page Write within 5 ms
■Additional Write lockable page (Identification
page)
■Write Protect: quarter, half or whole memory
array
■High-speed clock: 20 MHz
■Single supply voltage:
– 2.5 V to 5.5 V for M95320-W
– 1.8 V to 5.5 V for M95320-R
– 1.7 V to 5.5 V for M95320-DF
■Operating temperature range: from -40°C up to
+85°C
■Enhanced ESD protection
■More than 4 million Write cycles
■More than 200-year data retention
■Packages
– RoHS compliant and halogen-free
(ECOPACK®)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8
2 × 3 mm (MLP)
www.st.com
Contents M95320-W M95320-R M95320-DF
2/46 Doc ID 5711 Rev 15
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M95320-W M95320-R M95320-DF Contents
Doc ID 5711 Rev 15 3/46
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Read Identification Page (available only in M95320-D devices) . . . . . . . . 26
6.8 Write Identification Page (available only in M95320-D devices) . . . . . . . . 27
6.9 Read Lock Status (available only in M95320-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95320-D devices) . . . . . . . . . . . . . . . . . . . . . 29
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
List of tables M95320-W M95320-R M95320-DF
4/46 Doc ID 5711 Rev 15
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. M95320-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Operating conditions (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Operating conditions (M95320-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Operating conditions (M95320-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. DC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. DC characteristics (M95320-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. DC characteristics (M95320-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. AC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. AC characteristics (M95320-R, M95320-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41
Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 42
Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
M95320-W M95320-R M95320-DF List of figures
Doc ID 5711 Rev 15 5/46
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41
Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 43
Description M95320-W M95320-R M95320-DF
6/46 Doc ID 5711 Rev 15
1 Description
The M95320 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 4096 x 8 bits, accessed through the SPI bus.
The M95320 devices can operate with a supply range from 1.7 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95320-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
The SPI bus signals are C, D and Q, as shown in Figure 1 and Ta bl e 1 . The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data Input Input
Q Serial Data Output Output
SChip Select Input
WWrite Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
M95320-W M95320-R M95320-DF Description
Doc ID 5711 Rev 15 7/46
Figure 2. 8-pin package connections (top view)
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
DVSS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
Memory organization M95320-W M95320-R M95320-DF
8/46 Doc ID 5711 Rev 15
2 Memory organization
The memory is organized as shown in the following figure.
Figure 3. Block diagram
-36
(/,$
3
7#ONTROLLOGIC (IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
#
$
1
3IZEOFTHE
2EADONLY
%%02/-
AREA
3TATUS
REGISTER
)DENTIFICATIONPAGE


M95320-W M95320-R M95320-DF Signal description
Doc ID 5711 Rev 15 9/46
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
Signal description M95320-W M95320-R M95320-DF
10/46 Doc ID 5711 Rev 15
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 VCC supply voltage
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
M95320-W M95320-R M95320-DF Connecting to the SPI bus
Doc ID 5711 Rev 15 11/46
4 Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
Connecting to the SPI bus M95320-W M95320-R M95320-DF
12/46 Doc ID 5711 Rev 15
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M95320-W M95320-R M95320-DF Operating features
Doc ID 5711 Rev 15 13/46
5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
●in Standby Power mode,
●deselected,
●Status Register values:
– The Write Enable Latch (WEL) bit is reset to 0.
– The Write In Progress (WIP) bit is reset to 0.
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
Operating features M95320-W M95320-R M95320-DF
14/46 Doc ID 5711 Rev 15
5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
●deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
●in Standby Power mode (there should not be any internal write cycle in progress).
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)
Figure 6. Hold condition activation
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
ai02029E
c
HOLD
Hold
condition
Hold
condition
M95320-W M95320-R M95320-DF Operating features
Doc ID 5711 Rev 15 15/46
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms:
●Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
●All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
●The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
●The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 none none
0 1 Upper quarter 0C00h - 0FFFh
1 0 Upper half 0800h - 0FFFh
1 1 Whole memory 0000h - 0FFFh
Instructions M95320-W M95320-R M95320-DF
16/46 Doc ID 5711 Rev 15
6 Instructions
Each instruction starts with a single-byte code, as summarized in Ta b l e 4 .
If an invalid instruction is sent (one not contained in Ta b le 4 ), the device automatically
deselects itself.
Table 3. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Table 4. M95320-D instruction set
Instruction Description Instruction
format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Read Identification
Page Reads the page dedicated to identification. 1000 0011(1)
1. Address bit A10 must be 0, all other address bits are Don't Care.
Write Identification
Page Writes the page dedicated to identification. 1000 0010(1)
Read Lock Status Reads the lock status of the Identification Page. 1000 0011(2)
2. Address bit A10 must be 1, all other address bits are Don't Care.
Lock ID Locks the Identification page in read-only mode. 1000 0010(2)
Table 5. Address range bits
Address significant bits A11-A0(1)
1. Upper MSBs are Don’t Care.
M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 17/46
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7. Write Enable (WREN) sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M95320-W M95320-R M95320-DF
18/46 Doc ID 5711 Rev 15
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●Power-up
●WRDI instruction execution
●WRSR instruction completion
●WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 19/46
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
Figure 9. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●Power-up
●Write Disable (WRDI) instruction completion
●Write Status Register (WRSR) instruction completion
●Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Ta b l e 2 ) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M95320-W M95320-R M95320-DF
20/46 Doc ID 5711 Rev 15
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.
Figure 10. Write Status Register (WRSR) sequence
Table 6. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 21/46
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Ta bl e 2 .
●The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Ta b l e 7 . When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
The protection features of the device are summarized in Ta bl e 7 .
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
Table 7. Protection modes
W
signal
SRWD
bit Mode Write protection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
Unprotected area(1)
10
Software-
protected
(SPM)
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Write-protected Ready to accept
Write instructions
00
11
01
Hardware-
protected
(HPM)
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Write-protected Ready to accept
Write instructions
Instructions M95320-W M95320-R M95320-DF
22/46 Doc ID 5711 Rev 15
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
●If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●either setting the SRWD bit after driving the Write Protect (W) input pin low,
●or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
6.5 Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
Figure 11. Read from Memory Array (READ) sequence
M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 23/46
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6 Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
Figure 12. Byte Write (WRITE) sequence
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
Instructions M95320-W M95320-R M95320-DF
24/46 Doc ID 5711 Rev 15
The instruction is not accepted, and is not executed, under the following conditions:
●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
●if a Write cycle is already in progress,
●if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
Figure 13. Page Write (WRITE) sequence
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 25/46
6.6.1 Cycling with Error Correction Code (ECC)
M95320-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic
function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(c). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Ta bl e 1 4 .
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
Instructions M95320-W M95320-R M95320-DF
26/46 Doc ID 5711 Rev 15
6.7 Read Identification Page (available only in M95320-D
devices)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Ta bl e 4 ).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper
address bits are Don't Care, and the data byte pointed to by the lower address bits [A4:A0]
is shifted out on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the
internal address register is automatically incremented, and the byte of data at the new
address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the ID page from location 10d, the number of
bytes should be less than or equal to 22d, as the ID page boundary is 32 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 14. Read Identification Page sequence
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M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 27/46
6.8 Write Identification Page (available only in M95320-D
devices)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Tabl e 4 ). The
Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and
at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must be
0, upper address bits are Don't Care, the lower address bits [A4:A0] address bits define the
byte address inside the identification page. The instruction sequence is shown in Figure 15.
Figure 15. Write identification page sequence
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Instructions M95320-W M95320-R M95320-DF
28/46 Doc ID 5711 Rev 15
6.9 Read Lock Status (available only in M95320-D devices)
The Read Lock Status instruction (see Ta b l e 4 ) is used to check whether the Identification
Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with
the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are
then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are
Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data
Output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip
Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is
terminated by driving Chip Select (S) high.
The instruction sequence is shown in Figure 16.
Figure 16. Read Lock Status sequence
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M95320-W M95320-R M95320-DF Instructions
Doc ID 5711 Rev 15 29/46
6.10 Lock ID (available only in M95320-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is tW (as specified in AC characteristics in Section 9: DC and AC
parameters). The instruction sequence is shown in Figure 17.
The instruction is discarded, and is not executed, under the following conditions:
●If a Write cycle is already in progress,
●If the Block Protect bits (BP1,BP0) = (1,1),
●If a rising edge on Chip Select (S) happens outside of a byte boundary.
Figure 17. Lock ID sequence
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Power-up and delivery state M95320-W M95320-R M95320-DF
30/46 Doc ID 5711 Rev 15
7 Power-up and delivery state
7.1 Power-up state
After power-up, the device is in the following state:
●Standby power mode,
●deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●not in the Hold condition,
●the Write Enable Latch (WEL) is reset to 0,
●Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
M95320-W M95320-R M95320-DF Maximum rating
Doc ID 5711 Rev 15 31/46
8 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1)
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VOOutput voltage –0.50 VCC+0.6 V
VIInput voltage –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1) 5 mA
VESD Electrostatic discharge voltage (human body model)(2)
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
4000 V
DC and AC parameters M95320-W M95320-R M95320-DF
32/46 Doc ID 5711 Rev 15
9 DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Figure 18. AC measurement I/O waveform
Table 9. Operating conditions (M95320-W, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
Table 10. Operating conditions (M95320-R, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
Table 11. Operating conditions (M95320-DF, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TAAmbient operating temperature –40 85 °C
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 30 pF
Input rise and fall times 25 ns
Input pulse voltages 0.2 VCC to 0.8 VCC V
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V
!)#
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)NPUTVOLTAGELEVELS
M95320-W M95320-R M95320-DF DC and AC parameters
Doc ID 5711 Rev 15 33/46
Table 13. Capacitance
Symbol Parameter Test conditions(1)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Min. Max. Unit
COUT Output capacitance (Q) VOUT = 0 V 8 pF
CIN
Input capacitance (D) VIN = 0 V 8 pF
Input capacitance (other pins) VIN = 0 V 6 pF
Table 14. Cycling performance by groups of four bytes
Symbol Parameter(1)
1. Cycling performance for products identified by process letter K.
Test conditions Min. Max. Unit
Ncycle Write cycle endurance(2)
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
TA ≤ 25 °C,
VCC(min) < VCC < VCC(max) 4,000,000
Write cycle(3)
3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is
decoded. When using the Byte Write, the Page Write or the WRID instruction, refer also to Section 6.6.1:
Cycling with Error Correction Code (ECC).
TA = 85 °C,
VCC(min) < VCC < VCC(max) 1,200,000
Table 15. Memory cell data retention
Parameter Test conditions Min. Unit
Data retention(1)
1. For products identified by process letter K. The data retention behavior is checked in production. The 200-
year limit is defined from characterization and qualification results.
TA = 55 °C 200 Year
DC and AC parameters M95320-W M95320-R M95320-DF
34/46 Doc ID 5711 Rev 15
Table 16. DC characteristics (M95320-W, device grade 6)
Symbol Parameter Test conditions in addition to those
defined in Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC = 2.5 V, fC = 5 MHz,
C=0.1V
CC/0.9 VCC, Q = open 3
mA
VCC = 2.5 V, fC = 10 MHz,
C=0.1V
CC/0.9 VCC, Q = open 2(1)
VCC = 3.0 V, fC = 10 MHz
C=0.1V
CC/0.9 VCC, Q = open 4
VCC =5.5V, f
C = 20 MHz,
C=0.1V
CC/0.9 VCC, Q = open 5(1)
1. Only for the device identified by process letter K.
ICC0(2)
2. Characterized only, not tested in production.
Supply current
(Write) During tW, S = VCC, 2.5 V < VCC < 5.5 V 5 mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5.5 V
VIN = VSS or VCC
3(1)
µA
S = VCC, VCC = 5.0 V
VIN = VSS or VCC
2
S = VCC, VCC = 2.5 V
VIN = VSS or VCC
1(3)
3. 2 µA with the device identified by process letter K.
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH Output high voltage VCC = 2.5 V and IOH = 0.4 mA or
VCC = 5 V and IOH = 2 mA 0.8 VCC V
VRES(2) Internal reset
threshold voltage 1.0(4)
4. 0.7 V with the device identified by process letter K.
1.65(5)
5. 1.3 V with the device identified by process letter K.
V
M95320-W M95320-R M95320-DF DC and AC parameters
Doc ID 5711 Rev 15 35/46
Table 17. DC characteristics (M95320-R, device grade 6)
Symbol Parameter Test conditions(1) Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, voltage applied on Q = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC = 1.8 V, max clock frequency (fC),
C = 0.1VCC/0.9VCC, Q = open 2
mA
VCC = 1.8 V, fC = 5 MHz,
C = 0.1VCC/0.9VCC, Q = open 2(2)
ICC0(3) Supply current
(Write) VCC = 1.8 V, during tW, S = VCC 5mA
ICC1
Supply current
(Standby) VCC = 1.8 V, S = VCC, VIN = VSS or VCC 1µA
VIL Input low voltage 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIH Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V
VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V
VRES(3) Internal reset
threshold voltage 1.0(4) 1.65(5) V
1. If the application uses the M95320-R device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 16:
DC characteristics (M95320-W, device grade 6), rather than to the above table.
2. For the device identified by process letter K.
3. Characterized only, not tested in production.
4. 0.7 V with the device identified by process letter K.
5. 1.3 V with the device identified by process letter K.
DC and AC parameters M95320-W M95320-R M95320-DF
36/46 Doc ID 5711 Rev 15
Table 18. DC characteristics (M95320-DF, device grade 6)
Symbol Parameter Test conditions (1) Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, voltage applied on Q = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC = 1.7 V, max clock frequency (fC),
C = 0.1 VCC/0.9 VCC, Q = open 2
mA
VCC = 1.7 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open 2
ICC0(2) Supply current
(Write) VCC = 1.7 V, during tW, S = VCC 5mA
ICC1
Supply current
(Standby) VCC = 1.7 V, S = VCC, VIN = VSS or VCC 1µA
VIL Input low voltage 1.7 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIH Input high voltage 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V
VOL Output low voltage IOL = 0.15 mA, VCC = 1.7 V 0.3 V
VOH Output high voltage IOH = –0.1 mA, VCC = 1.7 V 0.8 VCC V
VRES(2) Internal reset
threshold voltage 1.0 1.65 V
1. If the application uses the M95320-DF devices at 2.5 V ≤ V
CC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer to Table 16:
DC characteristics (M95320-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
M95320-W M95320-R M95320-DF DC and AC parameters
Doc ID 5711 Rev 15 37/46
Table 19. AC characteristics (M95320-W, device grade 6)
Test conditions specified in Tabl e 10 and Table 1 2
Symbol Alt. Parameter
VCC = 2.5 to 5.5 V New products
VCC = 4.5 to 5.5 V Unit
Min. Max. Min. Max.
fCfSCK Clock frequency D.C. 10 D.C. 20 MHz
tSLCH tCSS1 S active setup time 30 15 ns
tSHCH tCSS2 S not active setup time 30 15 ns
tSHSL tCS S deselect time 40 20 ns
tCHSH tCSH S active hold time 30 15 ns
tCHSL S not active hold time 30 15 ns
tCH(1) tCLH Clock high time 42 20 ns
tCL(1) tCLL Clock low time 40 20 ns
tCLCH(2) tRC Clock rise time 2 2 µs
tCHCL(2) tFC Clock fall time 2 2 µs
tDVCH tDSU Data in setup time 10 5 ns
tCHDX tDH Data in hold time 10 10 ns
tHHCH Clock low hold time after HOLD not active 30 15 ns
tHLCH Clock low hold time after HOLD active 30 15 ns
tCLHL Clock low set-up time before HOLD active 0 0 ns
tCLHH Clock low set-up time before HOLD not active 0 0 ns
tSHQZ(2) tDIS Output disable time 40 20 ns
tCLQV(3) tVClock low to output valid 40 20 ns
tCLQX tHO Output hold time 0 0 ns
tQLQH(2) tRO Output rise time 40 20 ns
tQHQL(2) tFO Output fall time 40 20 ns
tHHQV tLZ HOLD high to output valid 40 20 ns
tHLQZ(2) tHZ HOLD low to output high-Z 40 20 ns
tWtWC Write time 5 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
DC and AC parameters M95320-W M95320-R M95320-DF
38/46 Doc ID 5711 Rev 15
Table 20. AC characteristics (M95320-R, M95320-DF, device grade 6)
Test conditions specified in Table 10 and Table 12(1)
1. If the application uses the M95320-R or M95320-DF at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C,
please refer t to Table 19: AC characteristics (M95320-W, device grade 6) rather than to the above table.
Symbol Alt. Parameter Min. Max. Unit
fCfSCK Clock frequency D.C. 5 MHz
tSLCH tCSS1 S active setup time 60 ns
tSHCH tCSS2 S not active setup time 60 ns
tSHSL tCS S deselect time 90 ns
tCHSH tCSH S active hold time 60 ns
tCHSL S not active hold time 60 ns
tCH(2)
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
tCLH Clock high time 90 ns
tCL(2) tCLL Clock low time 90 ns
tCLCH(3)
3. Characterized only, not tested in production.
tRC Clock rise time 2 µs
tCHCL(3) tFC Clock fall time 2 µs
tDVCH tDSU Data in setup time 20 ns
tCHDX tDH Data in hold time 20 ns
tHHCH Clock low hold time after HOLD not active 60 ns
tHLCH Clock low hold time after HOLD active 60 ns
tCLHL Clock low set-up time before HOLD active 0 ns
tCLHH Clock low set-up time before HOLD not active 0 ns
tSHQZ(3) tDIS Output disable time 80 ns
tCLQV tVClock low to output valid 80 ns
tCLQX tHO Output hold time 0 ns
tQLQH(3) tRO Output rise time 80 ns
tQHQL(3) tFO Output fall time 80 ns
tHHQV tLZ HOLD high to output valid 80 ns
tHLQZ(3) tHZ HOLD low to output high-Z 80 ns
tWtWC Write time 5 ms
M95320-W M95320-R M95320-DF DC and AC parameters
Doc ID 5711 Rev 15 39/46
Figure 19. Serial input timing
Figure 20. Hold timing
C
D
AI01447d
S
MSB IN
Q
tDVCH
High impedance
LSB IN
tSLCH
tCHDX
tCLCH
tSHCH
tSHSL
tCHSHtCHSL tCH
tCL
tCHCL
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
DC and AC parameters M95320-W M95320-R M95320-DF
40/46 Doc ID 5711 Rev 15
Figure 21. Serial output timing
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
M95320-W M95320-R M95320-DF Package mechanical data
Doc ID 5711 Rev 15 41/46
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0°8° 0°8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package mechanical data M95320-W M95320-R M95320-DF
42/46 Doc ID 5711 Rev 15
Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
N8 8
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M95320-W M95320-R M95320-DF Package mechanical data
Doc ID 5711 Rev 15 43/46
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
eee(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
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Part numbering M95320-W M95320-R M95320-DF
44/46 Doc ID 5711 Rev 15
11 Part numbering
Table 24. Ordering information scheme
Example: M95320 W MN 6 T P /P
Device type
M95 = SPI serial access EEPROM
Device function
320 = 32 Kbit (4096 x 8)
320-D = 32 Kbit plus Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = MLP8 (2 x 3 mm)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(1)
1. The process letters appear on the device package (marking) and on the shipment box. Please contact your
nearest ST Sales Office for further information.
/P or /K= Manufacturing technology code
M95320-W M95320-R M95320-DF Revision history
Doc ID 5711 Rev 15 45/46
12 Revision history
Table 25. Document revision history
Date Revision Changes
13-May-2011 13
Added part number M95320-DR and related explanations:
– Table 4: M95320-DR instruction set
– Section 6.7: Read Identification Page
– Section 6.9: Read Lock Status
– Section 6.10: Lock ID
– Figure 16: Read Lock Status sequence
– Figure 17: Lock ID sequence
Updated:
– Features
– Section 1: Description
– Section 6.4: Write Status Register (WRSR)
– Section 6.6: Write to Memory Array (WRITE)
– Table 8: Absolute maximum ratings
– Table 40: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 x 3 mm, data
– All tables in Section 9: DC and AC parameters
– Section 11: Part numbering
–Figure 27: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no
lead, package outline.
29-May-2012 14
Datasheet split into:
– M95320-W, M95320-R, M95320-DR (this datasheet) for standard
products (range 6),
– M95320-125 datasheet for automotive products (range 3).
12-Nov-2012 15
Removed:
– M95320-DR product
– MLP rev B package
Added:
– M95320-DF product
Updated:
–Section 7.2: Initial delivery state.
M95320-W M95320-R M95320-DF
46/46 Doc ID 5711 Rev 15
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