2013-2018 Microchip Technology Inc. DS80000588K-page 1
PIC32MZ EMBEDDED
CONNECTIVITY (EC)
The PIC32MZ Embedded Connectivity (EC) family of
devices that you have received conform functionally to
the current Device Data S heet (DS60001191G), except
for the anomalies described in this doc ument.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document w ill be addressed
in future revisions of the PIC32MZ Embedded
Connectivity (EC) family si licon.
Data Sheet clarifications and corrections (if applicable)
start on page 19, following the discussion of silicon
issues.
The silicon revision level can be identified using the
current version of MPLAB
®
X IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
www.microchip.com.
For example, to identify the silicon revision level
using MPLAB X IDE in conjunction with a hardware
debugger, follow these steps:
1. Using the appropriate interface, connect the
device to the hardware deb ugger.
2. Open an MPLAB X IDE project.
3. Configure the MPLAB X IDE project for the
appropriate device and hardware debugger .
4. Select W indow > Dashboa rd, and then clic k
the Refresh Debug Tool Status icon
().
5. The part number, and the Device and
Revision ID values appear in the Output
window.
The Device and Revision ID values for the various
PIC32MZ Embedded Connectivity (EC) family silicon
revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A5).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A3 A4 A5
PIC32MZ1024ECG064 0x05103053
0x3 0x4 0x5
PIC32MZ1024ECH064 0x05108053
PIC32MZ1024ECM064 0x05130053
PIC32MZ2048ECG064 0x05104053
PIC32MZ2048ECH064 0x05109053
PIC32MZ2048ECM064 0x05131053
PIC32MZ1024ECG100 0x0510D053
PIC32MZ1024ECH100 0x05112053
PIC32MZ1024ECM100 0x0513A053
PIC32MZ2048ECG100 0x0510E053
PIC32MZ2048ECH100 0x05113053
PIC32MZ2048ECM100 0x0513B053
Note 1: Refer to the “Mem ory O rgani zation” and “Special Features” chapters in the current Device Data Sheet
(DS60001191G) for detailed information on Device and Revision IDs for your specific device.
PIC32MZ Embedded Connectivity (EC) Family
Silicon Errata and Data Sheet Clarification
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 2 2013-2018 Microchip Technology Inc.
PIC32MZ1024ECG124 0x05117053
0x3 0x4 0x5
PIC32MZ1024ECH124 0x0511C053
PIC32MZ1024ECM124 0x05144053
PIC32MZ2048ECG124 0x05118053
PIC32MZ2048ECH124 0x0511D053
PIC32MZ2048ECM124 0x05145053
PIC32MZ1024ECG144 0x05121053
PIC32MZ1024ECH144 0x05126053
PIC32MZ1024ECM144 0x0514E053
PIC32MZ2048ECG144 0x05122053
PIC32MZ2048ECH144 0x05127053
PIC32MZ2048ECM144 0x0514F053
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A3 A4 A5
Note 1: Refer to the “Mem ory O rgani zation” and “Special Features” chapters in the current Device Data Sheet
(DS60001191G) for detailed information on Device and Revision IDs for your specific device.
2013-2018 Microchip Technology Inc. DS80000588K-page 3
PIC32MZ EMBEDDED CONNECTIVITY (EC)
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item Issue Summary
Affected
Revisions
(1)
A3 A4 A5
ADC INT0 T r igger 1.
When using INT0 as a trigger source for ADC conversion, the
INT0EP bit in the INTC ON regi ster co ntrols whi ch edge triggers
the conversion (rising or falling). However, only a rising edge
will trigger the conversion.
XXX
ADC Data Format 2. Two’s complement (signed) input mode does not produce
expected results. XXX
Boot Flash Boot Sequence 3. When Boot Flash 1 is selected to be mapped to a Lower Boot
Alias memory, the device may instead incorrectly map Boot
Flash 2. XXX
Comparator
Voltage
Reference
Range
Selection 4. The Comparator Voltage Reference (CV
REF
) module range
selectio n (CVRR bit in the CVRC ON registe r) does not function. X X X
Ethernet
Controller
Alternate MII
and RMII
Configurations 5. The Alternate Ethernet pins, AERXDV and AERXCLK, are not
available on 100-pin devices. X X X
Ethernet
Controller MII
Configuration 6. MII mode is not available on 64-pin devices. XXX
Ethernet
Controller RMII Mode 7. MII pins that are not used by the Ethernet module during RMII
operation may not be available for other functions. XXX
I/O Port Op en Dr ain 8.
The Open Drain selection (ODCx) on I/O port pins is not
available when the pin is configured for anything other than a
standard po rt output. th e Open Drain featu re is not av ailab le for
dedicated or remappable Peri pheral Pin Select (PPS) output
features.
XXX
Oscillator FRC T uning 9. Changing values in the OSCTUN register has no effect on the
FRC accuracy. XXX
Oscillator Ceramic
Resonator 10. The Ceramic Resonator cannot be used as an input to the
Oscillator module (OSC1/OSC2 pins). XXX
Secondary
Oscillator Crystal
Oscillator 11. A crystal oscillator cannot be used as the input to the
Secondary Os c ill ato r (SOSCI/SO SC O pins). XXX
Reserved —12. — ———
Power-
Saving
Modes Dream Mode 13. Dream mode does not function. XXX
Power-
Saving
Modes Sleep Mode 14. The device may not exit Sleep mode. XXX
SPI Maximum
Speed
Operation 15. The SPI clock speed does not meet the published specification. XXX
Reserved —16. — ———
System Bus Permission
Access 17. When Perm is si on Acces s i s en ab led , an y a cc ess by an in itiator
that is not allowed will not succeed; however, the status
registers may not accurately report the violations. XXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 4 2013-2018 Microchip Technology Inc.
USB Suspend Mo de 18. The USB module will not function if the device enters Sleep
mode and the USB PHY is turned off by setting the USBSSEN
bit in the CFGCON regis ter to ‘1’. XXX
USB —19. The USB module requires a start-up delay. X X X
USB Endpoint FIFO 20. Endpoint FIFOs cannot be read using 32-bit reads. X X X
Reserved —21. — ———
Watchdog
Timer Window Mode 22. When the Watchdog Timer is used in Window mode, the
module may issue a Reset even if the user tries to clear the
module w ithin the allo wed window. XXX
Watchdog
Timer Reset Trigger 23. When the Watchdog Timer expires during Sleep mode, it
ca uses a Reset rather than a nonmaskabl e interrupt (NMI). XXX
PMP Address Lines 24. PMP add r ess lines block the use of lower-order func tio ns when
the PMP is used but the corresponding bit in the PMAEN
register is cleared. XXX
I
2
CMaster Stop 25. The hardware Master Stop control does not function. X X X
Crypto
Engine Byte Ordering 26. The Crypto Engine processes data in big-endian order rather
than little-endian. XXX
Random
Number
Generator
True Random
Number
Generator
(TRNG) Mode
27.
TRNG mode does not function.
XXX
Flash Code-Protect 28. Once the Code-Protect feature is enabled, a device cannot be
erased using ICSP™ or JTAG. X
ADC Group Interrupt 29. When using Channel Scan, Clas s 3 inputs are always part of
the Group Interrupt regardless of the setting of the AGIENx bits
in the AD1IRQENx register. XXX
SQI Soft Reset 30. A Soft Reset is only possible when clock divider values are ‘0’
and ‘1’. XXX
SQI XIP Mode 31. XIP mode is not ope rational. X X X
SQI Buffer
Thresholds 32. Transmit and receive operation may not function properly. XXX
SQI Interrupts 33. Some Interrupt Signal Enable bits are set upon a Reset. X X X
SQI Read Clock
Speed 34. Clock for read operations does not meet the published
specification. XXX
SQI Transmit Buffer
Empty Status 35. Upon a reset, the Transmit Buffer Empty Status (TXEMPTYIF)
bit in the SQI1INTSTAT register is cleared to zero instead of
being set to one. XXX
Reserved —36. — ———
Comparator Offset 37. The Comparator offset does not meet the published
specification XXX
I/O Pins SOSCO
Function 38. I/O pins shared wi th the SOSCO function cannot be used as
general purpose input or output. XXX
I
2
COverrun
Interrupt 39. A Slav e interru pt is not generated during an overrun conditio n. XXX
Flash
Memory Program Write
Protect 40. The Program Write Protect (PWP) bits protect all Program
Memory. XXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected
Revisions
(1)
A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2013-2018 Microchip Technology Inc. DS80000588K-page 5
PIC32MZ EMBEDDED CONNECTIVITY (EC)
Oscillator P
OSC
41. A crystal oscillator cannot be used as an input to the Primary
Oscillator (OSC1/OSC2 pins). XX
5V Toler ant
I/O Pins Pull-ups 42. Internal pull-up resistors may not guarant ee a lo gical ‘1’ on
digital inputs on 5V tolerant pins. XXX
ADC —43. Certain ADC operating modes are not supported. X X X
ADC —44. The ADC module does not meet published specifications. X X X
Prefetch Module Disable 45. Disabling the Prefetch does not invalidate contents. X X X
Oscillator Clock Switch 46. Switching the System Clock (SYSCLK) to the Secondary PLL
(SPLL) causes a device Reset. This affects both software and
hardware (IESO) clock switch ing. XXX
DMA Interrupt Trigge r 47. A UART6 Transfer Done interrupt cannot be used to trigger
DMA activity. XXX
UART Auto-baud 48. The Automatic Baud Rate feature does not function to set the
baud rate. XXX
Reserved —49. — ———
Oscillator POSC Crystal 50. Crystal support for the Primary Oscillator does not meet
published specifications for frequency and voltage. XXX
Reserved —51. — ———
I
2
CSDA Hold Time 52. Lengthening the SDA hold time causes bus collisions in 1 MHz
mode. XXX
System Bus Simultaneous
Access 53. CAN data may become corrupted during si multaneous
operation. XXX
Reserved —54. — ———
Oscillator Reference
Clock 55. The Referenc e Clock ca nnot use in put frequen cies greater th an
100 MHz. XXX
UART Synchronization 56. On a RX FIFO overflow, shift registers stop receiving data,
which causes the UART to lose synchronization. XXX
Timer1 Prescaler 57. Timer1 will not generate interrupts with an external
asynchronous clock input and prescaler other than 1:1. XXX
PMP Read 58. A PMP read does not generate an interrupt when the WAITE
bit = 0.XXX
PMP Wai t Cycle 59. The pulse width of WAITE is ‘0’ when the WAITM<3:0>
bits = 0000.XXX
Reserved —60. — ———
Watchdog
Timer Clearing 61. Clearing the Watchdog Timer does not function as specified in
the data sheet. XXX
Flash Panel Swap 62. The NVMKEY unlock sequence is not required to change the
Flash panel orde r. XXX
Resets SWNMI bit 63. The software nonmaskable interrupt (NMI) feature does not
function. XXX
Crypto
Engine Partial Packet 64. The Crypto engine does not support partial packet processing. XXX
Crypto
Engine Zero Length
Packet 65. Zero length packet fails to process as the Crypto engine does
not support an empty string hash. XXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected
Revisions
(1)
A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 6 2013-2018 Microchip Technology Inc.
Silicon Errat a Issues
1. Module: ADC
When using INT0 as a trigger source for ADC
convers ion, the IN T0EP b it in the INTCON reg ister
controls which edge tri ggers the con version (ri sing
or falling). However, only a rising edge wi ll trigger
the conversion.
Work around
None.
Affected Silicon Revisions
2. Module: ADC
Two’s complement (signed) input mode does not
produce the expected results. Signed mode
selections are SHxMOD<1:0> = 01 for single-
ended or SHxMOD<1:0> = 11 for differential
inputs.
Work arounds:
Work around 1
Use two's complement format for all inputs. The
Two's c omplement for ma t works properly when all
sample and holds are set for this format. Single-
ended or Differential mode can still be selected
independently. Use any one of the following
settings for SH0MOD through SH5MOD:
• SHxMOD<1:0> = 01 for signed single-ended
• SHxMOD<1:0> = 11 for si gned differential
inputs
Work around 2
Use unipolar (unsigned) mode selections for all
sample and holds. Where needed, convert the
unsigne d results to s igned value s. Unsign ed 12-bit
results can be converted to signed values by
subtracting 2048 from the signed result. Use any
one of the following settings for SH0MOD through
SH5MOD:
• SHxMOD<1:0> = 00 for unsigned single-ended
• SHxMOD<1:0> = 10 for unsigned differential
inputs
Affected Silicon Revisions
3. Module: Boot Flash
When Boot Flash 1 is selected to be mapped to a
Lower Boot Alias mem ory, the device may ins tead
incorrectly map Boot Flash 2.
Work around
Program an invalid sequence number, such as
0xFFFFFFFF or 0x00000000 into Boot Flash 2.
This will force the device to map Boot Flas h 1 into
the Lower Boot Alias memory.
Affected Silicon Revisions
4. Module: Comparator Voltage Reference
The Comparator Voltage Reference (CV
REF
)
module range selection (CVRR bit in the CVRCON
register) does not function. The default setting of
the CV
REF
Range Selection bit (CVRR) is set to
0to0.67 CV
RSRC
, with a step size of CV
RSRC
/24,
and cannot be changed.
Work around
Use an External Voltage Reference and adjust it
appropriately to achieve the desired CV
REF
output.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 7
PIC32MZ EMBEDDED CONNECTIVITY (EC)
5. Module: Ethernet Controller
The Alternate Ethernet pins, AERXDV and
AERXCLK, are not available on 100-pin devices.
Work around
Only use either the MII or RMII configuration.
Affected Silicon Revisions
6. Module: Ethernet Controller
MII mod e is not available o n 64-pin d evices. In this
mode, the Ethernet pin ERXD2, is not available.
Work around
Use the RMII or Alte rnate RMII configurations.
Affected Silicon Revisions
7. Module: Ethernet Controller
MII pins that are not used by the Ethernet module
during RMII operation are not released, and
therefore, lower priority functions on these pins are
not avail able in this mode. Howe ver , higher priorit y
functions on these pins, such as EBI and analog
inputs (for ADC and Comparators), can still be
used.
Work around
None.
Affected Silicon Revisions
8. Module: I/O Port
The Ope n D rai n s ele cti on (OD Cx ) on I /O port pins
is not available when the pin is configured for
anything other than a standard port output. the
Open Drain feature is not available for dedicated
or remappa ble Perip hera l Pin Selec t (PPS) output
features.
Work around
None.
Affected Silicon Revisions
9. Module: Oscillator
Changing values in the OSCTUN register has no
effect on the FRC accuracy.
Work around
None.
Affected Silicon Revisions
10. Module: Oscillator
The Ceramic Resonator cannot be used as an
input to the Oscillator module (OSC1/OSC2 pins).
Work around
Instead, use either a crystal oscillator or the
external clock.
Affected Silicon Revisions
11. Module: Secondary Oscilla tor
A crystal oscillator cannot be used as the input to
the Secondary Oscillator (SOSCI/SOSCO pins).
Work around
Instead, use the external clock.
Affected Silicon Revisions
12. Module: Reserved
The iss ue p rev iously reported in a p rior revision of
this errata is no longer relevant and was removed.
13. Module: Power-Saving Modes
Dream mode is intended as a feature allowing
DMA operation while the CPU is in Idle mode;
however, Dream mode does not function.
Work around
None.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 8 2013-2018 Microchip Technology Inc.
14. Module: Power-Saving Modes
The device may not exit Sleep mode.
Work arounds
Enable Flash in Sleep mode by clearing the Flash
Sleep Mode Configuration bit, FSLEEP, in the
DEVCFG0/ADEVCFG0 configuration register.
Affected Silicon Revisions
15. Module: SPI
The SPI clock speed does not meet the published
specification. The maximum supported SPI clock
speed is 27 MHz.
Work around
None.
Affected Silicon Revisions
16. Module: Reserved
The iss ue p rev iou sl y re port ed i n a p rio r rev is ion of
this e rrata i s no longer relevan t a nd w as re mo ve d.
17. Module: System Bus
When Permission Access is enabled, any access
by an initiator that is not allowed will not succeed;
however, the status registers may not accurately
report the violations.
Work around
None.
Affected Silicon Revisions
18. Module: USB
The USB module will not function if the device
enters Sl eep mo de a nd the USB PH Y i s tu rne d off
by setting the USBSSEN bit in the CFGCON
register to ‘1’.
Work around
Keep the USB PH Y operational in Sleep mode by
setting the USBSSEN bit to ‘0’.
Affected Silicon Revisions
19. Module: USB
The USB module requires a start-up delay.
Work around
When enabling the USB PLL, add a three second
delay before turning on the USB module.
Affected Silicon Revisions
20. Module: USB
Endpoint FIFOs cannot be read using 32 -bit reads.
Work around
Use 8- bit read s, reading each portion and copy in g
into a 32-bit value.
Affected Silicon Revisions
21. Module: Reserved
The iss ue p rev iously reported i n a p rior revision of
this errata is no longer relevant and was removed.
22. Module: Watchdog Timer
When the Watchdog Timer is used in Window
mode, the module may issue a Reset even if the
user tries to clear the module within the allowed
window.
Work around
None.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 9
PIC32MZ EMBEDDED CONNECTIVITY (EC)
23. Module: Watchdog Timer
When the Watchdog Timer expires during Sleep
mode, it causes a Reset rather than a
nonmaskable interrupt (NMI).
Work around
None.
Affected Silicon Revisions
24. Module: PMP
PMP address lines block the use of lower-order
functions when the PMP is used but the
corresponding bit in the PMAEN register is
cleared. For example, on 100-pin devices, pin 2 is
EBIA5/AN34/PMA5/RA5; however, clearing bit 5
of the PMAEN register does not allow RA5 to
funct ion as GP IO even th ough PMA 5 is not to be
used with the PMP.
Work around
Higher-order functions are available and should be
used instead. As described in the previous
example, EBIA5 and AN34 are available.
Affected Silicon Revisions
25. Module: I
2
C
The hardwa re Master Stop control (PEN bit) does
not function.
Work around
Instead of hardware, use software to create the
Stop condition, which involves execution of two
separate steps.
Step 1:
During I
2
C software initialization, perform the
following actions:
1. Clear the LAT bit of the SDA pin.
2. Clear the TRIS bit of the SDA pin to be
configured as an output.
3. Set the LAT bit of the SCL pin.
4. Set the TRIS bit of the SCL pin to be
configured as an input.
5. En able the I
2
C modul e by setting the ON b it
in the I2CxCON register.
6. To avoid usin g so ftw are dela y lo ops , se t up
a Timer module with an interval equivalent
to 1 BRG t ime. Load the Period register with
the value equivalent to 1 BRG time. The
Timer interrupt will occur for every 1 BRG
time period.
Step 2:
To create the Stop condition on the I
2
C bus, do
not set the PEN bit in the I2CxCON register.
Instead, a software routine should be invoked to
provide delays and manipulate the GPIO (bit-
bang) that the I
2
C pins share that would create
a Stop condition. A Stop condition occurs when
SDA goes high 1 BRG time after SCL goes
high. SCL goes high at least 1 BRG time after
receiving ACK or NACK from the slave.
When the Mater is ready to send a Stop
condition, perform the following steps to create
the Stop condition:
1. Start the Timer module.
2. After 1 BRG time period has elapsed,
disable the I
2
C module by clearing the ON
bit in the I2CxCON register.
3. After 1 more additional BRG time periods
have elapsed, change the direction of the
SDA pin to an input by setting the corre-
spondin g TRIS bit.
4. After 2 more additional BRG time periods
have elapsed, enable the I
2
C module by
setting the ON bit in the I2CxCON register.
5. Clear the LAT bit of the SDA pin.
6. Clear the TRIS bit of the SDA pin to be
configu r ed as an output.
7. Set the LAT bit of the SCL pin.
8. Set the TRIS bit of the SCL pin to be
configu r ed as input.
9. Stop the Timer module.
Disabling the I
2
C module
When users want to disable the I
2
C module for
saving power, the following steps must be
performed:
1. Set the LAT bit of the SDA pin.
2. Set the TRIS bit of the SDA pin to be con-
figured as an input.
3. Turn OFF the I
2
C module by clearing the
ON bit in the I2CxCON register.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 10 2013-2018 Microchip Technology Inc.
26. Module: Crypto Engine
The Crypto Engine processes data in big-endian
order rather than little-endian.
Use the SWAPEN bit (CECON<5>) to byte-
reverse the data on input. After the data is
process ed, it must be byte-re versed by software or
programmable DMA.
Affected Silicon Revisions
27. Module: Random Number Generator
True RNG mode does not function.
Work around
Inst ead, use Ps eudo-Ran dom Number Generato r
(PRNG) mode.
Affected Silicon Revisions
28. Module: Flash
Under normal conditions, once the Code-Protect
feature is enabled, a device cannot be accessed
(read/write) through external interfaces, such as
ICSP™ or JTAG. To gain access through these
interfaces, the Code-Protect bit must be erased
either by issuing an erase command (using
ICSP or JTAG) or with the help of RTSP code.
However, the device erase command using
ICSP or JTAG does not function once the Code-
Protect feature is enabled.
Work arounds:
Work around 1
Use the RTSP method to update code in a
Code-Protect enabled device. In this mode,
Flash memory can be erased and programmed
with desired data.
Work around 2
Use the RTSP method with the Live-Update
feature of the device to erase the Co de-Protect bit.
Using this method, the application will erase the
Code-Pro tect bit located in th e inacti ve Boot Fl ash
memory, and update this Boot Flash sequence to
a higher number versus the active Boot Flash
memory. On the next POR, Boot Flash memory
with the erased Code-Protect bit will be used to
configure the device, including Code-Protect
configuration.
Affected Silicon Revisions
29. Module: ADC
When using Channel Scan, Class 3 inputs are
always part of the group interrupt regardless of the
setting of the AGIENx bits in the AD1IRQENx
register. Conversions should only be part of the
Group interrupt if a AGIENx bit is set.
Work around
None.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
X
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 11
PIC32MZ EMBEDDED CONNECTIVITY (EC)
30. Module: SQI
A SQI Soft Reset, which is controlled by the
RESET bit in the SQI1CFG regis ter , does not work
when the CLKDIV<7:0> bits in the SQI1CLKCON
register have a value of two or higher.
Work around
Set the CLKDIV<7:0> bits to a value of zero or
one.
Affected Silicon Revisions
31. Module: SQI
XIP mode is not operational (MODE<2:0> bits =
011 in the SQI1CFG register).
Work around
Use PIO mode (MODE<2:0> bits = 001) or DMA
mode (MODE<2:0> bits = 010).
Affected Silicon Revisions
32. Module: SQI
Transmit and receive operation may not function
properly.
Work around
Set the TXCMDTHR<5:0> and RXCMDTHR<5:0>
bits in the SQI1CMDTHR register to multiples of
4 (32-bit aligned data buffers).
Affected Silicon Revisions
33. Module: SQI
The TXEMPTYISE, TXTHRISE, RXEMPTYISE,
RXTHRISE, and CONEMPTYISE Interrupt Signal
Enable bits in the SQI1INTSEN register are
enabled on a device Reset.
Work around
Clear these bits by software.
Affected Silicon Revisions
34. Module: SQI
Clock s peed for read o perations doe s not meet th e
maximum specification (SQ10) of 50 MHz. For
read operations, the maximum clock is 25 MHz.
Work around
None.
Affected Silicon Revisions
35. Module: SQI
For all resets, the Transmit Buffer Empty Status
(TXEMPTYIF) bit in the SQI1INTSTAT register is
cleared to zero instead of being set to one.
Work around
None.
Affected Silicon Revisions
36. Module: Reserved
The iss ue p rev iously reported i n a p rior revision of
this errata is no longer relevant and was removed.
37. Module: Comparator
The Input Offset Voltage parameter (D300) is not
within the published data sheet spec ification. The
typical value is ±30 mV.
Work around
None.
Affected Silicon Revisions
38. Module: I/O Pins
When the Secondary Oscillator is disabled
through the FSOSCEN bit (DEVCFG1<6>), the
SOSCO p in d oes no t tri-s tate and is d riv en t o Vss .
An I/O pi n shared with t he SOSCO funct ion cannot
be used as a general purpose input or output.
Work around
None.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 12 2013-2018 Microchip Technology Inc.
39. Module: I
2
C
When operating in Slave mode, the I
2
C module
does not trigger an interrupt when an overrun
conditi on oc curs.
Work around
Monitor the I2COV bit in the I2CxSTAT register
using software.
Affected Silicon Revisions
40. Module: Flash Memory
Under normal conditions, setting the Program
Write P rotect (PWP) bits sets a mark below which
the program memory is protected. Memory above
this se tting may be era sed or written. Ho wever , the
device protects all of program memory when any
PWP bits are set.
Work around
None.
Affected Silicon Revisions
41. Module: Oscillator
Depending on the revision of the silicon, a crystal
oscillator cannot be used as the input to the
Primary Oscillator (OSC1/OSC2 pins).
Work around
For Revision A3 and A4 silicon:
Use an external clock or an internal FRC.
For Revision A5 silicon:
See Da ta Sh eet Cla r ifi cat ion 1: Primary O scil lat or .
Affected Silicon Revisions
42. Module: 5V Tolerant I/O Pins
When internal pull-ups are enabled on 5V-tolerant
I/O pins, the level as measured on the pin and
availa ble to e xternal d evice i nputs m ay not exc eed
the minimum value of V
IH
, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as V
DD
3V and the load doesn't
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the devi ce.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inpu ts, if the external load
exceeds -50 µA or V
DD
< 3V
Affected Silicon Revisions
43. Module: ADC
The following ADC operating modes are not
supported:
• Software polling of ADC status bits
• Manual software ADC triggering
• ADC interrupt modes (use DMA Interrupt mode)
• ADC SFR accesses by the CPU while A DC is
operating
• ADC Boost or Low-Power mode.
• Individ ual ADC Input Convers ion R eque sts (i.e. ,
RQCNVRT bi t in the ADCCON3 register)
• Use of ADC S&H Channels 0-4 except for
calibration
• Any ADC references other than external V
REF
+
and V
REF
- pins
• ADC Differential mode
Work around
None.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XX
A3 A4 A5
XXX
Note: A related code example is available
in MPLAB Harmony, 1.02 or later
version. For more information, visit
http://www.micochip.com/harmony.
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 13
PIC32MZ EMBEDDED CONNECTIVITY (EC)
44. Module: ADC
For Revision A3 and A4 silicon:
The ADC module does not meet the published
Throughput Rate (AD51) and Full-Scale Input
Range (AD12) specifications. The updated
Maximum Throughput Rate (AD51) specification
is 125 ksps, assuming 16x Oversampling mode.
The updated Maximum Full-Scale Input Range
is 2.5V for both Differential and Singled-Ended
modes. The updated Minimum Full-Scale Input
Range is -2.5V f or Differential mode.
For Revision A5 silicon with date codes of
1503xxx (i.e., 1/12/15) or later:
These devices will have ADC performance as
specified in Table 3 and Table .
For Revision A5 silicon with date codes prior
to 1503xxx (i.e., 1/12 /15 ) :
These devices were not calibrated appropriately
and may not perform to the specifications
defined in Table 3 and Table .
Work around
None.
Affected Silicon Revisions
Note: A related code example is available
in MPL AB Harmony, V ersions 1.0 0 or
1.01. These versions are available in
the MPLAB Harmony archive. For
more information, visit http://
www.micochip.com/harmony.
Note: A related code example is available
in MPLAB Harmony, Version 1.02 or
later. For more information, visit:
http://www.micochip.com/harmony.
A3 A4 A5
XXX
TABLE 3: ADC1 MODULE SPECIFICATIONS
AC CHARACTERISTICS
(3,4)
Standard Operating Conditions (see Notes 2,3,4): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature 0°C T
A
+85°C
Param. Symbol Characteristics Min. Typical Max. Units Conditions
Device Supply
AD01 AV
DD
Module V
DD
Supply Gr eater of
V
DD
– 0.3
or 2.5
— Lesser of
V
DD
+ 0.3
or 3.6
V—
AD02 AV
SS
Module V
SS
Supply V
SS
—V
SS
+ 0.3 V —
Reference Input s
AD05 V
REFH
Reference Voltage High AV
SS
+ 2.0 — AV
DD
VV
REFH
= V
REF
+ (Note 1)
AD06 V
REFL
Reference Voltage Low AV
SS
—V
REFH
– 2.0 V (Note 1)
AD07 V
REF
Absolute Reference
Voltage (V
REFH
– V
REFL
)2.0 — AV
DD
V—
AD08
AD08a I
REF
Current Drain —
—100
.002 150
1A
AADC operating
ADC off
Analog Input
AD12 V
INH
-V
INL
Full-Sca le Input Range 0 — Lesser of
V
DD
– 0.6
or 2.5
V Single-ended mode only
(Differential mod e is no t
supported)
AD14 V
INCM
Common Mode Input
Voltage AV
SS
+
V
REF
/2 —AV
DD
–
V
REF
/2 V—
AD17 R
IN
Recommended
Impedance of Analog
Voltage Source
——10k For minimum samplin g
time (Note 1 )
Note 1: These parameters are not characterized or tested in manufacturing.
2: The ADC module is functional at V
BORMIN
< V
DD
< V
DDMIN
, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
3: Specifications are based on adherence to the requirem ents listed in Section 28.1 “ADC Configuration
Requirements”.
4: All data were collected using a dedicated external precision voltage source connected to V
REF
+ and with
V
REF
- tied to external AV
SS
. External V
REF
+ and V
REF
- must be used at all times.
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 14 2013-2018 Microchip Technology Inc.
ADC Ac cur ac y – Measu r eme nts wit h Exter nal V
REF
+/V
REF
-
AD20c Nr Resolution 8 data bits b its —
AD21c INL Integral Nonlinearity -5 ±3 +5 LSb V
INL
= V
REF
- = V
REFL
= 0V,
V
REF
+ = V
REFH
= 2.5V
AD22c DNL Differential Nonlinearity -1 ±1 +2 LSb V
INL
= V
REF
- = V
REFL
= 0V,
V
REF
+ = V
REFH
= 2.5V
AD23c G
ERR
Gain Error -10 ±3 +10 LSb V
INL
= V
REF
- = V
REFL
= 0V,
V
REF
+ = V
REFH
= 2.5V
AD24c E
OFF
Offset Error -9 ±1 +9 LSb V
INL
= V
REF
- = V
REFL
= 0V,
V
REF
+ = V
REFH
= 2.5V
AD25e — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal to Noise and
Distortion —42—dB —
AD34b ENOB Effective Number of bits — 7 — bits —
TABLE 3: ADC1 MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
(3,4)
Standard Operating Conditions (see Notes 2,3,4): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature 0°C T
A
+85°C
Param. Symbol Characteristics Min. Typical Max. Units Conditions
Note 1: These parameters are not characterized or tested in manufacturing.
2: The ADC module is functional at V
BORMIN
< V
DD
< V
DDMIN
, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
3: Specifications are based on adherence to the requirements listed in Section 28.1 “ADC Configuration
Requirements”.
4: All data were collected using a dedicated external precision voltage source connected to V
REF
+ and with
V
REF
- tied to external AV
SS
. External V
REF
+ and V
REF
- must be used at all times.
2013-2018 Microchip Technology Inc. DS80000588K-page 15
PIC32MZ EMBEDDED CONNECTIVITY (EC)
TABLE 4: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
(2,4,5)
Standard Operating Conditions (see Notes 3,4,5): 2.5V to 3.6V
(unless otherwise stated)
Operatin g temperature 0°C T
A
+85°C
Param.
No. Symbol Characteristics Min. Typ.
(1)
Max. Units Conditions
Clock Parameters
AD50 T
AD
ADC Clock
Period 1000 — 2000 ns —
Throughput Rate
AD51 F
TP
SH0 – SH4
(Class 1 Inputs) — — ——
SH0-SH4 functionality is not supported.
Samplin g mus t be pe rformed on SH5 on ly. (Note
3)
SH5
(Class 2 and 3
Inputs) — — 66.6 ksps
Single Class 2 or 3 input, 1 MHz ADC Clock,
Source im pedance 10 k,
SAMC = ‘b00001010, assumes there are no
pending sample conversion operations at the
time of trigger. (Note 3)
Conversion
Pipeline ——1Msps —
Timing Parameters
AD60 T
SAMP
Sample T ime
for SH0-SH4
(Class 1 Inputs) ———T
AD
SH0-SH4 functionality is not supported.
Sampling must be performed on SH5 only.
Sample T ime
for SH5
(Class 2 and 3
Inputs)
10 — — T
AD
Source Impedance 10 k, 1 MHz ADC clock
AD62 T
CONV
Conversion
Time
(after
sample ti me is
complete)
——10 T
AD
SH0-SH4 functionality is not supported.
Sampling must be performed on SH5 only.
For SH5, T
SAMP
+ T
CONV
provides Trigger to data
ready timing;
AD64 T
CAL
Calib ration Time — 160 — T
AD
—
AD65 T
WAKE
Wake-up time
from Low-
Power Mode —2—T
AD
—
Note 1: These parameters are not characterized, or tested in manufacturing.
2: The ADC module is functional at V
BORMIN
< V
DD
< V
DDMIN
, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
3: Assuming correct PLL configuration (i.e., 192 MHz system clock).
4: Specifications are based on adherence to the requirem ents listed in Section 28.1 “ADC Configuration
Requirements”.
5: All data were collected using a dedicated external precision voltage source connected to V
REF
+ and with
V
REF
- tied to external AV
SS
. External V
REF
+ and V
REF
- must be used at all times.
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 16 2013-2018 Microchip Technology Inc.
45. Module: Prefetch
The Prefetch module does not invalidate buffer
contents when the module is disabled by setting
the PREFEN<1:0> bits to ‘b00.
Work around
To disable the Prefetch module, execute four
32-bit NOP commands before and after setting
the PREFEN<1:0> bits to ‘b00.
Affected Silicon Revisions
46. Module: Oscillator
Switching the System Clock (SYSCLK) to the
System PLL (SPLL) causes a device Reset. This
affects both software and hardware (IESO) clock
switching.
Work around
To switch the clock source, disable IESO and
execute the foll owin g step s in sof tware:
1. Reduce the speed of all peripheral buses to
128:1 through PBCLKx (where ‘x’
7) and
reduce the speed of the CPU bus to 128:1
through PBCLK7.
2. Perform the clock switch.
3. Set the speed of the CPU bus to the
previous clock switch divisor and set the
speed of the peripheral buses to their
previous clock switch divisor.
Affected Silicon Revisions
47. Module: DMA
The UART6 Transfer Done Interrupt (190) cannot
be used to tri gger a DMA activit y , such as a start or
a st op.
Work around
None.
Affected Silicon Revisions
48. Module: UART
The UAR T Automatic baud rate feature is intended
to set the baud rate during run-time based on
external data input. However, this feature does not
function.
Work around
None.
Affected Silicon Revisions
49. Module: Reserved
The iss ue p rev iously reported i n a p rior revision of
this errata is no longer relevant and was removed.
50. Module: Oscillator
The Primary Oscillator does not meet the
published specifications for crystal support.
Work around
To use a crystal with the Primary Oscillator, the
following limitations on voltage and frequency
must be observed:
•2.4V V
DD
3.6V
• Cry stal Speed = 12 MHz
Additional details can be found in Data Sheet
Clarification 1: Primary Oscillator.
Affected Silicon Revisions
51. Module: Reserved
The iss ue p rev iously reported i n a p rior revision of
this errata is no longer relevant and was removed.
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 17
PIC32MZ EMBEDDED CONNECTIVITY (EC)
52. Module: I
2
C
Setting the SDAH T bit in the I
2
C modu le lengt hens
the time that the SDAx pin is held after SCLx falls
to 300 ns from 100 ns. However, the actual hold
time is longer than 300 ns, and as a result, it
causes a bus collision when operating at 1 MHz.
Work around
Do not set the SDAH T bit when operating the I
2
C
module at 1 MHz.
Affected Silicon Revisions
53. Module: System Bus
When operating the system bus at 8 MHz, having
the CAN module access one RAM bank while the
Crypto module accesses the other RAM bank can
cause the CAN data to become corrupted.
Work around
Operate the sys tem bus at freq uenci es fas ter than
8MHz.
Affected Silicon Revisions
54. Module: Reserved
The iss ue p rev iou sl y re port ed i n a p rio r rev is ion of
this e rrata i s no longer relevan t a nd w as re mo ve d.
55. Module: Oscillator
The Reference Clock Module cannot accept input
frequencies greater than 100 MHz. Therefore,
SYSCLK cannot be used as an input if the
SYSCLK operates at frequencies greater than
100 MHz.
Work around
Instead of using SYSCLK, use PBCLK1 as the
input, which is limited to 100 MHz and is
synchroniz ed to SYSCLK.
Affected Silicon Revisions
56. Module: UART
During a RX FIFO overflow condition, the shift
register stops receiving data. This causes the
UART to lose synchronization with the serial data
stream. The on ly way to rec over from this is to tu rn
the UART OFF and ON until it synchronizes. This
could require several OFF/ON sequences.
Work arounds
Work around 1:
Avoid the RX overrun condition by ensuring that
the UARTx module has a high enough interrupt
priority such that other peripheral interrupt
processing latencies do not exceed the time to
overrun the UART RX buffer based on the
application baud rate. Alternately or in addition to,
set the URXISEL bits in the UxSTA register to
generate an earlier RX interrupt based on RX
FIFO fill status to buy more time for interrupt
latency processing r equirements.
Work around 2:
If avoiding RX FIFO overruns is not possible,
implement a ACK/NAK software handshake
protocol to repeat lost packet transfers after
restoring UART synchronization.
Affected Silicon Revisions
57. Module: Timer1
T imer1 will not ge nerate interrupts wi th an external
asynch ronous clock i nput and pr escaler othe r than
1:1.
Work around
With External Clock Asynchronous mode, use the
1:1 Presc ale r m ode with a s oftw a re ti me r ov erfl ow
variable to keep track of the desired equivalent of
the greater than 1:1 prescaler setting.
Alternately, use External Synchronous Clock
mode if this is an option for the application
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 18 2013-2018 Microchip Technology Inc.
58. Module: PMP
When the PMP is set to Master mode, and the
WAITE bi t is set to ‘ 0’ to have no wait states after
the read strobe, a read operation does not
generate an interrupt.
Work around
None.
Affected Silicon Revisions
59. Module: PMP
If the WAITM<3:0> bits = 0000, the end phase
should be 1 T
PB
. Howeve r, the end phase does not
delay.
Work around
None
Affected Silicon Revisions
60. Module: Reserved
The iss ue p rev iou sl y re port ed i n a p rio r rev is ion of
this e rrata i s no longer relevan t a nd w as re mo ve d.
61. Module: Watchdog Timer
The data sheet specifies that a 16-bit write to the
WDTCLRKEY<15:0> bits is required to clear the
Watchdog Timer. However, a 16-bit write does not
work. In addition, writing to the WDTCONCLR,
WDTCON SET, and WDTCO NIN V regi ste rs cl ea rs
the Watchdog Timer, which should not occur.
Work around
Use a 32-bit write to th e WDTCON re gister to cle ar
the Watchdog Timer.
Affected Silicon Revisions
62. Module: Flash
The SWAP bit (NVMCON<7>) can be changed
without executing the NVMKEY unlock sequence.
Work around
None.
Affected Silicon Revisions
63. Module: Resets
The SWNMI bit (RNMICON<23>) in the
Nonmaskable Interrupt (NMI) Control register
does not function to trigger the NMI through
software control.
Work around
None.
Affected Silicon Revisions
64. Module: Crypto Engine
The output digest of a partial message cannot be
used as the Initial Vector for continuing the
cryptographic operation on the rest of the
message. The full message must be processed in
one operation.
Work around
None.
Affected Silicon Revisions
65. Module: Crypto Engine
The Crypto DMA does not support the hash
operation on an empty string (i.e., string with zero
length). The Crypto DMA times out and does not
return a valid hash.
Work around
Use the fixed known hash of the empty string.
Affected Silicon Revisions
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
A3 A4 A5
XXX
2013-2018 Microchip Technology Inc. DS80000588K-page 19
PIC32MZ EMBEDDED CONNECTIVITY (EC)
Data Sheet Clarifications
The foll owing ty pographic c orrections and clar ification s
are to be no ted for the latest ve rsio n of the device data
sheet (DS60001191G):
1. Module: Primary Oscillator
To use the Primary Oscillator with a crystal, only
the followi ng cry s tal is sup port ed for PIC32 MZ EC
famil y devices:
XTAL = ABLS-LR-12.000MHZ-18-D-R-T
No othe r crystals are guaranteed to funct ion 100%
over voltage, temperature, and population.
Adequate testing is required in the user application
to ensure reliable operation.
The following figure shows the required
configuration.
Note: Corrections in tables are shown in bold.
Where possible, the original bold text
formatting has been removed for clarity.
(To USB PLL)
C1 = 2 pF
C2 = 4 pF
XTAL
Enable
OSC2
OSC1
R
F
Primary Osc illa to r (P
OSC
)
4.7 M4.7 k
V
DD
To
SYSCLK
Mux
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 20 2013-2018 Microchip Technology Inc.
2. Module: Program Flash Memory Wait
States
The SYSCLK values in Table 37-13: DC
Characteristics: Program Flash Memory Wait
States were incorrectly specified. The following
table shows the correct values and symbols in
bold type.
3. Module: System Ti ming Requirements
In Table 37-18: System Timing Requirements,
the minimum System Frequency value for
parameter OS51 (F
SYS
) when the USB module is
enabled was incorrectly specified. The following
table shows the correct value in bold type.
TA B LE 37-18 : SY STE M TIMING REQU IR EME NT S
TABLE 37-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operati ng tem pera ture -40°C T
A
+85°C for Industrial
Required Flash Wait States
(1)
SYSCLK Units Conditions
With ECC:
0 Wait states
1 Wait state
2 Wait states
0 SYSCLK 60
60 < SYSCLK 120
120 < SYSCLK 200
MHz —
Without ECC:
0 Wait states
1 Wait state
2 Wait states
0 SYSCLK 74
74 < SYSCLK 140
140 < SYSCLK 200
MHz —
Note 1: To use Wait states, the PFMWS<2:0> bits must be written with the desired Wait state value.
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Indu stri al
Param.
No. Symbol Characteristics Minimum Typical Maximum Units Conditions
OS51 F
SYS
System Frequency DC — 200 MHz USB module disabled
60 — 200 MHz USB module enabled
OS55a F
PB
Peripheral Bus Frequency DC — 100 MHz For PBCLKx, ‘x’
4, 7
OS55b DC — 200 MHz For PBCLK4, PBCLK7
OS56 F
REF
Reference Clock Frequency — — 50 M Hz For REFCLKI1, 3, 4
and REFCLKO1, 3, 4
pins
2013-2018 Microchip Technology Inc. DS80000588K-page 21
PIC32MZ EMBEDDED CONNECTIVITY (EC)
APPENDIX A: REVISION HISTOR Y
Rev A Document (11/2013)
Initial release of this document, issued for revision A3
silicon.
This version includes the following issues: 1 (ADC),
2 (ADC), 3 (Boot Flash), 4 (Comparator Voltage
Reference), 5 (Ethernet Controller), 6 (Ethernet
Controller), 7 (Ethernet Controller), 8 (I/O Port),
9 (Oscillator), 10 (Oscillator), 11 (Secondary Oscillator),
12 (LPRC Oscillator), 13 (Power-Saving Modes),
14 (Power-Saving Modes), 15 (SPI), 16 (SQI),
17 (System Bus), 18 (USB), 19 (USB), 20 (USB),
21 (USB), 22 (Watchdog Timer), 23 (Watchdog Timer),
24 (PMP), 25 (I
2
C), 26 (Crypto Engine), and
27 (Random Number Generator).
Rev B Document (12/2013)
Updated issues 7 (Ethernet Controller) and
14 (Power-Saving Modes).
Content in issue 21, which was included in a
previous errata version, was removed and this issue
has been marked as Reserved.
Added data sheet clarification issues 1 (Power-Down
Current) and 2 (Operating Conditions), and silicon
issues 28 ( Flash) and 29 (ADC).
Rev C Document (4/2014)
Upda ted for revision A4 silicon.
Content in issues 12 and 16, which was included in
a previous errata version, was removed and these
issues have been marked as Reserved.
Added silicon issues 30 (SQI), 31 (SQI), 32 (SQI),
33 (SQI), 34 (SQI), 35 (SQI), 36 (Comparator),
37 (Comparator), 38 (I/O Pins), 39 (I
2
C), 40 (Flash
Memory), 41 (Oscillator), 42 (5V Tolerant I/O Pins),
43 (ADC), 44 (ADC), and 45 (Prefetch).
Added data sheet clarification issues 3 (Internal FRC
Accuracy), 4 (Internal LPRC Accuracy), 5 (Internal
Backup FRC (BFRC) Accuracy), 6 (ADC1 Module
Specifications and Timing Requirements), 7 (ADC
Configuration Requirements), 8 (SQI Timing
Requirements), 9 (DC Temperature and Voltage
Specifications.), 10 (Recommended Minimum
Connection), and 11 (I/O Ports).
Rev D Document (5/2014)
Updated silicon issues 43 (ADC) and 44 (ADC) and
data sheet clarifications 6 (ADC1 Module
Speci fications and Timing Requirem ents) an d 7 (ADC
Configuration Requirement s).
Rev E Document (9/2014)
Updated for revision A5 silicon.
Updated silicon issues 24 (PMP), 25 (I
2
C), and
41 (Oscillator).
Added silicon issues 46 (Oscillator), 47 (DMA),
48 (UART), 49 (Deadman Timer), 50 (Oscillator), and
51 (ADC).
Removed data sheet clarifications 1 through 6 and 8
through 11. Issue 7 was retained, which is now
issu e 1 ( ADC Configuration Re quirements).
Added data sheet clarifications 2 (I/O Ports) and
3 (Prima ry Oscillator).
Rev F Document (10/2014)
Content in issue 51, which was included in the
previous errata version, was removed and this issue
have been marked as Reserved.
Updated issue 44 (ADC).
Added data sheet clarification 4 (Internal FRC
Oscillator.).
Rev G Document (12/2014)
Updated silicon issues 25 (I
2
C), 30 (SQI), 43 (ADC),
44 (ADC), and 50 (Oscill ator ).
Update d Data Sheet Cl arification 1 ( ADC Configura tion
Requirements) and 3 (Primary Oscillator).
Added silicon issues 52 (I
2
C), 53 (System Bus),
54 (Power-Saving Modes), 55 (Oscillator), and
56 (UART).
Added Data Sheet Clarification 5 (Internal LPRC
Oscillator).
Rev H Document (7/2015)
Content in issues 36, 49, and 54, which was included
in the previous errata version, has been removed and
these issues have been marked as Reserved.
Updated silicon issue 50 (Oscillator).
Added silicon issues 57 (Timer1), 58 (PMP),
59 (PMP), 60 (Oscillator), 61 (Watchdog Timer), and
62 (Flash ).
Removed data sheet clarification 1 (ADC
Configuration Requirements), 2 (I/O Ports), 3 (Internal
FRC Oscillator), 4 (Internal LPRC Oscillator), and 5
(USB).
Updated data sheet clarification issue 2 (Primary
Oscillator), which is now issue 2.
Added data sheet clarification 1 (System Bus
Arbitration).
Rev J Document (9/20 15)
Removed silicon issue 60 (Oscillator), which is now
marked Reserved.
PIC32MZ EMBEDDED CONNECTIVITY (EC)
DS80000588K-page 22 2013-2018 Microchip Technology Inc.
Rev K Document (1/2018)
Removed data sheet clarification 1 (System Bus
Arbitration).
Added silicon issues 63 (Resets), 64 (Crypto Engine)
and 65 (Crypt o Engine)
Added data sheet clarifications 2 (Program Flash
Memory Wait States) and 3 (System Timing
Requirements).
2013-2018 Microchip Technology Inc. DS80000588K-page 23
PIC32MZ Graphics (DA) Family
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be su persed ed by updates . I t is your res ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microc hip name and logo, the Micr ochip log o, Any Rate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, K
EE
L
OQ
,
K
EE
L
OQ
logo, Kle e r, LANCheck, LI N K MD, m aX S tyl u s,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer , PIC, picoPower, PICSTART, PIC32 logo, Prochip
Design e r, QTouch , Ri gh t Touch, SA M- B A, SpyNIC , SS T, SST
Logo, SuperFlash, tinyAV R, UNI/O, and XMEGA are regist ered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other c ountries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Spe ed Control, HyperLight Load, IntelliMO S,
mTouch, Preci sion Edge, and Quiet -Wire are regis tered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor , AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthent i cation, CryptoCo mpanion,
CryptoController, ds PICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Progra mming, ICSP, Inter-Chip Conn ectivity, JitterBlocker,
KleerNe t, KleerNet logo, Mindi, MiWi, motorBench, MP A SM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRA K, NetDetac h,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon , QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Ser ial Quad I/O, SMART-I.S., SQI ,
Super Switcher, SuperSwitcher II, Total Endurance, TS HARC,
USBCheck, V ariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are tra demarks of Microchip T e chnolo gy Incorporated in the
U.S.A. and other countries.
SQTP is a servic e mark of Microchip Technology Incorporated in
the U.S.A.
Silicon S torage Technology is a r egistered trade mark of Microch ip
Technology Inc. in other countries.
GestIC i s a reg i stered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip T echnology
Inc., in other countries.
All ot her trademarks mentioned herein are property of their
respective companies.
© 2013-2018, Microchip Technology Incorporated, All Right s
Reserved.
ISBN: 978-1-5224-2592-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the c ustom er who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly e volving. We at M icrochip are c omm itted t o c ontinuously impr oving t he c ode pr otection feat ures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac ts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue f or relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldw id e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hoppin g
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949
==
DS80000588K-page 24 2013-2018 Microchip Technology Inc.
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10/25/17
