General Description
Critical loads often employ parallel-connected power
supplies with redundancy to enhance system reliability.
The MAX8555/MAX8555A are highly integrated, inex-
pensive MOSFET controllers that provide isolation and
redundant power capability in high-reliability systems.
The MAX8555/MAX8555A are used in 0.5V to 3.3V sys-
tems, and have an internal charge pump to drive the
gates of the N-channel pass elements to (VCS+ + 5V).
During startup, the MAX8555/MAX8555A monitor the
voltage drop across the external MOSFETs. Once VCS+
approaches or exceeds the bus voltage (VCS-), the
MOSFETs are turned on. The MAX8555/MAX8555A fea-
ture a dual-purpose TIMER input. A single external
resistor from TIMER to ground sets the turn-on speed of
the external MOSFETs. Optionally, the TIMER input can
be used as a logic enable input. Once the external
MOSFET is turned on, these controllers monitor the
load, protecting the bus against overvoltage, undervolt-
age, and reverse-current fault conditions. The
MAX8555 is available with a 40mV reverse-current
threshold, while the MAX8555A is available with a 20mV
reverse-current threshold.
Overvoltage and undervoltage fault thresholds are
adjustable and can be disabled. The current-limit trip
points are set by the external MOSFETs’ RDS(ON),
reducing component count. An open-drain, logic-low
fault output indicates if an overvoltage, undervoltage, or
reverse-current fault occurs. The MAX8555 and the
MAX8555A can shut down in response to a reverse-
current fault condition as quickly as 200ns.
Both devices come in space-saving 10-pin µMAX or
TDFN packages and are specified over the extended
-40°C to +85°C temperature range.
Applications
Point-of-Load Supplies
Power-Supply Modules
Servers
Telecom Power Supplies
Rectifiers
Redundant Power Supplies in High-Availability
Systems
Features
♦Simple, Integrated, and Inexpensive MOSFET
Controllers
♦ORing FET Drive for 0.5V to 3.3V
♦Eliminate ORing Diode Power Dissipation
♦Provide N+1 Redundant Supply Capability for
Highly Reliable Systems
♦Isolate Failed Short-Circuit Supply from
Output BUS
♦Respond to Reverse Short-Circuit Current
in 200ns
♦Adjustable Blank Time
♦Programmable Soft-Start
♦Logic Enable Input
♦Adjustable Overvoltage and Undervoltage
Trip Points
♦Fault-Indicator Output
♦Space-Saving Packages
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
13-3087; Rev 0; 1/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
MAX8555ETB
-40°C to 85°C
10 TDFN
3mm x 3mm*
ACC
MAX8555EUB
-40°C to 85°C
10 µMAX
8555EUB
MAX8555AETB
-40°C to 85°C
10 TDFN
3mm x 3mm*
ADD
MAX8555AEUB
-40°C to 85°C
10 µMAX
8555AEUB
1
2
3
4
5
10
9
8
7
6
CS+
CS-
OVP
VDD
VL
GND
GATE
MAX8555/
MAX8555A
µMAX
TOP VIEW
TIMERUVP
FAULT
1
2
3
4
5
10
9
8
7
6
CS+
CS-
OVP
VDD
VL
GND
GATE
MAX8555/
MAX8555A
TDFN
TIMERUVP
FAULT
Pin Configurations
*Exposed paddle
Typical Operating Circuit appears at end of data sheet.
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF,
TA = 0°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
GATE to GND .........................................................-0.3V to +12V
FAULT, VL to GND ...................................................-0.3V to +6V
OVP, UVP, TIMER, CS+, CS- to GND.......-0.3V to +(VVL + 0.3V)
VDD to GND..................................................(VVL - 0.3V) to +18V
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW
10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS
MIN
TYP
MAX
VDD SUPPLY
VL unconnected
8.00 13.25
VDD Input Voltage VTIMER = 2.5V VL = VDD 3.0 5.5 V
VL unconnected, VTIMER = 2.5V, VDD = 13.25V 2.0 3.3
VDD Supply Current VDD = VVL = 5V, VTIMER = 2.5V
0.04
0.2
VDD Shutdown Current VTIMER = 0V, VDD = 13.25V 3.0
Rising threshold
14.0 14.4
15.0
VDD Overvoltage Internal
Threshold Falling threshold
13.3 13.8
14.5 V
VL SUPPLY
VL Input Voltage VDD = VVL 3.0 5.5 V
VL Supply Current VDD = VVL = 5V, VTIMER = 2.5V 1.8 3.0
VL Current in Shutdown Mode TIMER = GND, VDD = VVL = 5V 1.6 3.0
VL Output Voltage VDD = 8V to 13.25V, IVL = 0A
3.80
4.1 4.45 V
VL = VDD, rising threshold
2.78 2.82
2.90
VL Undervoltage Lockout VL = VDD, falling threshold
2.68 2.75
2.82 V
CS INPUTS
CS+, CS- Input Current VTIMER = 2.5V, VCS = 3.0V 5.2 µA
Offset Input Current (CS+, CS-) VCS = 3.0V, Figure 4
-250 +250
nA
CS+/CS- Input Range (Note 1) 0.5
VVL - 0.5
V
VCS+ = +3V, VCS- = 0V, ICS-
-0.5
CS Isolation VCS- = +3V, VCS+ = 0V, ICS+
-0.5
µA
CHARGE-PUMP VOLTAGE
VDD = 8V to 13.25V
GATE Voltage, VGATE
Measured from GATE to CS+
VDD = VVL = 5V 5.0
5.25
5.5 V
RTIMER = 20kΩ
187
RTIMER = 125kΩ
450
RTIMER = open
500
Charge-Pump Switching
Frequency
VTIMER = 1.5V
550
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF,
TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
TIMER
TIMER Voltage
1.22 1.25
1.28 V
TIMER Maximum Source Current
VTIMER = 1.0V 85
100
115 µA
TIMER High Input Current VTIMER = 1.5V 10 15 µA
TIMER Maximum Frequency
Select Voltage Input Range (Note 1) 1.5 VVL V
TIMER Logic High, VIH Charge pump enabled 1.0 V
TIMER Logic Low, VIL Charge pump disabled 0.5 V
FAULT
Fault Output Low Voltage IFAULT = 10mA 0.2 V
Fault Sink Current V FAULT = 0.4V 15
mA
Fault Leakage Current V FAULT = 5.5V, TA = +25°C 1 µA
GATE
MAX8555 80
100
120
Gate-On Threshold Measured from CS- to CS+ MAX8555A 35 50 65
mV
RTIMER = open 17 25 33
VGATE = VCS+ = 2.5V RTIMER = 25kΩ81216
RTIMER = open 15
VGATE = VCS+ = 2.5V,
VDD = VVL = 3V RTIMER = 25kΩ7.5
RTIMER = open 30
Gate-Drive Current
VGATE = VCS+ = 2.5V,
VDD = VVL = 5V RTIMER = 25kΩ15
µA
VTIMER falling
100
200
Gate Shutdown Delay (Note 2) IREV fault 60 150 ns
Gate Discharge Current VGATE = VCS+= +5V
1000
mA
GATE Fall Time Gate voltage fall from FAULT to VGATE = VCS+,
R1 = 2Ω, Figure 3 or Figure 4 0.2 µs
CURRENT SENSE
MAX8555 34 40 46
Reverse-Current Threshold Measured from CS- to CS+ MAX8555A 16 20 24
mV
Startup IREV Blank Time TIMER = unconnected 4.1 ms
Forward-Current Threshold Measured from CS+ to CS- 6 10 14
mV
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF,
TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
OVERVOLTAGE PROTECTION
OVP rising
0.49 0.5
0.51
OVP Fault Threshold, VOVP OVP falling 0.4 V
TA = +25°C 0.1
OVP Bias Current TA = +85°C
0.021
µA
UNDERVOLTAGE PROTECTION
UVP rising
0.488 0.5 0.512
UVP Fault Threshold, VUVP UVP falling 0.4 V
TA = +25°C 0.1
UVP Bias Current TA = +85°C
0.003
µA
ELECTRICAL CHARACTERISTICS
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF,
TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
VDD SUPPLY
VL unconnected
8.00 13.25
VDD Input Voltage VTIMER = 2.5V VL = VDD 3.0 5.5 V
VL unconnected, VTIMER = 2.5V, VDD = 13.25V 3.3
VDD Supply Current VDD = VVL = 5V, VTIMER = 2.5V 0.2
mA
VDD Shutdown Current VTIMER = 0V, VDD = 13.25V 3.0
mA
Rising threshold
14.0
15.0
VDD Overvoltage Internal
Threshold Falling threshold
13.3
14.5 V
VL SUPPLY
VL Input Voltage VDD = VVL 3.0 5.5 V
VL Supply Current VDD = VVL = 5V, VTIMER = 2.5V 3.0
mA
VL Current in Shutdown Mode TIMER = GND, VDD = VVL= 5V 3.0
mA
VL Output Voltage VDD = 8V to 13.25V, IVL = 0A
3.80
4.45 V
VL = VDD, rising threshold
2.78
2.90
VL Undervoltage Lockout VL = VDD, falling threshold
2.68
2.82 V
CS INPUTS
Offset Input Current (CS+, CS-) VCS = 3.0V, Figure 4
-250
+250 nA
CS+/CS- Input Range (Note 1) 0.5
VVL - 0.5
V
CHARGE-PUMP VOLTAGE
VDD = 8V to 13.25V
GATE Voltage, VGATE
Measured from GATE to CS+
VDD = VVL = 5V 5.0 5.5 V
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
_______________________________________________________________________________________ 5
Note 1: Guaranteed by design. Not production tested.
Note 2: Gate shutdown delay is measured from reverse-current fault to the start of gate-voltage falling or from TIMER to the start of
gate-voltage falling.
Note 3: Specifications to -40°C are guaranteed by design and not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF,
TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
TIMER
TIMER Voltage
1.22
1.28 V
TIMER Maximum Source Current
VTIMER = 1.0V 85 115 µA
TIMER High Input Current VTIMER = 1.5V 15 µA
TIMER Maximum Frequency
Select Voltage Input Range (Note 1) 1.5 VVL V
TIMER Logic High, VIH Charge pump enabled 1.1 V
TIMER Logic Low, VIL Charge pump disabled 0.5 V
FAULT
Fault Output Low Voltage IFAULT = 10mA 0.2 V
Fault Sink Current V FAULT = 0.4V 15
mA
GATE
MAX8555 80 120
Gate-On Threshold Measured from CS- to CS+ MAX8555A 35 65
mV
RTIMER = open 17 33
Gate-Drive Current VGATE = VCS+ = 2.5V RTIMER = 25kΩ816
µA
VTIMER falling 200
Gate Shutdown Delay IREV fault 150 ns
CURRENT SENSE
MAX8555 34 46
Reverse-Current Threshold Measured from CS- to CS+ MAX8555A 16 24
mV
Forward-Current Threshold Measured from CS+ to CS- 6 14
mV
OVERVOLTAGE PROTECTION
OVP Fault Threshold, VOVP OVP rising
0.49
0.51 V
UNDERVOLTAGE PROTECTION
UVP Fault Threshold, VUVP UVP rising
0.488 0.512
V
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
6_______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 12V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.4V, RFAULT = 50kΩto output bus, CVDD = CGATE = CVL = 0.01µF, TA =
+25°C, R1 = 2Ωin Figure 3, MAX8555A, unless otherwise noted.)
GATE-CHARGE CURRENT
vs. TIMER RESISTOR (VDD = 12V)
MAX8555/55A toc01
TIMER RESISTOR (kΩ)
GATE CURRENT (µA)
100
0
5
10
15
20
25
-5
10 1000
TA = +85°C
TA = +25°C
TA = -40°C
GATE-CHARGE CURRENT vs.
TIMER RESISTOR (VDD = VVL = 3V)
MAX8555/55A toc02
TIMER RESISTOR (kΩ)
GATE-CHARGE CURRENT (µA)
100
0
2
4
6
8
10
12
14
16
18
-2
10 1000
TA = +85°C
TA = +25°CTA = -40°C
VDD CURRENT vs. TEMPERATURE
MAX8555/55A toc03
TEMPERATURE (°C)
VDD CURRENT (mA)
6040200-20
0.5
1.0
1.5
2.0
2.5
3.0
0
-40 80
TIMER = OPEN
TIMER = GND
VDD = 13.25V
REVERSE-CURRENT THRESHOLD vs.
TEMPERATURE
MAX8555/55A toc04
TEMPERATURE (°C)
REVERSE-CURRENT THRESHOLD (mV)
6040200-20
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
10.0
-40 80
OVP AND UVP LEAKAGE CURRENT vs.
TEMPERATURE
MAX8555/55A toc05
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
6040200-20
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0
-40 80
OVP
UVP
POWER-UP WAVEFORMS BUS
VOLTAGE HIGH IMPEDANCE
MAX8555/55A toc06
1ms/div
VCS+
VGATE
VCS-
IMOSFET
1V/div
5V/div
1V/div
1A/div
POWER-UP WAVEFORMS
BUS VOLTAGE IS LIVE
MAX8555/55A toc07
2ms/div
VCS+
VGATE
VCS-
IMOSFET
1V/div
5V/div
1V/div
500mA/div
POWER-UP AND DOWN WAVEFORMS
USING TIMER
MAX8555/55A toc08
5ms/div
VGATE
VTIMER
IMOSFET 1A/div
2V/div
5V/div
REVERSE-CURRENT
SHUTDOWN WAVEFORMS
MAX8555/55A toc09
200ns/div
VGATE
VCS-
VFAULT
IMOSFET 0A
-2A
5V/div
1V/div
100mV/div
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
_______________________________________________________________________________________ 7
UVP SHUTDOWN WAVEFORMS
MAX8555/55A toc10
200ns/div
VGATE
VUVP
VCS-
AC-COUPLED
VFAULT
2V/div
2V/div
5V/div
100mV/div
OVP SHUTDOWN WAVEFORMS
MAX8555/55A toc11
200ns/div
VGATE
VOVP
VCS-
AC-COUPLED
VFAULT 1V/div
2V/div
5V/div
100mV/div
POWER-SUPPLY OUTPUT
SHORT-CIRCUIT SHUTDOWN WAVEFORMS
MAX8555/55A toc12
200ns/div
VGATE1
IMOSFET2
VCS+
VCS-
AC-COUPLED
1V/div
5V/div
200mA/div
100mV/div
VDD FAULT SHUTDOWN WAVEFORMS
MAX8555/55A toc13
1µs/div
VGATE
VFAULT
VDD
VCS- 1V/div
5V/div
1V/div
10V/div
Typical Operating Characteristics (continued)
(VDD = 12V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.4V, RFAULT = 50kΩto output bus, CVDD = CGATE = CVL = 0.01µF, TA =
+25°C, R1 = 2Ωin Figure 3, MAX8555A, unless otherwise noted.)
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
8_______________________________________________________________________________________
PIN
NAME
FUNCTION
1
GATE
Gate-Drive Output. Nominal GATE load is a 0.01µF capacitor to ground. Gate is discharged to GND in
shutdown.
2GND Ground
3VL
Low-Voltage Optional Input Power. Leave disconnected when VDD = 8V to 13.25V, or connect VDD to VL
when VDD = 3V to 5.5V. Bypass VL to GND with a 0.01µF capacitor.
4V
DD Power-Supply Input. Connect to an 8V to 13.25V supply or connect to VL when using a 3V to 5.5V supply.
Bypass VDD with a 0.01µF capacitor to ground.
5UVP Undervoltage-Protection Input. Connect UVP to the center of a resistor-divider from CS+ to GND. Connect
UVP to VL to disable the undervoltage protection.
6
TIMER
Timer Input. Connect a resistor from TIMER to GND to select the charge-pump operating frequency. Drive
TIMER low (< 0.5V) to disable the gate drive. Drive TIMER high (above 1.5V) for charge-pump operation
at 550kHz.
7
FAULT
Open-Drain Fault Output. FAULT is high impedance during normal operation and is pulled to GND when a
fault condition occurs. Connect a pullup resistor of 10kΩ or higher value (50kΩ typ) to a voltage rail of 5.5V
or lower.
8OVP Overvoltage-Protection Input. Connect OVP to the center of a resistor-divider from the output bus to GND.
Connect OVP to GND to disable the overvoltage protection.
9CS- Current-Sensing Input. Connect CS- to the positive side of the system bus. Bypass with a 1000pF capacitor
to GND.
10 CS+ Current-Sensing Input. Connect CS+ to the positive side of the input power. Bypass with a 1000pF capacitor
to GND.
Pin Description
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
_______________________________________________________________________________________ 9
MAX8555/
(MAX8555A)
CS+
CLK
CHARGE
PUMP
CONTROL
LOGIC
SHUTDOWN
GATE CS-
VL
REVERSE CURRENT
FORWARD CURRENT
100mV
(50mV) 10mV
VL
OVP
UVP
OVERVOLTAGE EXTERNAL
UNDERVOLTAGE
TIMER
IOSC
0.5V
0.4V
1.25V REF
ENABLE
14.5V
OVERVOLTAGE INTERNAL
40mV
(20mV)
VOLTAGE SHARE
VDD
VL
REGULATOR
VLGND
VL
FAULT
Figure 1. MAX8555/MAX8555A Functional Diagram
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
10 ______________________________________________________________________________________
STANDBY:
CPMP: OFF
GATE: LOW
WAIT
FOR
VSHARE
CS- - CS+ < 0.1V
CS- - CS+ > 0.1V
ON: SET
VSHARE LATCH,
CHARGE PUMP ON
UVP = OK
OVP OK AND
IREVERSE DURING
FIRST 4.1ms
FAULT
SHUTDOWN GATE:
FAULT LATCHED
UVP FAULT
SHUTDOWN GATE
FAULT NOT LATCHED
UVP FAULT
UVP-OK
CS-
CS+
CS- - 100mV/50mV
CS- + 10mV
VSHARE LATCH SET
IFORWARD
FAULT
SHUTDOWN GATE
FAULT LATCHED
IREVERSE CONDITION DETECTED AFTER
4.1ms BLANK TIME
CS- - 40mV/20mV
IREVERSE
IFORWARD
and OVP Fault
TIMER > 1V
ALL TRANSITIONS ARE ASYNCHRONOUS
VSHARE = ((CS-) - CS+) < 0.1V/0.05V
IFORWARD = ((CS+) - CS-) > 0.01V
IREVERSE = ((CS-) -CS+ ) > 40mV/20mV
VDD OR
TIMER
CYCLED
VCC OR
TIMER
CYCLED
4.1ms
VCC > VCCOK
State Diagram
General Description
Critical loads often employ parallel-connected power
supplies with redundancy to enhance system reliability.
The MAX8555/MAX8555A are highly integrated, inex-
pensive MOSFET controllers that provide isolation and
redundant power capability in high-reliability systems.
The MAX8555/MAX8555A are used in 0.5V to 3.3V sys-
tems, and have an internal charge pump to drive the
gates of the N-channel pass elements to VCS+ + 5V.
During startup, the MAX8555/MAX8555A monitor the
voltage drop across the external MOSFETs. Once VCS+
approaches or exceeds the bus voltage (VCS-), the
MOSFETs are turned on. The MAX8555/MAX8555A fea-
ture a dual-purpose TIMER input. A single external
resistor from TIMER to ground sets the turn-on speed of
the external MOSFETs. Optionally, the TIMER input can
be used as a logic enable input. Once the external
MOSFET is turned on, these controllers monitor the
load, protecting the bus against overvoltage, undervolt-
age, and reverse-current fault conditions. The
MAX8555 is available with a 40mV reverse-current
threshold, while the MAX8555A is available with a
20mV reverse-current threshold.
Overvoltage and undervoltage fault thresholds are
adjustable and can be disabled. The current-limit trip
points are set by the external MOSFETs’ RDS(ON),
reducing component count. An open-drain, logic-low
fault output indicates if an overvoltage, undervoltage, or
reverse-current fault occurs. The MAX8555 and the
MAX8555A can shut down in response to a reverse-
current fault condition as quickly as 200ns.
VDD
VDD is the power-supply input for the MAX8555/
MAX8555A and the input to the internal preregulator.
Bypass VDD to GND with a 0.01µF capacitor. The input
supply range for VDD is 8V to 13.25V. The internal
charge pump is disabled for input voltages above
14.4V (typ). For 3V to 5.5V input voltages, connect VDD
to VL.
VL
VL is the regulated power supply for the
MAX8555/MAX8555A. The MAX8555/MAX8555A moni-
tor VL at all times. During startup the device turns on
when VL rises above VLOK (2.82V typ). After VVL
exceeds VLOK and VCS+ is typically greater than
(VCS- - 100mV), the charge pump turns on and drives
GATE high, turning on the external MOSFETs. For oper-
ation from 3V to 5.5V input supplies, connect VL
to VDD.
TIMER
GATE is the output of the internal charge pump that
drives the external MOSFETS. During startup, the volt-
age at GATE ramps up according to the charge-pump
frequency. At 250kHz, the GATE drive current for the
MAX8555/MAX8555A is 12µA. Increasing the charge-
pump frequency increases the GATE drive current. To
change charge-pump frequency, change the value of
RTIMER. See the Selecting the TIMER Resistor section.
CS+, CS-
The voltage drop across the external MOSFETs is mea-
sured between the CS+ and CS- inputs. CS+ connects
to the positive side of the input voltage. CS- connects to
the positive side of the system bus. The MAX8555/
MAX8555A use the voltage drop across CS+ and CS- to
determine operating mode. IFORWARD is defined as
VCS+ - VCS- and must be greater than 0.01V (typ) to
properly detect an overvoltage fault condition. IREVERSE
is defined as VCS- - VCS+ and must be greater than
0.02V (MAX8555A) or 0.04V (MAX8555) (typ) for a
reverse-current fault. The IFORWARD and IREVERSE
thresholds can be effectively increased by placing an
external divider such as R8 and R9 as shown in Figure 4.
The values shown increase the thresholds by 50%. When
R8 and R9 are used, also add R10 (a parallel combina-
tion of R8 and R9) to eliminate any input offset errors
caused by impedance differences and input-bias-cur-
rent differences.
Fault Conditions
The MAX8555/MAX8555A have an open-drain FAULT
output that signals overvoltage, undervoltage, or
reverse-current fault conditions. During a fault condi-
tion, FAULT is pulled to GND, the charge pump shuts
down, and GATE discharges to CS- in 200ns (typ). See
Table 1 for fault modes.
Undervoltage Fault
The MAX8555/MAX8555A turn off the external
MOSFETs if VUVP falls below the UVP threshold (0.4V).
Connect UVP to the center of a resistor-divider from the
input supply to GND. Once VUVP rises above the UVP
rising threshold (0.5V), FAULT clears and GATE is dri-
ven high. FAULT is not latched. Connect UVP to VL to
disable the undervoltage-protection feature.
Overvoltage Fault
The MAX8555/MAX8555A are protected from overvolt-
age conditions using an adjustable overvoltage-protec-
tion input. A resistor-divider from the output bus to GND
with OVP connected to the center tap sets the overvolt-
age threshold. When VOVP exceeds the OVP threshold
(0.5V) and the device is in the IFORWARD condition
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
______________________________________________________________________________________ 11
MAX8555/MAX8555A
(defined as VCS+ > VCS- + 0.01V), the MAX8555/
MAX8555A discharge GATE to GND and FAULT is
latched low. If the IFORWARD condition is not detected,
OVP is disabled. In redundant systems, when one input
supply approaches its OVP threshold, some of the
other input supplies may be pulled up with it, thereby
tripping those OVP comparators with a slightly lower
set point. The IFORWARD condition for the pulled-up
supplies may not be detected until the first supply is
shut down. An alternate application schematic for
FAULT and OVP is shown in Figure 2. The FAULT
output of the first channel, which has both OVP and
IFORWARD conditions, temporarily reduces the common
OVP signal by 125mV. This ensures that only the input
supply, which is causing the overvoltage condition, is
turned off in a redundant power-system application.
Exceeding the OVP threshold causes the MAX8555/
MAX8555A to be latched off. Toggle VDD or TIMER to
reset the IC. Connect OVP to GND to disable the over-
voltage-protection feature.
Reverse-Current Fault
The MAX8555/MAX8555A provide a reverse-current
fault-protection feature that turns off the oring MOSFET
when a reverse-current fault condition is detected.
Once a reverse-current fault condition is detected, the
MAX8555/MAX8555A discharge GATE to GND and
latch FAULT low. Toggle VDD, VL, or TIMER to reset the
IC. The reverse-current-protection feature is blanked for
2048 charge-pump cycles at startup.
Selecting the TIMER Resistor
Connect a resistor from TIMER to GND to set the inter-
nal charge pump’s frequency of operation. Determine
the TIMER resistor with the following equation:
Drive TIMER above 1.5V for the maximum charge-
pump frequency (550kHz). Drive TIMER below 0.5V to
disable the charge pump and shut down the MAX8555/
MAX8555A.
Selecting the GATE Capacitor and
GATE Resistor
The charge pump uses an internal monolithic transfer
capacitor to charge the external MOSFET gates.
Normally, the external MOSFET’s gate capacitance is
sufficient to serve as a reservoir capacitor. To slow down
turn-on times further, add a small capacitor between
GATE and GND. Adding a small resistor between GATE
and the gate of the Oring MOSFET reduces the high-fre-
quency ringing due to gate trace inductance. However,
the resistor increases the turn-off time.
RV
Af
kHz A
TIMER =
µ−µ
125
100 5
.
/
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
12 ______________________________________________________________________________________
150pF
150pF R2B
6.04kΩ
R5
2.87kΩ
R6
1kΩ
OVP
R2A
47kΩ
R2A
47kΩ
R2B
6.04kΩ
SYSTEM BUS
FAULT
OVP
FAULT
Figure 2. OVP Connection when Multiple MAX8555s Are Used
FAULT MODE CONDITIONS
GATE
FAULT
LATCHING
VL UVLO VL < VLOK
LOW High Impedance
NO
UVP
Undervoltage Protection VUVP < 0.4V
LOW
LOW NO
OVP
Overvoltage Protection
VOVP > 0.5V
VCS+ > VCS- + 0.01V
LOW
LOW YES
Reverse-Current Protection VCS+ < VCS- - 0.04V (0.02V for MAX8555A) and
GATE is on for > 2048 charge-pump cycles
LOW
LOW YES
VDD Internal Overvoltage Protection
VDD > 14.5V
LOW
LOW NO
Table 1. Fault Modes
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
______________________________________________________________________________________ 13
MAX8555/
MAX8555A
R1
2Ω
INPUT
SUPPLY
OUT-
OUT+
C2
0.01µF
R2
51kΩ
TIMER
GATE
VDD
CS-
GND
C1
1000pF
R7
24.9kΩ
OUTPUT:
1.5V/20A
OVP
R3
5kΩ
R4
10kΩ
R5
15kΩ
R6
10kΩ
UVP
12V
CS+
VL
Q1 Q2
C4
0.01µF
FAULT
OUTPUT
BUS
+VO
-VO
C3
1000pF
Figure 3. Application Circuit for 12V IC Supply Voltage
MAX8555/
MAX8555A
R1
2Ω
R10
665Ω
INPUT
SUPPLY
OUT-
OUT+
C2
0.01µF
R2
51kΩ
TIMER
GATE
VDD
CS-
GND
C4
1000pF
R7
24.9kΩ
OUTPUT:
1.5V/20A
OVP
R3
5kΩ
R4
10kΩ
R5
15kΩ
R6
10kΩ
UVP
5V CS+
VL
Q1 Q2
C1
0.01µF
C3
1000pF
FAULT
OUTPUT
BUS
+VO
-VO
R8
1kΩ
R9
2kΩ
Figure 4. Application Circuit for 5V IC Supply Voltage
Applications Information
MAX8555/MAX8555A
Set the UVP Fault Threshold
Use a resistor-divider from the input supply to GND with
the center tap connected to UVP to set the undervoltage
threshold. Use a 10kΩresistor from UVP to GND (R4 in
Figure 4) and calculate R3 as follows:
where VUV is the desired undervoltage trip point and
VUVP is the UVP reference threshold (0.4V typ). Connect
UVP to VL to disable the undervoltage-protection feature.
Set the OVP Fault Threshold
For a single-supply application, use a resistor-divider
from the output bus to GND with the center tap con-
nected to OVP to set the overvoltage threshold. Use a
10kΩresistor from OVP to GND (R6 in Figure 4) and
calculate R5 as follows:
where VOV is the desired overvoltage threshold and VOVP
is the OVP reference threshold (0.5V typ). Connect OVP
to GND to disable the overvoltage-protection feature.
For (n + 1) applications, the required circuit values are:
where the resistors are as shown in Figure 2.
MOSFET Selection
The MAX8555/MAX8555A drive N-channel MOSFETs.
The most important specification of the MOSFETs is
RDS(ON). As load current flows through the external
MOSFET, VDS is generated from source to drain due to
the MOSFET’s on-resistance, RDS(ON). The MAX8555/
MAX8555A monitor VDS of the MOSFETs at all times to
determine the state of the monitored power supply.
Selecting a MOSFET with a low RDS(ON) allows more
current to flow through the MOSFETs before the
MAX8555/MAX8555A detect reverse-current (IREVERSE)
and forward-current (IFORWARD) conditions.
Using Two MOSFETs
Two MOSFETs must be used for overvoltage protec-
tion. When using two external MOSFETs, the monitored
voltage equation becomes:
VDSTOTAL = RDS(ON)1 x ILOAD + RDS(ON)2 x ILOAD
Using One MOSFET
A single MOSFET can be used if the overvoltage-protec-
tion function is not needed. Connect CS+ to the source of
the MOSFET and CS- to the drain of the MOSFET.
Calculating GATE Current
The charge-pump output current is proportional to both
oscillator frequency and VVL. There is also a small inter-
nal load of approximately 6MΩ. The GATE current for a
given VVL and RTIMER is calculated as:
Layout Guidelines
It is important to keep all traces as short as possible
and to maximize the high-current trace dimensions to
reduce the effect of undesirable parasitic inductance.
The MOSFET dissipates a fair amount of heat due to
the high currents involved, especially during an over-
current condition. To dissipate the heat generated by
the MOSFET, make the power traces very wide with a
large amount of copper area and place the MAX8555
as close as possible to the drain of the external MOS-
FET. A more efficient way to achieve good power dissi-
pation on a surface-mount package is to lay out two
copper pads directly under the MOSFET package on
both sides of the board. Use enlarged copper mount-
ing pads on the top side of the board. Use a ground
plane to minimize impedance and inductance. In addi-
tion to the usual high-power considerations, here are
three tips to prevent false faults:
1) Kelvin connect CS+ and CS- to the external
MOSFET and route the two traces in parallel, as
close as possible, back to the IC.
2) Bypass VDD with a 0.01µF capacitor to ground and
bypass CS+ and CS- with a 1000pF capacitor to
ground.
3) Make the traces connected to UVP and OVP as
short as possible.
Refer to the MAX8555/MAX8555A evaluation kit for an
example of good PC board layout.
IV
RA
GATE L
TIMER
≈×−
×−
−
µ24 12 08
34 112 500 04.(.)
.
,.
Rk
RR V
V
RA k
RB R
OV
OVP
61
56 1
247
225
=Ω
=× −
=Ω
=×
RRV
V
OV
OVP
56 1=−
RRV
V
UV
UVP
34 1=−
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
14 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 2309
PROCESS: BiCMOS
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
______________________________________________________________________________________ 15
MAX8555/
MAX8555A
INPUT
SUPPLY
OUT-
OUT+
TIMER
GATE
VDD
CS-
GND
OUTPUT:
1.5V AT 20A
OVP
UVP
8V TO 13.25V CS+
VL
FAULT
OUTPUT
BUS
+VO
-VO
Typical Operating Circuit
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
16 ______________________________________________________________________________________
6, 8, &10L, DFN THIN.EPS
PROPRIETARY INFORMATION
TITLE:
APPROVAL DOCUMENT CONTROL NO. REV.
2
1
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137 D
L
CL
C
SEMICONDUCTOR
DALLAS
A2
A
PIN 1
INDEX
AREA
D
E
A1
D2
b
E2 [(N/2)-1] x e
REF.
e
k
1N1
L
e
L
A
L
PIN 1 ID
C0.35
DETAIL A
e
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
DOCUMENT CONTROL NO.APPROVAL
TITLE:
PROPRIETARY INFORMATION
REV.
2
2
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A0.70 0.80
D2.90 3.10
E2.90 3.10
A1 0.00 0.05
L0.20 0.40
PKG. CODE
6
N
T633-1 1.50±0.10
D2
2.30±0.10
E2
0.95 BSC
e
MO229 / WEEA
JEDEC SPEC
0.40±0.05
b
1.90 REF
[(N/2)-1] x e
1.50±0.10 MO229 / WEEC 1.95 REF0.30±0.05
0.65 BSC
2.30±0.10T833-1 8
PACKAGE VARIATIONS
21-0137
0.25±0.05 2.00 REFMO229 / WEED-30.50 BSC1.50±0.10 2.30±0.1010T1033-1
0.25 MIN.
k
A2 0.20 REF.
D
SEMICONDUCTOR
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
MAX8555/MAX8555A
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
10LUMAX.EPS
PACKAGE OUTLINE, 10L uMAX/uSOP
1
1
21-0061 I
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
1
0.498 REF
0.0196 REF
S
6∞
SIDE VIEW
α
BOTTOM VIEW
0∞0∞6∞
0.037 REF
0.0078
MAX
0.006
0.043
0.118
0.120
0.199
0.0275
0.118
0.0106
0.120
0.0197 BSC
INCHES
1
10
L1
0.0035
0.007
e
c
b
0.187
0.0157
0.114
H
L
E2
DIM
0.116
0.114
0.116
0.002
D2
E1
A1
D1
MIN
-A
0.940 REF
0.500 BSC
0.090
0.177
4.75
2.89
0.40
0.200
0.270
5.05
0.70
3.00
MILLIMETERS
0.05
2.89
2.95
2.95
-
MIN
3.00
3.05
0.15
3.05
MAX
1.10
10
0.6±0.1
0.6±0.1
ÿ0.50±0.1
H
4X S
e
D2
D1
b
A2 A
E2
E1 L
L1
c
α
GAGE PLANE
A2 0.030 0.037 0.75 0.95
A1