1
®
FN8106.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C512, X28C513
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology . Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 suppo rt a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DA TA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C51 3 support the software data
protection option.
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or VPP control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
- Endurance: 100 ,000 write cycles
- Data retention: 100 years
- Early end of write detection
-DATA
polling
- Toggle bit polling
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
Data Sheet June 7, 2006
2FN8106.2
June 7, 2006
Block Diagram
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Latches and
Decoder
Control
Logic and
Timing
512Kbit
EEPROM
Array
I/O0-I/O7
Data Inputs/Outputs
CE
OE
VCC
VSS
A7-A15
WE
A0-A6
Ordering Information
PART NUMBER PART MARKING ACCESS TIME
(ns) TEMP RANGE (°C) PACKAGE
X28C512D X28C512D - 0 to +70 32 Ld CERDIP
X28C512DM X28C512DM -55 to +125 32 Ld CERDIP
X28C512J X28C512J 0 to +70 32 Ld PLCC
X28C513EM X28C513EM -55 to +125 32 Ld LCC
X28C512D-12 X28C512D-12 120 0 to +70 32 Ld CERDIP
X28C512DI-12 X28C512DI-12 -40 to +85 32 Ld CERDIP
X28C512DMB-12 X28C512DMB-12 Mil-STD-883 32 Ld CERDIP
X28C512FMB-12 X28C512FMB-12 Mil-STD-883 32 Ld Flat Pack
X28C512J-12* X28C512J-12 0 to +70 32 Ld PLCC
X28C512JZ-12* (See Note) X28C512J-12 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C512JI-12 X28C512JI-12 -40 to +85 32 Ld PLCC
X28C512JIZ-12* (See Note) X28C512JI-12 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C512JM-12 X28C512JM-12 -55 to +125 32 Ld PLCC
X28C512KM-12 X28C512KM-12 -55 to +125 36 Ld CPGA
X28C512PI-12 X28C512PI-12 -40 to +85 32 Ld PDIP
X28C512RMB-12 X28C512RMB-12 Mil-STD-883 32 Ld Flat Pack
X28C513EM-12 X28C513EM-12 -55 to +125 32 Ld LCC
X28C513EMB-12 X28C513EMB-12 Mil-STD-883 32 Ld LCC
X28C513J-12* X28C513J-12 0 to +70 32 Ld PLCC
X28C513JZ-12* (Note) X28C513J-12 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C513JI-12* X28C513JI-12 -40 to +85 32 Ld PLCC
X28C513JIZ-12* (Note) X28C513JI-12 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C513JM-12 X28C513JM-12 -55 to +125 32 Ld PLCC
X28C512, X28C513
3FN8106.2
June 7, 2006
X28C512D-15 X28C512D-15 150 0 to +70 32 Ld CERDIP
X28C512DI-15 X28C512DI-15 -40 to +85 32 Ld CERDIP
X28C512DMB-15 X28C512DMB-15 Mil-STD-883 32 Ld CERDIP
X28C512J-15* X28C512J-15 0 to +70 32 Ld PLCC
X28C512JZ-15* (See Note) X28C512J-15 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C512JI-15* X28C512JI-15 -40 to +85 32 Ld PLCC
X28C512JIZ-15* (See Note) X28C512JI-15 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C512JM-15 X28C512JM-15 -55 to +125 32 Ld PLCC
X28C513EM-15 X28C513EM-15 -55 to +125 32 Ld LCC
X28C513EMB-15 X28C513EMB-15 Mil-STD-883 32 Ld LCC
X28C513J-15* X28C513J-15 0 to +70 32 Ld PLCC
X28C513JZ-15* (Note) X28C513J-15 Z 0 to +70 32 Ld PLCC (Pb-free)
X28C513JI-15 X28C513JI-15 -40 to +85 32 Ld PLCC
X28C513JIZ-15* (Note) X28C513JI-15 Z -40 to +85 32 Ld PLCC (Pb-free)
X28C513JM-15 X28C513JM-15 -55 to +125 32 Ld PLCC
X28C512DMB-20 X28C512DMB-20 200 Mil-STD-883 32 Ld CERDIP
X28C512JM-20 X28C512JM-20 -55 to +125 32 Ld PLCC
X28C512KI-20 X28C512KI-20 -40 to +85 36 Ld CPGA
X28C512KM-20 X28C512KM-20 -55 to +125 36 Ld CPGA
X28C513EI-20 X28C513EI-20 -40 to +85 32 Ld LCC
X28C513EM-20 X28C513EM-20 -55 to +125 32 Ld LCC
X28C513EMB-20 X28C513EMB-20 Mil-STD-883 32 Ld LCC
X28C513J-20T1 X28C513J-20 0 to +70 32 Ld PLCC Tape and Reel
X28C512EM-25 X28C512EM-25 250 -55 to +125 32 Ld LCC
X28C512JM-25 X28C512JM-25 -55 to +125 32 Ld PLCC
X28C512KM-25 X28C512KM-25 -55 to +125 36 Ld CPGA
X28C512KMB-25 X28C512KMB-25 Mil-STD-883 36 Ld CPGA
X28C513EM-25 X28C513EM-25 -55 to +125 32 Ld LCC
X28C513EMB-25 X28C513EMB-25 Mil-STD-883 32 Ld LCC
*Add "T1" suffix for tape and reel.
NOTE: Inter sil Pb-free plus an neal product s employ special Pb-f ree material set s; molding compounds/die att ach materials a nd 100% matte t in plate terminat ion finish,
which are RoHS compliant and compatible with both SnPb and Pb-f ree soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER PART MARKING ACCESS TIME
(ns) TEMP RANGE (°C) PACKAGE
X28C512, X28C513
4FN8106.2
June 7, 2006
Pinouts
Pin Descriptions
Addresses (A0-A15)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enab le (WE)
The Write Enable input controls the writing of data to the
X28C512, X28C513.
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O5
I/O4
I/O3
I/O2
I/O1
X28C512
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
Bottom
14
A0
16
I/O1
18
VSS
11
A3
9
A5
7
A7
15
I/O0
17
I/O2
19
I/O3
5
A15
2
NC
36
VCC
20
I/O 4
21
I/O 5
34
NC
23
I/O 7
25
A10
27
A11
29
A8
22
I/O 6
32
NC
24
CE
26
OE
28
A9
30
A13
13
A1
12
A2
10
A4
8
A6
4
NC
3
NC
1
NC
35
WE
33
NC
31
A14
6
A12
PGA
X28C512
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
OE
A10
CE
I/O7
A14
I/O1
A12
A15
NC
NC
VCC
WE
NC
2 32
6 1
5 4 3
8
7
9
10
11
12
13 15 17 16 18 19 20
22
23
24
25
26
27
28
29
31
14 21
30
PLCC/LCC
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
X28C513
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A9
A11
NC
OE
A10
CE
I/O6
A8
I/O1
A7
A12
VCC
WE
2 32
6 1
5 4 3
8
7
9
10
11
12
13 15 17 16 18 19 20
22
23
24
25
26
27
28
29
31
14 21
30
I/O2
VSS
NC
I/O3
I/O4
I/O5
A14
A15
A13
I/O7
View
(Top View)
(Top View)
Pin Names
SYMBOL DESCRIPTION
A0-A15 Address Inputs
I/O0-I/O7Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
VCC +5V
VSS Ground
NC No Connect
X28C512, X28C513
5FN8106.2
June 7, 2006
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C512, X28C513 support
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automati cally
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C512, X28C513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to be
consecutively written to the X28C512, X28C513, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page ad d ress (A7 through A15) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin withi n 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
programming cycle will commence. Th ere is no page write
window limitation. Effectively, the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28C512, X28C513 provide the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling (I/O7)
The X28C512, X28C513 feature DATA polling as a method
to indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple bit
test operation to determine the status of the X28C512,
X28C513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write dat a = 0xxx xxxx,
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28C512, X28C513 also provide another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete, the toggling will
cease, and the device will be accessible for additional read
or write operations.
5TBDP 43210I/O
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
X28C512, X28C513
6FN8106.2
June 7, 2006
DATA Polling I/O7
DATA Polling can effectively halve the time for writing to the
X28C512, X28C513. The timing diagram in Figure 2A
illustrates the sequence of events on the bus. The software
flow diagram in Figure 2B illustrates one method of
implementing the routine.
CE
OE
WE
I/O7
X28C512, X28C513
Ready
Last
Write
HIGH Z
VOL
VIH
A0-A15 AnAnAnAnAnAn
VOH
An
FIGURE 2A. DATA POLLING BUS SEQUENCE
Write Data
Save Last Data
and Address
Read Last
Address
IO7
Compare?
Ready
No
Yes
Writes
Complete?
No
Yes
FIGURE 2B. DATA POLLING SOFTWARE FLOW
X28C512, X28C513
7FN8106.2
June 7, 2006
The Toggle Bit I/O6
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to impleme nt
DATA Polling. This can be especially hel pful in an array
comprised of multiple X28C512, X28C513 memories that
are frequently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applications.
The timing diagram in Figure 3A illustrates the sequence of
events on the bus. The software flow diagram in Figure 3B
illustrates a method for polling the Toggle Bit.
Hardware Data Protection
The X28C512, X28C513 provid e three hardware features
that protect nonvolatile data from inadvertent writes.
- Noise Protection—A WE pulse typically less than 10ns
will not initiate a write cycle.
- Default VCC Sense—All write functions are inhibited
when VCC is 3.6V.
- Write Inhibit—Holding either OE LOW , WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Write cycle timing specifications must be observed
concurrently.
Software Data Protection
The X28C512, X28C513 offer a software controlled data
protection feature. The X28C512, X28C513 are shipped
from Intersil with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read and
write access of the device once VCC was stable.
The X28C512, X28C513 can be automatically protected
during power-up and power-down without the need for
external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C512,
X28C513 are also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data to
the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
CE
OE
WE
X28C512, X28C513
Last
Write
I/O6
HIGH Z
**
VOH
VOL
Ready
* Beginning and ending state of I/O6 will vary.
FIGURE 3A. TOGGLE BIT BUS SEQUENCE
Compare
X28C512
No
Yes
Ok?
Compare
Accum with
Addr N
Load Accum
From Addr N
Last Write
Ready
FIGURE 3B. TOGGLE BIT SOFTWARE FLOW
X28C512, X28C513
8FN8106.2
June 7, 2006
Software Data Protection
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 4A and 4B for the sequence. The three byte
sequence opens the page write window, enabling the host to
write from one to one hundred twenty-eig ht bytes of data.
Once the page load cycle has been completed, the device
will automatically be returned to the data protected state.
Regardless of whether the device has previously been
protected or not, once the software data protected algorithm
is used and data has been written, the X28C512, X28C513
will automatically disable further writes, unless another
command is issued to cancel it. If no further commands are
issued the X28C512, X28C513 will be write-protected during
power-down and after any subsequent power-up. The state
of A15 while executing the algorithm is “don’t care”.
Note: Once initiated, the sequence of write operations
should not be interrupted.
CE
WE
(VCC)
Write
Protected
VCC
0V
Data
Addr AAA
5555 55
2AAA A0
5555
≤ tBLC MAX
Writes
ok
Byte
or
Page
tWC
Note: All other timings and control pins are per page write timing requirements
FIGURE 4A. TIMING SEQUENCE—SOFTWARE DATA PROTECT ENABLE SEQUENCE FOLLOWED BY BYTE OR PAGE WRITE
Write Last
Write Data XX
to any
Write Data 80
to Address
5555
Write Data 55
to Address
2AAA
Write Data AA
to Address
5555
After tWC
Re-Enters Data
Protected State
Byte to
Last Address
Address
Optional
Byte/Page
Load Operation
FIGURE 4B. WRITE SEQUENCE FOR SOFTW ARE DA TA
PROTECTION
X28C512, X28C513
9FN8106.2
June 7, 2006
Resetting Software Data Protection
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the followin g si x step algorithm will
reset the internal protection circuit. After tWC, the X28C512,
X28C513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
System Considerations
Because the X28C512, X28C513 are frequently used in
large memory arrays, it is provi ded with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation and
eliminate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array . For a read operation
this assures that all deselected devices are in their standby
mode and that only the selected device(s) is/are outputting
data on the bus.
Because the X28C512, X28C513 have two power modes,
(standby and active), proper decoupling of the memory array
is of prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on the
output capacitive loading of the I/Os. Therefore, the larger
the array sharing a common bus, the larger the transi ent
spikes. The voltage peaks associated with the current
transients can be suppressed by the proper selection and
placement of decoupling capacitors. As a minimum, it is
recommended that a 0.1µF high frequency cerami c
capacitor be used between VCC and VSS at each device.
Depending on the size of the array , the value of the capacitor
may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each 8
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
CE
WE
Standard
Operating
Mode
VCC
Data
Addr
AAA
5555
55
2AAA
80
5555 ≥ tWC
AA
5555
55
2AAA
20
5555
Note: All other timings and control pins are per page write timing requirements
FIGURE 5A. Reset Software Data Protection Timing Sequence
Write Data 55
to Address
2AAA
Write Data 55
to Address
2AAA
Write Data A0
to Address
5555
Write Data AA
to Address
5555
Write Data 20
to Address
5555
Write Data AA
to Address
5555
FIGURE 5B. SOFTW ARE SEQUENCE TO DEACTIV A TE
SOFTWARE DATA PROTECTION
X28C512, X28C513
10 FN8106.2
June 7, 2006
Active Supply Current vs Ambient Temperature
S tandby Supply Current vs Ambient Temperature
ICC (RD) by Temperature Over Frequency
-55 -10 +125
10
11
12
13
14
Ambient Temperature (°C)
8
+35 +80
VCC = 5V
9
ICC (mA)
-55 -10 +125
0.14
0.16
0.18
0.2
0.24
Ambient Temperature (°C)
0.1
+35 +80
0.22
VCC = 5V
0.12
ISB (mA)
0315
30
40
50
60
5.0 VCC
Frequency (MHz)
10
69
-55°C
+25°C
+125°C
12
20
70
ICC (mA)
X28C512, X28C513
11 FN8106.2
June 7, 2006
NOTE:
2. This parameter is periodically sampled and not 100% tested.
Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias
X28C512, X28C513 . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28C512I/513I . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
X28C512M/513M . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with respect to VSS . . . . . . . . . . . . . . -1V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . .300°C
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications Over recommended operating conditions, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
ICC VCC current (active) (TTL inputs) CE = OE = VIL, WE = VIH, All I/O’s = open, address
inputs = 0.4V/2.4V Levels @ f = 5MHz 50 mA
ISB1 VCC current (standby) (TTL inputs) CE = VIH, OE = VIL, All I/O’s = open, other inputs = VIH 3mA
ISB2 VCC current (standby) (CMOS inputs) CE = VCC - 0.3V, OE = VIL, All I/O’s = Open, Other Inputs
= VIH 500 µA
ILI Input leakage current VIN = VSS to VCC 10 µA
ILO Output leakage current VOUT = VSS to VCC, CE = VIH 10 µA
VlL
(Note 1) Input LOW voltage -1 0.8 V
VIH
(Note 1) Input HIGH voltage 2V
CC + 1 V
VOL Output LOW voltage IOL = 2.1mA 0.4 V
VOH Output HIGH voltage IOH = -400µA 2.4 V
NOTE:
1. VIL min. and VIH max. are for reference only and are not tested.
Power-Up Timing
SYMBOL PARAMETER MAX UNIT
tPUR (Note 2) Power-up to read operation 100 µs
tPUW (Note 2) Power-up to write operation 5 ms
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL PARAMETER TEST CONDITIONS MAX UNIT
CI/O (Note 2) Input/output capacitance VI/O = 0V 10 pF
CIN (Note 2) Input capacitance VIN = 0V 10 pF
Endurance and Data Retention
PARAMETER MIN MAX UNIT
Endurance 10,000 Cycles per byte
Endurance 100,000 Cycles per page
Data retention 100 Years
X28C512, X28C513
12 FN8106.2
June 7, 2006
Equivalent A.C. Load Circuit
Symbol Table
A.C. Conditions of Test
Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input and output timing levels 1.5V
Mode Selection
CE OE WE MODE I/O POWER
LLH Read DOUT Active
LHL Write DIN Active
HXX
Standby and write
inhibit High Z Standby
XLX Write inhibit — —
XXH Write inhibit — —
5V
1.92kΩ
100pF
Output
1.37KΩ
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X28C512, X28C513
13 FN8106.2
June 7, 2006
Read Cycle
NOTE:
3. tLZ min. , tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. a re measured , wit h CL = 5pF from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
AC Electrical Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL PARAMETER
X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25
UNIT
X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ CYCLE LIMITS
tRC Read cycle time 90 120 150 200 250 ns
tCE Chip enable access time 90 120 150 200 250 ns
tAA Address access time 90 120 150 200 250 ns
tOE Output enable access time 40 50 50 50 50 ns
tLZ
(Note 3) CE LOW to active output 0 0 0 0 0 ns
tOLZ
(Note 3) OE LOW to active output 0 0 0 0 0 ns
tHZ
(Note 3) CE HIGH to high Z output 40 50 50 50 50 ns
tOHZ
(Note 3) OE HIGH to high Z output 40 50 50 50 50 ns
tOH Output hold from address change 0 0 0 0 0 ns
tCE
tRC
Address
CE
OE
WE
Data Valid
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
Data I/O
VIH
HIGH Z
Data Valid
X28C512, X28C513
14 FN8106.2
June 7, 2006
WE Controlled Write Cycle
NOTE:
4. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete the internal write operation.
Write Cycle Limits
SYMBOL PARAMETER MIN MAX UNIT
tWC (Note 4) Write cycle time 10 ms
tAS Address setup time 0 ns
tAH Address hold time 50 ns
tCS Write setup time 0 ns
tCH Write hold time 0 ns
tCW CE pulse width 100 ns
tOES OE HIGH setup time 10 ns
tOEH OE HIGH hold time 10 ns
tWP WE pulse width 100 ns
tWPH WE High recovery 100 ns
tDV Data valid 1µs
tDS Data setup 50 ns
tDH Data hold 0 ns
tDW Delay to next write 10 µs
tBLC Byte load cycle 0.2 100 µs
Address
tAS
tWC
tAH
tOES
tDV
tDS tDH
tOEH
CE
WE
OE
Data In
Data Out
HIGH Z
Data Valid
tCS tCH
tWP
X28C512, X28C513
15 FN8106.2
June 7, 2006
CE Controlled Write Cycle
Page Write Cycle
NOTES:
5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
Address
tAS
tOEH
tWC
tAH
tOES
tCS
tDV
tDS tDH
tCH
CE
WE
OE
Data In
Data Out
HIGH Z
Data Valid
tCW
tWPH
WE
OE
Last Byte
Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2
tWP
tWPH
tBLC
tWC
CE
Address*
I/O
*For each successive write within the page write operation, A7-A15 should be the same or
writes to an unknown address could occur.
(Note 6)
(Note 5)
X28C512, X28C513
16 FN8106.2
June 7, 2006
DATA Polling Timing Diagram (Note 7)
Toggle Bit Timing Diagram
NOTE:
7. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Address An
DIN = X
tWC
tOEH tOES
CE
WE
OE
I/O7
tDW
AnAn
DOUT = X DOUT = X
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z
*
*
*Starting and ending state will vary, depending upon actual tWC.
X28C512, X28C513
17 FN8106.2
June 7, 2006
Packaging Information
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
1.690 (42.95)
Max.
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
Pin 1
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.033 (0.84)
Typ. 0.055 (1.40)
0.610 (15.49)
0.500 (12.70)
0.100 (2.54) Max.
0°
15°
32-Lead Hermetic Dual In-Line Package Type D
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.005 (0.13) Min.
0.150 (3.81) Min.
0.015 (0.38)
0.008 (0.20)
Seating
Plane
X28C512, X28C513
18 FN8106.2
June 7, 2006
Packaging Information
0.150 (3.81) BSC
0.458 (11.63)
--
0.458 (11.63)
0.442 (11.22)
Pin 1
0.020 (0.51) x 45° Ref.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.050 (1.27) BSC
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.200 (5.08)
BSC
0.558 (14.17)
--
0.088 (2.24)
0.050 (1.27)
0.120 (3.05)
0.060 (1.52)
Pin 1 Index Corner
32-Pad Ceramic Leadless Chip Carrier Package Type E
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
0.300 (7.62)
BSC
0.015 (0.38)
Min.
0.400 (10.16)
BSC
0.560 (14.22)
0.540 (13.71)
DIA.
0.015 (0.38)
0.003 (0.08)
X28C512, X28C513
19 FN8106.2
June 7, 2006
Packaging Information
32-Lead Ceramic Flat Pack Type F
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.019 (0.48)
0.015 (0.38)
0.045 (1.14) Max.
Pin 1 Index
132
0.120 (3.05)
0.090 (2.29)
0.026 (0.66)
0.007 (0.18)
0.004 (0.10)
0.370 (9.40)
0.270 (6.86)
0.830 (21.08) Max.
0.050 (1.27) BSC
0.440 (11.18)
0.430 (10.93)
0.347 (8.82)
0.330 (8.38)
0.005 (0.13) Min.
0.030 (0.76)
Min.
1.228 (31.19)
1.000 (25.40)
Min.
X28C512, X28C513
20 FN8106.2
June 7, 2006
X28C512, X28C513
Plastic Leaded Chip Carrier Packages (PLCC)
A1
A
SEATING
PLANE
0.015 (0.38)
MIN
VIEW “A”
D2/E2
0.025 (0.64)
0.045 (1.14) R
0.042 (1.07)
0.056 (1.42)
0.050 (1.27) TP
E
E1
PIN (1)
C
L
D1
D
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.050 (1.27)
MIN
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
VIEW “A” TYP.
0.004 (0.10) C
-C-
D2/E2
C
L
NE
ND
IDENTIFIER
(0.12) MDS
- B SAS
0.042 (1.07)
0.048 (1.22)
0.005
N32.45x55 (JEDEC MS-016AE ISSUE A)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.125 0.140 3.18 3.55 -
A1 0.060 0.095 1.53 2.41 -
D 0.485 0.495 12.32 12.57 -
D1 0.447 0.453 11.36 11.50 3
D2 0.188 0.223 4.78 5.66 4, 5
E 0.585 0.595 14.86 15.11 -
E1 0.547 0.553 13.90 14.04 3
E2 0.238 0.273 6.05 6.93 4, 5
N28 286
ND 7 7 7
NE 9 9 7
Rev. 0 7/98
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimen-
sions are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Al-
lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea-
sured at the extreme material condition at the body parting
line.
4. To be measured at seating plane contact point.
5. Centerline to be determined where center leads exit plastic
body.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num-
ber of leads on the two long sides of the package.
-C-
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8106.2
June 7, 2006
X28C512, X28C513
Ceramic Pin Grid Array Package (CPGA) G36.760x760A
36 LEAD CERAMIC PIN GRID ARRAY PACKAGE
Rev. 0 12/05
NOTE: All dimensions in inches (in parentheses in millimeters).
15 17 19 21 22
14 16 18 20 23
10 9 27 28
8 7 29 30
5 2 36 34 32
4 3 1 35 33
Typ. 0.100 (2.54)
All Leads
Pin 1 Index
NOTE: Leads 5, 14, 23, & 32
12 11 25 26
13
631
24
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.770 (19.56)
0.750 (19.05)
SQ
A
A
0.185 (4.70)
0.175 (4.45)
0.020 (0.51)
0.016 (0.41)
0.072 (1.83)
0.062 (1.57)
0.120 (3.05)
0.100 (2.54)
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.050 (1.27)
0.008 (0.20)
A
A
