IS61C1024H FEATURES High-speed access time: 15, 20, 25 ns Low active power: 750 mW (typical) Low standby power: 2 mW (typical) CMOS standby Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications Fully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V (10%) power supply FUNCTIONAL BLOCK DIAGRAM - 128K x 8 HIGH-SPEED CMOS STATIC RAM JANUARY 1996 DESCRIPTION The JSST 1S61C1024H is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM. They are fabricated using /SS/'s high-performance CMOS technology. This highly reliable process coupled with innovative circuit design tech- niques, yields higher performance and low power consump- tion devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The 1S61C1024H is available in 32-pin 300-mil and 400-mil plastic SOJ packages. 512 X 2048 AO-A16 > DECODER > MEMORY ARRAY vcc -> GND -> VO 1/00-/07 DATA CIRCUIT = COLUMN I/O A cei CE2 q_ CONTROL OE SCCCIRRCUIT WE 4 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1995, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. Rev. A 1/96 $R81995C0241IS61C1024H _ PIN DESCRIPTIONS PIN CONFIGURATION A0-A16 Address Inputs 32-Pin SOJ - oS CE1 Chip Enable 1 Input ne 01 32[] voc CE2 Chip Enable 2 Input Ai6 [2 31] A15 OE Output Enable Input ara [3 sof] cE2 ____ P P Ai2 4 29] WE WE Write Enable Input a7 Os 281] A13 /00-1/O7 Input/Output As 6 271] As 45 17 26[] ag Voc Power a4 Ls 25] Att GND Ground A3 [9 241] OE A2 TJ 10 23[] Aio Ai 14 22[] CE1 Ao 12 21] vo7 voo [J 13 20] 06 OPERATING RANGE vor Hu of vos Range Ambient Temperature Veco") voz [] 15 18[] vo4 Commercial 0C to +70C 5V + 10% GND [} 16 7H vos TRUTH TABLE Mode We CET CE2 OE W/OOperation Vcc Current Not Selected Xx H Xx Xx High-2 IsB1, IsB2 (Power-down) xX xX L xX High-2 IsB1, IsB2 Output Disabled H L H H High-Z Icc1, lec Read H L H L DouTt Icc1, Icc2 Write L L H Xx DIN Icc1, Icc2 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.5 to +7.0 Vv TBIAS Temperature Under Bias 55 to +125 C TsTG Storage Temperature 65 to +150 C Pr Power Dissipation 1.5 Ww lout DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 5 pF Court Output Capacitance Vout = OV 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vec = 5.0V. 2 Integrated Silicon Solution, Inc. Rev.A 1/96 $R81995C024IS61C1024H _ DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loH = -4.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.2 Veco + 0.5 Vv VIL Input LOW Voltage -0.3 0.8 Vv Iu Input Leakage GND < Vin s Vec 5 5 LA ILo Output Leakage GND < Vout < Vcc, Outputs Disabled 5 5 LA Notes: 1. Vit = -3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS (Over Operating Range) -15ns -20ns -25 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vcc Dynamic Operating Vcc =Max., 220 190 180 mA Supply Current lout = 0 mA, f = fax IsBt TTL Standby Current Vcc = Max., 60 60 60 mA (TTL Inputs) Vin = Vin or ViL CE1 > Vin or CE2<Vi_,f=0 Isp2 CMOS Standby Voc = Max., 50 50 50 mA Current (CMOS Inputs) CEI > Vcc -0.2V, CE2 <0.2V, Vin = Voc - 0.2V, or Vin<0.2V, f=0 Integrated Silicon Solution, Inc. 3 Rev. A 1/96 $R81995C024__ READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) IS61C1024H -15ns -20ns -25 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 15 20 25 ns TAA Address Access Time 15 _ 20 _ 25 ns toHa Output Hold Time 3 3 3 ns tacet CET Access Time 15 20 2 ns tace2 CE2 Access Time . _ 15 _ 20 25 ns tooe = OE Access Time 7 9 9 ns tizoe OE to Low-Z Output 0 0 0 ns tuzoe OE to High-Z Output 0 6 0 7 0 10 ns tizce1) CET to Low-Z Output 2 3 3 ns tizce2) CE2 to Low-Z Output 2 _ 3 _ 3 _ ns tuzce CET or CE2 to High-Z Output 0 8 0 9 0 10 ns teu) CET or CE2 to Power-Up 0 0 0 ns teo CET or CE2 to Power-Down 12 18 2 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 3ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1a and 1b AC TEST LOADS 480 480 5V 5V OUTPUT OUTPUT 30 pF 255 Q 5 pF 255 Q Including L Including jig and jig and scope = scope = Figure 1a. Figure 1b. 4 Integrated Silicon Solution, Inc. Rev.A 1/96 $R81995C024IS61C1024H AC WAVEFORMS READ CYCLE NO. 1) t tRC > ADDRESS sx SK at tAA j~ tOHA t TOHA DOUT DATA VALID READ CYCLE NO. 2) a tRC a ADDRESS mK je t{AA, _____ at LOH AD OE tDOE | tHZOE } CE1 a tLZOE~| mn ad LACE1/AACE2 |_| CE2 H ~ bet tLZCE1ALZCE2 {at tHZCE 1 DOUT Hier. x DATA VALID >_ bet {PU tp! ce y N SUPPLY 50% 50% CURRENT \ ISB Notes: 1. WE is HIGH for a Read Cycle. __ 2. The device is continuously selected. OE, CE1 = Vit, CE2 = Vin. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Silicon Solution, Inc. 5 Rev. A 1/96 $R81995C024__ WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range, Standard and Low Power) IS61C1024H -15ns -20ns -25 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twe Write Cycle Time 15 20 25 ns tscet CET to Write End 1200 = 15 0 2C ns tsce2 CE2 to Write End 12 _ 15 _ 20 ns taw Address Setup Time to Write End 12 _ 15 _ 20 _ ns THA Address Hold from Write End 0 _ 0 _ 0 ns tsa Address Setup Time 0 0 0 ns tewe WE Pulse Width 10 1200 = 15 ns tsp Data Setup to Write End 8 10 12 ns tHo Data Hold from Write End 0 _ 0 0 ns tuzwe WE LOW to High-Z Output 7 10 12 ns tizwe WE HIGH to Low-Z Output 2 2 2 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled) ~<a twC > ADDRESS mK tSCE1| a THA CEI \ Hy tSCE2 be CE2 4 N | A \ ~<a tAW i rs ~< {tPWE VA WE < y, a TSA. aN - tL7WE -~ DOUT DATA UNDEFINED J HIGH 2 < i tSD m~a tHD DIN DATA-IN VALID N 6 Integrated Silicon Solution, Inc. Rev.A 1/96 $R81995C024IS61C1024H WRITE CYCLE NO. 2 (CE1, CE2 Controlled) ?) a twc > ADDRESS mK att-1SA| tSCE1._ >- THA CE Xe Hf tsCcE2. } CE2 yo \N | A N\ <t tAW > ail tPWE > WE \ He -t tHZ7wE| -t tLZWE | DOUT DATA UNDEFINED HIGH 2 < VY tSD t~-e. tHD > DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CET LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. 1/O will assume the High-Z state if OE = Vir. ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. Package 15 1861C1024H-15J = 300-mil Plastic SOJ 15 1861C1024H-15K 400-mil Plastic SOJ 20 = 1861C1024H-20J 300-mil Plastic SOJ 20 1861C1024H-20K 400-mil Plastic SOJ 25 1861C1024H-25J 300-mil Plastic SOJ 25 1861C1024H-25K 400-mil Plastic SOJ Integrated Silicon Solution, Inc. 7 Rev. A 1/96 $R81995C024IS61C1024H 300-mil Plastic SOIC (J-Bend) Package Code: J N Oooo oo/ooooo D 300-mil Plastic SOIC (J-bend) (J) Inches Symbol Min Max Min Max Ref. Sid. No. Leads 28 32 A 0.128 0.140 _ 0.140 Al 0.020 0.030 0.020 _ A2 0.095 0.105 0.095 0.105 B 0.016 0.022 0.016 0.022 b 0.026 0.032 0.026 0.032 C 0.008 0.014 0.008 0.014 D 0.700 0.730 0.815 0.835 E 0.321 0.347 0.325 0.345 Et 0.292 0.305 0.295 0.305 E2 0.245 0.285 0.247 0.287 e 0.050 BSC 0.050 BSC S 0.023 0.045 0.023 0.035 Doooofoooooo < D > A- a ERR tL mi E 4 oe A -i E2 Notes: 1. 2. 3. 4. Controlling dimension: inches, unless otherwise specified. BSC = Basic lead spacing between centers. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. Rev.A 1/96 $R81995C024IS61C1024H 400-mil Plastic SOIC (J-Bend) Package Code: K N Oooo oo ooo oo ) : HWW YA UU cm E sy D > SEATING PLANE st < f >| = C rn i] -_| + y A2 OH te ft, 1 wi E2 Aa Cle 7 400-mil Plastic SOIC (J-bend) (K) Inches Symbol Min Max Min Max Ref. Std. No. Leads 28 32 A 0.128 0.148 0.131 0.145 Al 0.025 _ 0.025 _ A2 0.082 _ 0.082 _ B 0.016 0.020 0.013 0.021 b 0.026 0.032 0.024 0.032 C 0.007 0.0125 0.006 0.012 Notes: . . 007200780 0.800 0.8 1, Gonvoling dimension: Inches, unless otherwise specie E 0.435 0.445 0.430 0.445 3. Dimensions D and E1 do not include mold flash protru- Fi 0395 0.405 0395 0.405 sions and should be measured from the bottom of the E2 0.360 0.380 0.354 0.380 4. Hao ads shall be planar with respect to one another e 0.050 BSC 0.050 BSC within 0.004 inches at the seating plane. 8 _ 0.035 _ 0.045 Integrated Silicon Solution, Inc. 9 Rev. A 1/96 $R81995C024IS61C1024H ii NOTICE Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission. Integrated Silicon Solution, Inc. does notrecommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances. Copyright 1996 Integrated Silicon Solution, Inc. Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited. Integrated Silicon Solution, Inc. 680 Almanor Avenue Sunnyvale, CA 94086 Tel: (408) 733-4774 Fax: (408) 245-4774 10 Integrated Silicon Solution, Inc. Rev.A 1/96 $R81995C024