POWER MANAGEMENT
1www.semtech.com
SC1405B
High Speed Synchronous Power
MOSFET Smart Driver
Features
Applications
Revision: January 13, 2004
Typical Application Circuit
Description
The SC1405B is a Dual-MOSFET Driver with an internal
Overlap Protection Circuit to prevent shoot-through. Each
driver is capable of driving a 3000pF load in 15ns rise/
fall time and has ULTRA-LOW propagation delay from in-
put transition to the gate of the power FET’s. Adaptive
Overlap Protection circuit ensures that the synchronous
FET does not turn on until the top FET source has reached
a voltage low enough to prevent shoot-through. The de-
lay between the bottom gate going low to the top gate
transitioning high is externally programmable via a ca-
pacitor to minimize dead time. The bottom FET may be
disabled at light loads by keeping S_MOD low to trigger
asynchronous operation, thus saving the bottom FET’s
gate drive current and inductor ripple current. An inter-
nal voltage reference allows threshold adjustment for
an Output Over-Voltage protection circuitry, independent
of the PWM controller.
Under-Voltage-Lock-Out circuit is included to guarantee
that both driver outputs are off when Vcc is less than or
equal to 4.4V (typ) at supply ramp up (4.35V at supply
ramp down). A CMOS output provides status indication
of the 5V supply. A low enable input places the IC in stand-
by mode, reducing supply current to less than 10µA.
SC1405B is offered in a high pitch (.025” lead spacing)
TSSOP package.
Fast rise and fall times (15ns with 3000pf load)
14ns max. Propagation delay (BG going low)
Adaptive and programmable shoot-through
protection
Wide input voltage range (4.5-25V)
Power saving asynchronous mode control
Output overvoltage protection/overtemp shutdown
Under-Voltage lock-out and power ready signal
Less than 10µA stand-by current (EN=low)
Improved drive version of SC1405TS
High frequency (to 1.2MHz) operation allows use of
small inductors and low cost capacitors in place of
electrolytics
High Density/Fast transient microprocessor power
supplies
Motor Drives/Class-D amps
High efficiency portable computers
+
(20KHz-1MHz)
2.2
+
10uF,6.3V
MTB75N03
.1uF
SC1405
13
4
3
2
1
14
6
5 10
7
9
11
12
8
5817
MTB75N03
1.7V@30A
INPUT POWER, 5-20V
+
>>
75A,30V
75A,30V
<<< Output Feedback to PWM
Controller
+
+
Over-Voltage Sense
47pF
.22uF
Vcc
+
<<
2.2
PWM IN
<<
P_READY
+
DSPS_DR
22004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Absolute Maximum Ratings
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NOTE:
(1) Specification refers to application circuit in Figure 1.
Unless specified: -0 < θJ < 125°C; VCC = 6V; 4V < VBST < 26V
Electrical Characteristics - DC Operating Specifications
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3
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
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Electrical Characteristics - DC Operating Specifications
42004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Electrical Characteristics - AC Operating Specifications
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Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
5
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Timing Diagrams
62004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Pin Configuration Ordering Information
Pin Descriptions
Top View
(14-Pin TSSOP)
eciveD
)1(
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J
)
RT.STB5041CS41-POSSTC°521ot0
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
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NOTE:NOTE:
NOTE:NOTE:
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
7
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Block Diagram
Applications Information
SC1405B SC1405B
SC1405B SC1405B
SC1405B is the higher speed version of the SC1405.
It is designed to drive Low Rds_On power MOSFET’s with
ultra-low rise/fall times and propagation delays. As the
switching frequency of PWM controllers is increased to
reduce power supply and Class-D amplifier volume and
cost, fast rise and fall times are necessary to minimize
switching losses (TOP MOSFET) and reduce Dead-time
(BOTTOM MOSFET) losses. While Low Rds_On MOSFET’s
present a power saving in I2R losses, the MOSFET’s die
area is larger and thus the effective input capacitance
of the MOSFET is increased. Often a 50% decrease in
Rds_On more than doubles the effective input gate
charge, which must be supplied by the driver. The Rds_On
power savings can be offset by the switching and dead-
time losses with a suboptimum driver. While discrete
solution can achieve reasonable drive capability, imple-
menting shoot-through, programmable delay and other
housekeeping functions necessary for safe operation can
become cumbersome and costly. The SC1405 family of
parts presents a total solution for the high-speed, high
power density =applications. Wide input supply range of
4.5V-25V allows use in battery powered applications, new
high voltage, distributed power servers as well as Class-
D amplifiers.
Theory of Operation
The control input (CO) to the SC1405B is typically sup-
plied by a PWM controller that regulates the power sup-
ply output. (See Application Evaluation Schematic, Fig-
ure 3). The timing diagram demonstrates the sequence
of events by which the top and bottom drive signals are
applied. The shoot-through protection is implemented
by holding the bottom FET off until the voltage at the
phase node (intersection of top FET source, the output
inductor and the bottom FET drain) has dropped below
1V. This assures that the top FET has turned off and
that a direct current path does not exist between the
input supply and ground, a condition which both the top
and bottom FET’s are on momentarily. The top FET is
also prevented from turning on until the bottom FET is
off. This time is internally set to 20ns (typical) and may
be increased by adding a capacitor from the C-Delay pin
to GND. The delay is approximately 1ns/pf in addition to
the internal 20ns delay. The external capacitor may be
needed if multiple High input capacitance MOSFET’s are
used in parallel and the fall time is substantially greater
than 20ns.
It must be noted that increasing the dead-time by high
values of C-Delay capacitor will reduce efficiency since
the parallel Schottky or the bottom FET body diode will
have to conduct during dead-time.
Layout Guidelines
As with any high speed , high current circuit, proper lay-
out is critical in achieving optimum performance of the
SC1405B. The Evaluation board schematic (Refer to
figure 3) shows a dual phase synchronous design with all
surface mountable components.
82004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
While components connecting to C-Delay, OVP_S, EN,S-
MOD, DSPS_DR and PRDY are relatively non-critical, tight
placement and short,wide traces must be used in layout
of The Drives, DRN, and especially PGND pin. The top
gate driver supply voltage is provided by bootstrapping
the +5V supply and adding it the phase node voltage
(DRN). Since the bootstrap capacitor supplies the charge
to the TOP gate, it must be less than .5” away from the
SC1405. Ceramic X7R capacitors are a good choice for
supply bypassing near the chip. The Vcc pin capacitor
must also be less than .5” away from the SC1405. The
ground node of this capacitor, the SC1405 PGND pin
and the Source of the bottom FET must be very close to
each other, preferably with common PCB copper land
and multiple vias to the ground plane (if used). The par-
allel Shottkey must be physically next to the Bottom FETS
Drain and source. Any trace or lead inductance in these
connections will drive current way from the Shottkey and
allow it to flow through the FET’s Body diode, thus reduc-
ing efficiency.
Preventing Inadvertent Bottom FET Turn-on
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the Bot-
tom FET’s gate through the Miller capacitance, Crss of
the bottom FET. The voltage appearing on the gate due
to this spike is:
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous imped-
ance of the capacitors. (since dV/dT and thus the effec-
tive frequency is very high). If the BG pin of the SC1405B
is very close to the bottom FET, Vspike will be reduced
depending on trace inductance, rate if rise of current,etc.
While not shown in Figure 4, a capacitor may be added
from the gate of the Bottom FET to its source, preferably
less than .5” away. This capacitor will be added to Ciss
in the above equation to reduce the effective spike volt-
age, Vspike.
The selection of the bottom MOSFET must be done with
attention paid to the Crss/Ciss ratio. A low ratio reduces
the Miller feedback and thus reduces Vspike. Also
Applications Information
MOSFETs with higher Turn-on threshold voltages will con-
duct at a higher voltage and will not turn on during the
spike. The MOSFET shown in the schematic (figure 4)
has a 2 volt threshold and will require approximately 5
volts Vgs to be conducting, thus reducing the possibility
of shoot-through. A zero ohm bottom FET gate resistor
will obviously help keeping the gate voltage low.
Ultimately, slowing down the top FET by adding gate re-
sistance will reduce di/dt which will in turn make the ef-
fective impedance of the capacitors higher, thus allow-
ing the BG driver to hold the bottom gate voltage low.
Ringing on the Phase Node
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is deter-
mined by:
Where:
Lst = The effective stray inductance of the top FET added
to trace inductance of the connection between top FET’s
source and the bottom FET’s drain added to the trace
resistance of the bottom FET’s ground connection.
Coss=Drain to source capacitance of bottom FET. If there
is a Shottkey used, the capacitance of the Shottkey is
added to the value.
Although this ringing does not pose any power losses
due to a fairly high Q, it could cause the phase node to
go too far negative, thus causing improper operation,
double pulsing or at worst driver damage. This ringing is
also an EMI nuisance due to its high resonant frequency.
Adding a capacitor, typically 1000-2000pf, in parallel with
Coss can often eliminate the EMI issue. If double puls-
ing is caused due to excessive ringing, placing 4.7-10
ohm resistor between the phase node and the DRN pin
of the SC1405 should eliminate the double pulsing.
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the volt-
age between VBST - VDRN. If the phase node negative
spikes are too large, the voltage on the boost capacitor
could exceed device’s absolute maximum rating of 8V.
ISSRSS
RSSIN
SPIKE CC(
C*V
V+
=
OSSST
RING C*L(*2(
1
FΠ
=
9
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
To eliminate the effect of the ringing on the boost ca-
pacitor voltage, place a 4.7 - 10 Ohm resistor between
boost Schottky diode and Vcc to filter the negative spikes
on DRN Pin. Alternately, a Silicon diode, such as the
commonly available 1N4148 can substitute for the
Schottky diode and eliminate the need for the series re-
sistor.
Proper layout will guarantee minimum ringing and elimi-
nate the need for external components. Use of SO-8 or
other surface mount MOSFETs will reduce lead induc-
tance and their parasitic effects.
ASYNCHRONOUS OPERATION
The SC1405B can be configured to operate in Asynchro-
nous mode by pulling S-MOD to logic LOW, thus disabling
the bottom FET drive. This has the effect of saving power
at light loads since the bottom FET’s gate capacitance
does not have to charged at the switching frequency.
There can be a significant savings since the bottom driver
can supply up to 2A pulses to the FET at the switching
frequency. There is an additional efficiency benefit to
operating in asynchronous mode. When operating in syn-
chronous mode, the inductor current can go negative
and flow in reverse direction when the bottom FET is on
and the DC load is less than 1/2 inductor ripple current.
Applications Information (Cont.)
At that point, the inductor core and wire losses, depend-
ing on the magnitude of the ripple current, can be quite
significant. Operating in asynchronous mode at light loads
effectively only charges the inductor by as much as
needed to supply the load current, since the inductor
never completely discharges at light loads. DC regula-
tion can be an issue when operating in asynchronous
mode, depending on the type of controller used and mini-
mum load required to maintain regulation. If there are
no Shottkey diodes used in parallel with bottom FET, the
FET’s body diode will need to conduct in asynchronous
mode. The high voltage drop of this diode must be con-
sidered when determining the criteria for this mode of
operation.
DSPS DR
This pin produces an output which is a logical duplicate
of the bottom FET’s gate drive, if S-MOD is held LOW.
OVP_S/OVER TEMP SHUTDOWN
Output over-voltage protection may be implemented on
the SC1405 independent of the PWM controller . A volt-
age divider from the output is compared with the inter-
nal bandgap voltage of 1.2V (typical). Upon exceeding
this voltage, the overvoltage comparator disables the top
FET, while turning on the bottom FET to allow discharge
of the output capacitors excessive voltage through the
output inductor. There should be sufficient RC time con-
stant as well as voltage headroom on the OVP_S pin to
assure it does not enter overvoltage mode inadvertently.
The SC1405 will shutdown if its Tj exceeds 165°C.
102004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
PIN Descriptions
Typical Characteristics
Performance diagrams, Application Evaluation Board.
Figure 1: PWM input and Gate drive switching
waveforms. The MOSFETs driven are shown
on Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
Figure 2: PWM input and Gate drive and phase
node switching waveforms with time scale ex-
panded. The MOSFETs driven are shown on
Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
Figure 3: PWM input and Gate drive and phase
node switching waveforms with time scale
expanded. The MOSFETs driven are shown
on Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
11
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Evaluation Board Schematic
Figure 4 - APPLICAFigure 4 - APPLICA
Figure 4 - APPLICAFigure 4 - APPLICA
Figure 4 - APPLICATION EVTION EV
TION EVTION EV
TION EVALAL
ALAL
ALUU
UU
UAA
AA
ATION BOTION BO
TION BOTION BO
TION BOARD SCHEMAARD SCHEMA
ARD SCHEMAARD SCHEMA
ARD SCHEMATICTIC
TICTIC
TIC
Vid0
Vid3
Vid1
Vid2
Vid4
Vin
VIN
EN
+12V
Vcc
5-7V
Vcc
VCORE
OVP
PIT1103 _1uh
L2
R5
0
R6
0
R9
0
R13
0
C20
.1
C14
.1
R11
1K
C24
220pf
R1
.002
R3
10
10nf
C9
FDB 6035
Q1
R16
7.5K
R12
2.2
D4
5819
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5819
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Q3
1uf
C11
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L1
C16
.01
R4
10k
R8
7.5K
10uf
C21
10u,CE R
C19
1u,16V
C7
10u,CE R
C5
R2
10
10u,CE R
C22
10u,CE R
C1
10u,CE R
C29
U1
SC1405B
13
4
3
2
1
14
6
510
7
9
11
12
8
TG
CO
GND
EN
OVP_S
BST
DELA Y_ C
S_MO D PGND
PRDY
BG
DSPS_DR
DRN
Vcc
C27
.01
10u,CE R
C17
820uf,OS
C10
U3
SC1405B
13
4
3
2
1
14
6
510
7
9
11
12
8
TG
CO
GND
EN
OVP_S
BST
DELA Y_ C
S_MO D PGND
PRDY
BG
DSPS_DR
DRN
Vcc
10u,CE R
C4
FDB 7030
Q2
820uf,OS
C13
R20
3.6K 10u,CE R
C23
R14
13K
R10
120K
U?
SC2422-P
12
9
2
3
1
13
7
5
611
14
4
10
15
16
8
OUT2
GND
VID3
VID2
VID4
OUT1
FB
VID0
ERROUT OC-
OC+
VID1
UVLO
BGOUT
VCC
RREF
FDB 7030
Q4
10u,CE R
C15
R15
26.1k
33uf,OS
C2
10u,CE R
C18
C12
10uf
1uf
C3
10nf
C26
1uf
C6
10u,CE R
C28
10u,CE R
C25
1000uf,16V
C8
J1
INPUT
1
2
3
4
5
6
R17
1
R7
2.2
C30
.1
R19
7.5K R18
7.5K
All VIDs OFF disables the
SC2422 Controller.
122004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Evaluation Board Bill of Materials
metI.ytQecnerefeReulaVrerutcafunaM
121,32C,22C,91C,81C,71C,51C,5C,4C,1C
92C,82C,52C
.reC,u10KDT,ataruM
212CSO,fu33oynaS
33 11C,6C,3CFu1
417CV61,u1
518CV61,fu0001cinosanaP
62 62C,9Cfn01
72 31C,01CSO,fu028oynaS
82 21C,12Cfu01
93 03C,02C,41C1.
012 72C,61C10.
11142Cfp022
212 2D,4D9185
3111JTUPNI
412 1L,2Lhul_3011TIP)moc.asuoclaF(oclaF
512 3Q,1Q5306BDFdlihcriaF
612 4Q,2Q0307BDFdlihcriaF
7111R200.elaD
812 2R,3R01
9114Rk01
024 31R,9R,6R,5R0
122 7R,21R2.2
224 91R,81R,61R,8RK5.7
32101RK021
42111RK1
52141RK31
62151Rk1.62
72171R1
82102RK6.3
9212U2242CShcetmeS
032 3U,1UB5041CShcetmeS
13
2004 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1405B
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Outline Drawing -TSSOP-14
Contact Information
Land Pattern - TSSOP-14