SPOC-BTS5572E - Infineon Technologies AG

SPOC - BTS5572E

SPI Power Controller

Data Sheet, Rev. 1.0, May 2008

Automotive Power

Data Sheet 2 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Table of Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Pin Assignment SPOC - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3 Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.5 Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.6 Loss of VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.8 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1 Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.2 Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.3 Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11 Package Outlines SPOC - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table of Contents

PG-DSO-36-36

Type Package Marking

SPOC - BTS5572E PG-DSO-36-36 BTS5572E

Data Sheet 3 Rev. 1.0, 2008-05-15

SPI Power Controller

for Advanced Light Control

with Integrated LED Mode

SPOC - BTS5572E

1Overview

Features

• 8 bit serial peripheral interface (daisy chain capable SPI) for control

and diagnosis

• CMOS compatible parallel input pins for each channel provide direct

PWM operation

• Selectable AND- / OR-combination for parallel inputs (PWM control)

• Very low stand-by current

• Enhanced electromagnetic compatibility (EMC) for bulbs as well as

LED

• Stable behavior at under voltage

• Device ground independent from load ground

• Green Product (RoHS-Compliant)

• AEC Qualified

Description

The SPOC - BTS5572E is a five channel high-side smart power switch in PG-DSO-36-36 package providing

embedded protective functions. It is specially designed to control standard exterior lighting in automotive

applications. In order to use the same hardware, the device can be configured to bulb or LED mode. As a result,

both load types are optimized in terms of switching and diagnosis behavior.

It is designed to drive lamps up to 3*27W + 2*10W.

Product Summary

Operating Voltage Power Switch VBB 5.5 … 28 V

Logic Supply Voltage VDD 3.8…5.5V

Over Voltage Protection VBB(AZ,min) 40 V

Maximum Stand-By Current at 25 °CIBB(OFF) 3µA

On-State Resistance at Tj = 150 °C

channel 0, 1, 2

channel 3, 4

RDS(ON,max) 100 mΩ

260 mΩ

SPI Access Frequency fSCLK(max) 2MHz

SPOC - BTS5572E

Overview

Data Sheet 4 Rev. 1.0, 2008-05-15

Configuration and status diagnosis are done via SPI. An 8 bit serial peripheral interface (SPI) is used. The SPI can

be used in daisy chain configuration.

The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be

enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis

word. A multiplexed switch bypass monitor provides short-circuit to VBB diagnosis.

In order to use the same hardware, channels OUT0, OUT1 and OUT2 can be configured to bulb or LED mode.

The SPOC - BTS5572E provides a fail-safe feature via a limp home input pin.

The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is

monolithically integrated in SMART technology.

Protective Functions

• Reverse battery protection with external components

• Short circuit protection

• Overload protection

• Multi step current limitation

• Thermal shutdown with latch and dynamic temperature sensor

• Overvoltage protection

• Loss of ground protection

• Electrostatic discharge protection (ESD)

Diagnostic Functions

• Multiplexed proportional load current sense signal (IS)

• Enable function for current sense signal configurable via SPI

• High accuracy of current sense signal at wide load current range

• Current sense ratio (kILIS) configurable for LEDs or bulbs

• Very fast diagnosis in LED mode (>2% duty cycle at 100 Hz)

• Feedback on over temperature and over load via SPI

• Multiplexed switch bypass monitor provides short circuit to VBB detection

Application Specific Functions

• Fail-safe activation via LHI pin and control via input pins

• Load type configuration via SPI (bulbs or LEDs) for optimized load control

Applications

• High-side power switch for 12 V grounded loads in automotive applications

• Especially designed for standard exterior lighting like tail light, brake light, parking light, license plate light,

indicators and equivalent LEDs

• Replaces electromechanical relays, fuses and discrete circuits

Data Sheet 5 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Block Diagram

2BlockDiagram

Figure 1 Block Diagram SPOC - BTS5572E

channel 0

power

supply

driver

logic

gate control

charge pump

clamp for

inductive

load

load current

lim itat ion

load current

sense

temperature

sensor

ESD

protection

IN2

IN3

IN4

IN0

IN1

GND

SPI

current sense multiplexerIS

SCLK

LHI limp home control

switch bypass

monitor

PWM control

VBB

OUT3

OUT2

OUT1

OUT0

OUT4

VDD

SPOC - BTS5572E

Block Diagram

Data Sheet 6 Rev. 1.0, 2008-05-15

2.1 Terms

The following figure shows all terms used in this data sheet.

Figure 2 Terms

In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each

channel separately (e.g. VDS specification is valid for VDS0 … VDS4).

All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the

values in bold letters (e.g. 0) are default values.

Terms_5.emf

IN 0

IN 1

IN 2

IN 3

IN0

IN1

IN2

IN3

VBB

SCLK

IN 2

IN 3

IN 4

VDD

IN 4

IN4

LHI

OUT0

OUT1

OUT3

OUT4

OUT3

OUT2

DS3

DS2

OUT2

GND

SC L K

SC LK

OUT1

OUT0

DS1

DS0

OUT4

DS4

Data Sheet 7 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Pin Configuration

3 Pin Configuration

3.1 Pin Assignment SPOC - BTS5572E

Figure 3 Pin Configuration PG-DSO-36-36

WRSYLHZ

287

9%%

































QF

287

287

QF

287

































287

287

287

QF

9%%

 



QF

6&/.

,1

,1

,1

,1

,1



9%%

H[SRVHGSDGERWWRP

/+,

9''

*1'

QF*

QF

SPOC - BTS5572E

Pin Configuration

Data Sheet 8 Rev. 1.0, 2008-05-15

3.2 Pin Definitions and Functions

Pin Symbol I/O Function

Power Supply Pins

19, 36, 37 1)

1) The exposed pad (pin 37) has to be connected to the power supply with a low impedance connection. The exposed pad

must be connected with a low thermal resistance.

VBB – Positive power supply for high-side power switch

2 VDD – Logic supply (5 V)

1 GND – Ground connection

Parallel Input Pins (integrated pull-down, leave unused input pins unconnected)

7 IN0 I Input signal of channel 0

8 IN1 I Input signal of channel 1

9 IN2 I Input signal of channel 2

10 IN3 I Input signal of channel 3

11 IN4 I Input signal of channel 4

Power Output Pins

32, 33, 34 2)

2) All outputs pins of each channel have to be connected.

OUT0 O Protected high-side power output of channel 0

29, 30, 31 2) OUT1 O Protected high-side power output of channel 1

22, 23, 24 2) OUT2 O Protected high-side power output of channel 2

27,28 2) OUT3 O Protected high-side power output of channel 3

25,26 2) OUT4 O Protected high-side power output of channel 4

SPI & Diagnosis Pins

6 CS I Chip select of SPI interface (low active), Integrated pull up

5 SCLK I Serial clock of SPI interface

4 SI I Serial input of SPI interface

3 SO O Serial output of SPI interface

14 IS O Diagnosis output signal

Limp Home Pin (integrated pull-down, leave unused limp home pin unconnected)

13 LHI I Limp home activation signal; Active high

Not connected Pin

12, 15, 20, 21, 35 n.c. – not connected, internally not bonded

16, 17, 18 n.c.* – not connected, internally not bonded, shorted together

Data Sheet 9 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Electrical Characteristics

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Absolute Maximum Ratings 1)

Tj = -40 °C to +150 °C; all voltages with respect to ground

(unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Conditions

min. max.

Supply Voltage

4.1.1 Power supply voltage VBB -0.3 28 V –

4.1.2 Logic supply voltage VDD -0.3 5.5 V –

4.1.3 Reverse polarity voltage according Figure 21 -Vbat(rev) –16VTj(Start) = 25 °C

t ≤ 2min. 2)

4.1.4 Supply voltage for full short circuit protection

(single pulse)

(Tj(0) = -40 °C … 150 °C)

VBB(SC) 020

VRECU = 20mΩ

RCable= 16mΩ/m

LCable= 1µH/m

l = 0 or 5m 3)

4.1.5 Voltage at power transistor VDS –40V–

4.1.6 Supply voltage for load dump protection VBB(LD) –40VRI = 2 Ω 4)

t = 400ms

4.1.7 Current through ground pin IGND -100 25 mA t ≤ 2min.

4.1.8 Current through VDD pin IDD -25 12 mA t ≤ 2min.

Power Stages

4.1.9 Load current IL-IL(LIM) IL(LIM) A5)

Diagnosis Pin

4.1.10 Current through sense pin IS IIS -10 10 mA t ≤ 2min.

Input Pins

4.1.11 Voltage at input pins VIN -0.3 8.0 V –

4.1.12 Current through input pins IIN -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

SPI Pins

4.1.13 Voltage at chip select pin VCS -0.3 5.7 V –

4.1.14 Current through chip select pin ICS -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

4.1.15 Voltage at serial input pin VSI -0.3 5.7 V –

4.1.16 Current through serial input pin ISI -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

4.1.17 Voltage at serial clock pin VSCLK -0.3 5.7 V –

4.1.18 Current through serial clock pin ISCLK -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

4.1.19 Current through serial output pin SO ISO -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

Limp Home Pin

4.1.20 Voltage at limp home input pin VLHI -0.3 8.0 V –

SPOC - BTS5572E

Electrical Characteristics

Data Sheet 10 Rev. 1.0, 2008-05-15

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

4.2 Thermal Resistance

4.1.21 Current through limp home input pin ILHI -0.75

-2.0

0.75

2.0

mA –

t ≤ 2min.

Temperatures

4.1.22 Junction temperature Tj-40 150 °C–

4.1.23 Dynamic temperature increase while switching ∆Tj–60K–

4.1.24 Storage temperature Tstg -55 150 °C–

ESD Susceptibility

4.1.25 ESD resistivity

OUT pins vs. VBB

other pins incl. OUT vs. GND

VESD

-4

-2

kV HBM 6)

–

1) Not subject to production test, specified by design.

2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product

(chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable, a thermal via array under the package contacted the first inner copper layer.

3) In accordance to AEC Q100-012 and AEC Q101-006.

4) RI is the internal resistance of the load dump pulse generator.

5) Current limitation is a protection feature. Operation in current limitation is considered as “outside” normal operating range.

Protection features are not designed for continuous repetitive operation.

6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5kΩ, 100pF).

Pos. Parameter Symbol Limit Values Unit Conditions

Min. Typ. Max.

4.2.1 Junction to Case 1)

1) Not subject to production test, specified by design.

RthJC ––2K/W–

4.2.2 Junction to Ambient 1) RthJA –22–K/W

2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product

(chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable, a thermal via array under the package contacted the first inner copper layer.

Absolute Maximum Ratings (cont’d)1)

Tj = -40 °C to +150 °C; all voltages with respect to ground

(unless otherwise specified)

Pos. Parameter Symbol Limit Values Unit Conditions

min. max.

Data Sheet 11 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Supply

5 Power Supply

The SPOC - BTS5572E is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power

switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between

pins VDD and GND is recommended as shown in Figure 21.

There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power

supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active

as soon as VDD is provided in the specified range independent of VBB. The first SPI transmission after a reset

contains at pin SO the read information from register OUT, the transmission error bit TER is set.

5.1 Power Supply Modes

The following table shows all possible power supply modes for VBB, VDD and the pin LHI.

Stand-by mode is entered as soon as the current sense multiplexer (DCR.MUX) is in default (stand-by) position 1).

Additionally, all thermal latches are cleared automatically. As soon as stand-by mode is entered, register

HWCR.STB is set. To wake-up the device, the current sense multiplexer (DCR.MUX) is programmed different to

default (stand-by) position.

Idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in

default position, and VDD supply is available.

Limp home (LHI = high) will wake-up the device and is working without VDD supply. As a result, all channels can

be activated via the dedicated input pins.

Power Supply Modes Off Off SPI on Reset Off Limp Home

mode

without SPI

Normal

operation

Limp Home

mode with

SPI 1)

1) SPI read only.

VBB 0V 0V 0V 0V 13.5V 13.5V 13.5V 13.5V

VDD 0V 0V 5V 5V 0V 0V 5V 5V

LHI 0V5V0V5V0V5V 0V 5V

PROFET operating – – – – –✓✓✓

Limp home –––––✓ –✓

SPI (logic) – – ✓reset reset reset ✓reset

Stand-by current – – – – ✓–✓2)

2) When DCR.MUX = 111b .

–

Idle current –––––– ✓3)

3) When all channels are in OFF-state and DCR.MUX!= 111b.

–

Diagnosis –––––– ✓✓

4) Current sense disabled in limp home mode.

1) Not affected by the inputs state

SPOC - BTS5572E

Power Supply

Data Sheet 12 Rev. 1.0, 2008-05-15

5.2 Reset

There are several reset triggers implemented in the device. They reset the SPI registers and errors flags to their

default values. The power stages are not affected by the reset signals.

The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT,

the transmission error bit TER is set.

Power-On Reset

The power-on reset is released, when VDD voltage level is higher than VDD(min). The SPI interface can be accessed

after wake up time tWU(PO).

Reset Command

There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As

soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after

transfer delay time tCS(td).

Limp Home Mode

In Limp Home mode, the SPI write-registers are reset. Output OUTx will follow the input INx configuration only.

For application example see Figure 21. The SPI interface is operating normally, so the limp home register bit LHI

as well as the error flags can be read, but any write command will be ignored. To activate the Limp Home mode,

LHI input pin voltage must be higher than VLHI(H).

Data Sheet 13 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Supply

5.3 Electrical Characteristics

Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.

Typical values show the typical parameters expected from manufacturing at VBB = 13.5 V, VDD = 4.3 V and

Tj=25°C.

Electrical Characteristics Power Supply

Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8V to 5.5V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

5.3.1 Operating voltage power switch VBB 5.5 – 281)

1) Not subject to production test, specified by design.

V–

5.3.2 Stand-by current for whole device with loads IBB(STB)

–

0.5

–

µAVDD = 0 V

VLHI = 0 V

Tj = 25 °C

Tj ≤ 85 °C 1)

Tj = 150 °C

5.3.3 Idle current for whole device with loads, all

channels off.

IBB(idle) –38mAVDD = 5 V 2)

DCR.MUX = 110B

2) In case of OUT.5 = 1b increased current consumption.

5.3.4 Logic supply voltage VDD 3.8 – 5.5 V –

5.3.5 Logic supply current IDD –55120µAVCS = 0 V

fSCLK = 0 Hz

5.3.6 Logic idle current IDD(idle) –2050µAVCS = VDD

fSCLK = 0 Hz

Chip in Standby

5.3.7 Operating current for whole device IGND – 1225mAfSCLK = 0 Hz

LHI Input Characteristics

5.3.8 L-input level at pin LHI VLHI(L) -0.3 – 1.0 V –

5.3.9 H-input level at pin LHI VLHI(H) 2.6 – 5.5 V –

5.3.10 L-input current through pin LHI ILHI(L) 3–85µAVLHI = 0.4 V

5.3.11 H-input current through pin LHI ILHI(H) 73085µAVLHI = 5 V

Reset

5.3.12 Power-On wake up time tWU(PO) 500 µs1)

SPOC - BTS5572E

Power Supply

Data Sheet 14 Rev. 1.0, 2008-05-15

5.4 Command Description

HWCR

Hardware Configuration Register

W/R1) RB1)

1) W/R Write/Read, RB Register Bank, ADDR Address

ADDR1) 3210

read1100xSTBCTL

write11000RSTCTL

Field Bits Type Description

RST 1 w Reset Command

0Normal operation

1 Execute reset command

STB 1 r Stand-by

0 Device is awake

1Device is in stand-by mode

Data Sheet 15 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Stages

6 Power Stages

The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There

are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register

OUT. Channels 0, 1 and 2 provides a load type configuration for bulbs or LEDs in register PLCR. The load type

configuration is allowed to be changed in OFF-state only.

6.1 Output ON-State Resistance

The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj.

Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 11.

Figure 4 Typical On-State Resistance

6.2 Input Circuit

There are two ways of using the input pins in combination with the OUT register by programming the HWCR.PWM

parameter.

•PLCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin.

•PLCR.PWM = 1: A channel is switched on by the according OUT register bit only, when the input pin is high. In

this configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register

OUT.

Figure 5 shows the complete input switch matrix.

Tj = 25 °C

100

150

200

250

300

350

400

0 5 10 15 20 25 30

[V]

DS(ON)

[mΩ]

Channel 0, 1, 2 (bulb)

Channel 0, 1, 2 (LED)

Channel 3, 4

VBB = 13.5 V

100

150

200

250

300

350

-50 0 50 100 150

[°C]

DS(ON)

[mΩ]

Channel 0, 1, 2 (bulb)

Channel 0, 1, 2 (LED)

Channel 3, 4

SPOC - BTS5572E

Power Stages

Data Sheet 16 Rev. 1.0, 2008-05-15

Figure 5 Input Switch Matrix

The current sink to ground ensures that the input signal is low in case of an open input pin. The zener diode

protects the input circuit against ESD pulses.

6.3 Power Stage Output

The power stages are built to be used in high side configuration (Figure 6).

Figure 6 Power Stage Output

InputMatrix_5.emf

IN0

IN1

IN2

IN3

IN4

Gate Driver 2

Gate Driver 1

Gate Driver 0

Gate Driver 4

Gate Driver 3

OUT2 OUT1 OUT0OUT4 OUT3

PWM

IN 0

IN 1

IN 2

IN 3

IN 4

Output .emf

OUT

GND V

OUT

VBB

VDS

Data Sheet 17 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Stages

The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission.

Figure 7 Switching a Load (resistive)

When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential,

because the inductance intends to continue driving the current. To prevent avalanche of the device, there is a

voltage clamp mechanism implemented which limits that negative output voltage to a certain level (VDS(CL)). See

Figure 6 for details. The maximum allowed load inductance is limited.

OUT

SwitchOn.emf

OFF

90%

10%

70%

dV/

30%

70%

dV/

OFF

30%

delay (O N)

delay(O FF )

IN /

OUTx

SPOC - BTS5572E

Power Stages

Data Sheet 18 Rev. 1.0, 2008-05-15

6.4 Electrical Characteristics

Electrical Characteristics Power Stages

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Output Characteristics

6.4.1 On-State resistance RDS(ON) mΩ

channel 0, 1, 2

–

170

300

–

100

–

375

PLCR.LEDn = 0

1) Tj = 25 °C / IL = 2.6 A

Tj = 150 °C / IL = 2.6 A

PLCR.LEDn = 1

1) Tj = 25 °C / IL = 0.6 A

Tj = 150 °C / IL = 0.6 A

channel 3, 4 –

–

110

200

–

260

1) Tj = 25 °C / IL = 1.3 A

Tj = 150 °C / IL = 1.3 A

6.4.2 Output voltage drop limitation at small load

currents

VDS(NL) mV

channel 0, 1, 2

–25–

PLCR.LEDn = 0

IL = 35 mA

channel 3, 4 – 25 – IL = 35 mA

6.4.3 Output clamp VDS(CL) 40 47 54 V IL = 20 mA 2)

6.4.4 Output leakage current per channel IL(OFF) µAVIN = 0 V or floating

OUT.OUTn = 0

channel 0, 1, 2 –

–

0.1

–

stand-by

idle

channel 3, 4 –

–

0.1

–

stand-by

idle

6.4.5 Inverse current capability per channel -IL(IC) A3)

channel 0, 1, 2 – 2.5 – –

channel 3, 4 – 1.0 – –

Input Characteristics

6.4.6 L-input level VIN(L) -0.3 – 1.0 V –

6.4.7 H-input level VIN(H) 2.6 – 5.5 V –

6.4.8 L-input current IIN(L) 32575µAVIN = 0.4 V

6.4.9 H-input current IIN(H) 10 40 75 µAVIN = 5 V

Data Sheet 19 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Stages

Timings

6.4.10 Turn-ON delay to

10% VBB

(Logical propagation delay from input INx to

output OUTx)

tdelay(ON) µsVBB = 13.5 V 1)

channel 0, 1, 2

–35–

PLCR.LEDn = 0

RL = 6.8 Ω

channel 3, 4 – 20 – RL = 18 Ω

6.4.11 Turn-OFF delay to

90% VBB

(Logical propagation delay from input INx to

output OUTx)

tdelay(OFF) µsVBB = 13.5 V 1)

channel 0, 1, 2

–50–

PLCR.LEDn = 0

RL = 6.8 Ω

channel 3, 4 – 30 – RL = 18 Ω

6.4.12 Turn-ON time to

90% VBB

tON µsVBB = 13.5 V

channel 0, 1, 2

–

250

100

PLCR.LEDn = 0

RL = 6.8 Ω

PLCR.LEDn = 1

RL = 33 Ω

channel 3, 4 – – 150 RL = 18 Ω

6.4.13 Turn-OFF time to

10% VBB

tOFF µsVBB = 13.5 V

channel 0, 1, 2

–

290

100

PLCR.LEDn = 0

RL = 6.8 Ω

PLCR.LEDn = 1

RL = 33 Ω

channel 3, 4 – – 150 RL = 18 Ω

6.4.14 Turn-ON slew rate

30% to 70% VBB

dV/ dtON V/µsVBB = 13.5 V

channel 0, 1, 2

0.1

0.2

0.75

0.5

1.9

PLCR.LEDn = 0

RL = 6.8 Ω

PLCR.LEDn = 1

RL = 33 Ω

channel 3, 4 0.1 0.45 0.9 RL = 18 Ω

Electrical Characteristics Power Stages (cont’d)

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

SPOC - BTS5572E

Power Stages

Data Sheet 20 Rev. 1.0, 2008-05-15

6.4.15 Turn-OFF slew rate

70% to 30% VBB

-dV/

dtOFF

V/µsVBB = 13.5 V

channel 0, 1, 2

0.1

0.2

0.75

0.5

1.9

PLCR.LEDn = 0

RL = 6.8 Ω

PLCR.LEDn = 1

RL = 33 Ω

channel 3, 4 0.1 0.5 0.9 RL = 18 Ω

1) Not subject to production test, specified by design.

2) The voltage increase until the current is reached.

3) Not subject to production test, specified by design. In case of inverse current (VOUT > VBB), the error flag ERR in the standard

diagnosis of the affected channel is cleared. The inverse current capability in ON-state and OFF-state is defined for Tj <

Tj(SC) and channel remains in same state (ON-state or OFF-state). Other channels can be affected (e.g. OUT latch due to

junction temperature increase).

Electrical Characteristics Power Stages (cont’d)

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Data Sheet 21 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Power Stages

6.5 Command Description

Note: In case of OUT.5 = 1b the device current consumption is increased.

OUT

Output Configuration Registers

W/R RB543210

read 0 x OUT4 OUT3 OUT2 OUT1 OUT0

write 0 0 OUT4 OUT3 OUT2 OUT1 OUT0

Field Bits Type Description

OUTn

n = 4 to 0

nrwSet Output Mode for Channel n

0Channel n is switched off

1 Channel n is switched on

PLCR

PWM and LED-Mode Configuration Register

W/R RB ADDR 3 2 1 0

read/write 1 0 1 PWM LED2 LED1 LED0

Field Bits Type Description

PWM 3 rw PWM Configuration

0Input signal OR-combined with according OUT register bit

1 Input signal AND-combined with according OUT register bit

LEDn

n = 2 to 0

nrwSet LED Mode for Channel n

0Channel n is in bulb mode

1 Channel n is in LED mode

SPOC - BTS5572E

Protection Functions

Data Sheet 22 Rev. 1.0, 2008-05-15

7 Protection Functions

The device provides embedded protective functions, which are designed to prevent IC destruction under fault

conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.

Protective functions are neither designed for continuous nor for repetitive operation.

7.1 Over Load Protection

The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple

steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS.

Please note that the voltage at the OUT pin is VBB -VDS. Please refer to following figures for details.

Figure 8 Current Limitation Channels 0, 1, 2 (minimum values)

Figure 9 Current Limitation Channels 3, 4 (minimum values)

Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to

rapid temperature rise inside.

Curr entLi mitati on012 .emf

5 101520 V

25 WDLR.LED = 0

WDLR.LED = 1

CurrentLimitation34 .emf

5101520 V

Data Sheet 23 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Protection Functions

7.2 Over Temperature Protection

Each channel has its own temperature sensor. If the temperature at the channel exceeds the thermal shutdown

temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). In order

to reactivate the channel, the temperature at the output must drop by at least the thermal hysteresis ∆Tj and the

over temperature latch must be cleared by SPI command HWCR.CTL = 1. All over temperature latches are cleared

by SPI command HWCR.CTL = 1.

Figure 10 Shut Down by Over Temperature

Additionally, all channels have their own dynamic temperature sensors. The dynamic temperature sensor

improves short circuit robustness by limiting sudden increases in the junction temperature. The dynamic

temperature sensor turns off the channel if its sudden temperature increase exceeds the dynamic temperature

sensor threshold ∆Tj(SW). Please refer to the following figure for details.

IIS

IL(LIM)

ERR

OverLoad .emf

CTL = 1

IN /

OUTx

SPOC - BTS5572E

Protection Functions

Data Sheet 24 Rev. 1.0, 2008-05-15

Figure 11 Dynamic Temperature Sensor Operations

The ERR-flag will be set during dynamic temperature sensor shut down. It can be reset by reading the ERR-flag.

If the channel is still in dynamic temperature sensor shut down, the ERR-flag will be set again.

7.3 Reverse Polarity Protection

In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well

as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected

loads. The current through the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the limp

home input pin has to be limited as well (please refer to the maximum ratings listed on Page 9).

Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity.

∆TjSW

IL(LIM)

IIS

delt aT . emf

ERR

Tj(SC)

CTL = 1

OUTx

Data Sheet 25 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Protection Functions

7.4 Over Voltage Protection

In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism

available for over voltage protection. The current through the ground connection has to be limited during over

voltage. Please note that in case of over voltage the pin GND might have a high voltage offset to the module

ground.

7.5 Loss of Ground

In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5572E

securely changes to or stays in off-state.

7.6 Loss of VBB

In case of loss of VBB connection in on-state, all inductances of the loads have to be demagnetized through the

ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for

reverse polarity reason, the ground connection is not available for demagnetization. Then for example, a resistor

can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND.

SPOC - BTS5572E

Protection Functions

Data Sheet 26 Rev. 1.0, 2008-05-15

7.7 Electrical Characteristics

Electrical Characteristics Protection Functions

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Over Load Protection

7.7.1 Load current limitation IL(LIM) AVDS = 7 V

channel 0, 1, 2 24 – 40 PLCR.LEDn = 0 1)

1) For Tj = 150 °C, not subject to production test. Device will shutdown due to the maximum junction temperature sensor.

6–12 PLCR.LEDn = 1 1)

channel 3, 4 8 – 18 1)

Over Temperature Protection

7.7.2 Thermal shut down temperature Tj(SC) 150 170 190 °C2)

7.7.3 Thermal hysteresis ∆Tj–7–K

2) Not subject to production test, specified by design.

7.7.4 Dynamic temperature increase limitation

while switching

∆Tjsw –60–K

Over Voltage

7.7.5 Overvoltage protection VBB(AZ) 40 47 54 V IBB = 4 mA

Data Sheet 27 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Protection Functions

7.8 Command Description

HWCR

Hardware Configuration Register

W/R RB ADDR 3 2 1 0

write 1 1 0 0 0 RST CTL

Field Bits Type Description

CTL 0 rw Clear Thermal Latch

0Thermal latches are untouched

1 Command: Clear all thermal latches

SPOC - BTS5572E

Diagnosis

Data Sheet 28 Rev. 1.0, 2008-05-15

8 Diagnosis

For diagnosis purpose, the SPOC - BTS5572E provides a current sense signal at pin IS and the diagnosis word

via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be

disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the

battery voltage. Please refer to Figure 12 for details.

Figure 12 Block diagram: Diagnosis

channel 0

load

current

sense

D ia g no sis_5.e m f

IS 0

current sense multiplexer

gate

contr ol

load current

limitation

latch temperature

sensor

ERR0

latch

DCR.MUX V

DS(SB)

SBM

DCR.

OUT4

OUT3

OUT2

OUT1

OUT0

VBB

Data Sheet 29 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Diagnosis

For diagnosis feedback at different operation modes, please see Table 1.

8.1 Diagnosis Word at SPI

The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR

combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard

diagnosis bits ERRn.

The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is

transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal.

The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control

block. The latches are cleared by SPI command HWCR.CTL.

Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command

(HWCR.CTL), the error flag is cleared during command transmission of the next SPI frame and ready for latching

after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL

command will indicate a failure mode at the previously affected channels although the thermal latches have been

cleared already. In case of continuous over load, the error flags are set again immediately because of the over

load monitoring signal.

Table 1 Operation Modes 1)

1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit.

x = undefined.

Operation Mode Input Level

OUT.OUTn

Output

Level VOUT

Current

Sense IIS

Error Flag

ERRn2)

2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI.

DCR.

SBM

Normal Operation (OFF) L / 0

(OFF-state)

GND Z 0 1

Short Circuit to GND GND Z 0 1

Thermal shut down Z Z 03) x

Short Circuit to VBB VBB Z 0 0

Open Load Z Z 0 x

Normal Operation (ON) H / 1

(ON-state)

~VBB IL/kILIS 00

Current Limitation < VBB Z1 x

Short Circuit to GND ~GND Z 1 1

Dynamic Temperature Sensor shut down Z Z 1 x

Thermal shut down Z Z 13)

3) The over temperature flag is set latched (in OFF states also) and can be cleared by SPI command HWCR.CTL.

Short Circuit to VBB VBB <IL/kILIS 00

Open Load VBB Z0 0

SPOC - BTS5572E

Diagnosis

Data Sheet 30 Rev. 1.0, 2008-05-15

8.2 Load Current Sense Diagnosis

There is a current sense signal available at pin IS which provides a current proportional to the load current of one

selected channel. The selection is done by a multiplexer which is configured via SPI.

Current Sense Signal

The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs.The ratio kILIS can be

adjusted to the load type (LED or bulb) via SPI register PLCR for channels 0 to 2. Usually a resistor RIS is connected

to the current sense pin. It is recommended to use resistors 2.5 kΩ<RIS <7kΩ. A typical value is 3.3 kΩ.

Figure 13 Current Sense Ratio kILIS Channel 0, 1, 2 Bulb and LED mode 1)

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

012345

Load current / Proportion of I

Lnom

Normalized k

ilis

value

kilis bulb max

kilis bulb typ

kilis bulb min

kilis led max

kilis led typ

kilis led min

Data Sheet 31 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Diagnosis

Figure 14 Current Sense Ratio kILIS Channel 3, 41)

In case of over current as well as over temperature, the current sense signal of the affected channel is switched

off. To distinguish between over temperature and over load, the SPI diagnosis word can be used. Whereas the

over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated

SPI command (HWCR.CTL).

Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can

be found in Figure 15.

Figure 15 Timing of Current Sense Signal

1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in

Section 8.4 (Position 8.4.1).

500

1000

1500

2000

2500

3000

3500

4000

0 0,5 1 1,5 2 2,5

Load current / Proportion of I

Lnom

Normalized k

ilis

value

kilis bulb max

kilis bulb typ

kilis bulb min

SenseTiming.emf

VOUT

IIS

tON

tsIS(ON) tsIS(LC)

OFF

tOFF

tdIS (OFF)

OFF

SPOC - BTS5572E

Diagnosis

Data Sheet 32 Rev. 1.0, 2008-05-15

Current Sense Multiplexer

There is a current sense multiplexer implemented in the SPOC - BTS5572E that routes the sense current of the

selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current

also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer

to Figure 16.

Figure 16 Timing of Current Sense Multiplexer

8.3 Switch Bypass Diagnosis

To detect short circuit to VBB, there is a switch bypass monitor implemented. In case of short circuit between the

output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short

circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by

the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS.

The switch bypass monitor compares the voltage VDS across the power transistor of that channel which is selected

by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI

MuxTim ing.em f

000

DCR.MUX 001110 110

sIS(EN)

sIS(MUX)

dIS(MUX)

Data Sheet 33 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Diagnosis

8.4 Electrical Characteristics

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Load Current Sense

8.4.1 Current sense ratio kILIS

channel 0, 1, 2 (bulb): PLCR.LEDn = 0

0.600 A

1.3 A

2.6 A

4.0 A

2450

2700

3100

3900

3700

3500

–

channel 0, 1, 2 (LED): PLCR.LEDn = 1

0.020 A

0.050 A

0.300 A

0.600 A

1.0 A

500

590

680

730

750

950

910

830

1400

1250

990

930

910

–

channel 3, 4:

0.020 A

0.050 A

0.150 A

0.300 A

0.600 A

1.3 A

2.0 A

800

1000

1200

1250

1350

1370

1800

1700

1600

1550

2750

2400

2200

1950

1850

1750

1730

–

8.4.2 Current sense voltage limitation VIS(LIM) 0.9VDD VDD 1.1VDD VIIS = 1 mA

SPOC - BTS5572E

Diagnosis

Data Sheet 34 Rev. 1.0, 2008-05-15

8.4.3 Current sense leakage / offset current IIS(en) ––1µAIL = 0

DCR.MUX = 000B

8.4.4 Current sense leakage, while diagnosis

disabled

IIS(dis) ––1µADCR.MUX = 110B

8.4.5 Current sense settling time after channel

activation

channel 0, 1, 2

tsIS(ON)

––300

µsVBB = 13.5 V

RIS = 3.3 kΩ

PLCR.LEDn = 0

RL = 6.8 Ω

––115

PLCR.LEDn = 1

RL = 33 Ω

channel 3, 4 – – 180 RL = 18 Ω

8.4.6 Current sense desettling time after

channel deactivation

tdIS(OFF)

––25

µsVBB = 13.5 V 1)

RIS = 3.3 kΩ

PLCR.LEDn = 0

––25 PLCR.LEDn = 1

8.4.7 Current sense settling time after change

of load current

channel 0, 1, 2

tsIS(LC)

––30

µsVBB = 13.5 V

RIS = 3.3 kΩ

PLCR.LEDn = 0

IL = 2.6 A to 1.3 A

channel 3, 4 – – 30 IL = 1.3 A to 0.6 A

8.4.8 Current sense settling time after current

sense activation

tsIS(EN) ––25µsRIS = 3.3 kΩ

DCR.MUX:

110B -> 000B

8.4.9 Current sense settling time after

multiplexer channel change

tsIS(MUX) ––30µsRIS = 3.3 kΩ

DCR.MUX:

000B -> 001B

8.4.10 Current sense deactivation time tdIS(MUX) ––25µsRIS = 3.3 kΩ

DCR.MUX:

001B -> 110B

Switch Bypass Monitor

8.4.11 Switch bypass monitor threshold VDS(SB) 0.7– 2.5V –

1) Not subject to production test, specified by design.

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C

typical values: VBB = 13.5 V, Tj = 25 °C

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Data Sheet 35 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Diagnosis

8.5 Command Description

DCR

Diagnosis Control Register

W/R RB ADDR 3 2 1 0

read 1 1 1 SBM MUX

write 1 1 1 0 MUX

Input Level

OUT.OUTn

Field Bits Type Description

L / 0

(OFF-state)

MUX 2:0 rw Set Current Sense Multiplexer Configuration

000 IS pin is high impedance

001 IS pin is high impedance

010 IS pin is high impedance

011 IS pin is high impedance

100 IS pin is high impedance

101 IS pin is high impedance

110 IS pin is high impedance

111 Stand-by mode (IS pin is high impedance)

SBM 3 r Switch Bypass Monitor1)

0VDS < VDS(SB)

1VDS > VDS(SB)

1) Invalid in stand-by mode

H / 1

(ON-state)

MUX 2:0 rw Set Current Sense Multiplexer Configuration

000 current sense of channel 0 is routed to IS pin

001 current sense of channel 1 is routed to IS pin

010 current sense of channel 2 is routed to IS pin

011 current sense of channel 3 is routed to IS pin

100 current sense of channel 4 is routed to IS pin

101 IS pin is high impedance

110 IS pin is high impedance

111 Stand-by mode (IS pin is high impedance)

SBM 3 r Switch Bypass Monitor1)

0VDS < VDS(SB)

1VDS > VDS(SB)

SPOC - BTS5572E

Diagnosis

Data Sheet 36 Rev. 1.0, 2008-05-15

Standard Diagnosis

CS76543210

TER 0LHI x ERR4 ERR3 ERR2 ERR1 ERR0

Field Bits Type Description

ERRn

n = 4 to 0

nrError flag Channel n

0 normal operation

1 failure mode occurred

Data Sheet 37 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

9 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,

SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS

indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on

line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter

ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain

capability.

Figure 17 Serial Peripheral Interface

9.1 SPI Signal Description

CS - Chip Select:

The system micro controller selects the SPOC - BTS5572E by means of the CS pin. Whenever the pin is in low

state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and

SO is forced into a high impedance state.

CS High to Low transition:

• The requested information is transferred into the shift register.

• SO changes from high impedance state to high or low state depending on the logic OR combination between

the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,

a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.

CS Low to High transition:

• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK

signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the

command is ignored.

• Data from shift register is transferred into the addressed register.

SCLK - Serial Clock:

This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling

edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.

It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.

SI - Serial Input:

Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge

of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for

further information.

LSB654 321

LSB654 321CS MSB

MSB

SCLK

time

SPI.emf

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

Data Sheet 38 Rev. 1.0, 2008-05-15

SO Serial Output:

Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin

goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5

for further information.

9.2 Daisy Chain Capability

The SPI of SPOC - BTS5572E provides daisy chain capability. In this configuration several devices are activated

by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see

Figure 18), in order to build a chain. The ends of the chain are connected with the output and input of the master

device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the

SCLK line of each device in the chain.

Figure 18 Daisy Chain Configuration

In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The

bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.

In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy

chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in

daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high

(see Figure 19).

Figure 19 Data Transfer in Daisy Chain Configuration

device 1

SPI

SCLK

device 2

SPI

SCLK

device 3

SPI

SCLK

MCS

MCLK

SPI _DaisyChain . emf

MCS

MCLK

SI device 3 SI device 2 SI device 1

SO devi ce 3 S O devi ce 2 SO devi ce 1

time

SPI _DasyChain2.emf

Data Sheet 39 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

9.3 Timing Diagrams

Figure 20 Timing Diagram SPI Access

9.4 Electrical Characteristics

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C, VDD = 3.8 V to 5.5 V

typical values: VBB = 13.5 V, Tj = 25 °C, VDD = 4.3 V

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Input Characteristics (CS, SCLK, SI)

9.4.1 L level of pin

SCLK

VCS(L)

VSCLK(L)

VSI(L)

-0.3

–

1.0

VVDD = 4.3 V

–

9.4.2 H level of pin

SCLK

VCS(H)

VSCLK(H)

VSI(H)

2.6

–

5.5

VVDD = 4.3 V

–

9.4.3 L-input pull-up current at CS pin -ICS(L) 10 30 85 µAVDD = 4.3 V

VCS = 0 V

9.4.4 H-input pull-up current at CS pin -ICS(H) 3–85µAVDD = 4.3 V

VCS = 2.6 V

9.4.5 L-input pull-down current at pin

SCLK

ISCLK(L)

ISI(L)

–

µAVDD = 4.3 V

VSCLK = 0.4 V

VSI = 0.4 V

9.4.6 H-input pull-down current at pin

SCLK

ISCLK(H)

ISI(H)

µAVDD = 4.3 V

VSCLK = 4.3 V

VSI = 4.3 V

Output Characteristics (SO)

9.4.7 L level output voltage VSO(L) 0–0.5VISO = -0.5 mA

SCLK

tCS(lead) tCS( td )

tCS( l a g )

tSCL K( H) tSCL K( L )

tSCL K( P)

tSI( su) tSI( h)

tSO( v)

SO( e n ) tSO( d is)

0. 7V

0. 2V

0. 7V

0. 2V

0. 7V

0. 2V

0. 7V

0. 2V

SPI Timing.emf

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

Data Sheet 40 Rev. 1.0, 2008-05-15

9.4.8 H level output voltage VSO(H) VDD -

0.5 V

–VDD V ISO = 0.5 mA

VDD = 4.3 V

9.4.9 Output tristate leakage current ISO(OFF) -10 – 10 µAVCS =VDD

Timings

9.4.10 Serial clock frequency fSCLK 0–2MHz–

9.4.11 Serial clock period tSCLK(P) 500 – – ns –

9.4.12 Serial clock high time tSCLK(H) 250 – – ns –

9.4.13 Serial clock low time tSCLK(L) 250 – – ns –

9.4.14 Enable lead time (falling CS to rising

SCLK)

tCS(lead) 1––µs–

9.4.15 Enable lag time (falling SCLK to rising

CS)

tCS(lag) 1––µs–

9.4.16 Transfer delay time (rising CS to

falling CS)

tCS(td) 1––µs–

9.4.17 Data setup time (required time SI to

falling SCLK)

tSI(su) 100 – – ns –

9.4.18 Data hold time (falling SCLK to SI) tSI(h) 100 – – ns –

9.4.19 Output enable time (falling CS to SO

valid)

tSO(en) ––1µsCL = 20 pF 1)

9.4.20 Output disable time (rising CS to SO

tri-state)

tSO(dis) ––1µsCL = 20 pF 1)

9.4.21 Output data valid time with capacitive

load

tSO(v) – – 250 ns CL = 20 pF 1)

1) Not subject to production test, specified by design.

Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C, VDD = 3.8 V to 5.5 V

typical values: VBB = 13.5 V, Tj = 25 °C, VDD = 4.3 V

Pos. Parameter Symbol Limit Values Unit Test Conditions

min. typ. max.

Data Sheet 41 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

9.5 SPI Protocol

Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame

the output at SPI signal SO will contain the requested information. A new command can be executed in the

second frame.

CS1)

1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition.

76543210

Write OUT Register

SI 1 0 0 OUT4 OUT3 OUT2 OUT1 OUT0

Read OUT Register

SI 00xxxxx0

Write Configuration Register

SI 1 1 ADDR DATA

Read Configuration Register

SI 0 1 ADDR x x x 0

Read Standard Diagnosis

SI 0xxxxxx1

Standard Diagnosis

SO TER 0 LHI x ERR4 ERR3 ERR2 ERR1 ERR0

Second Frame of Read Command

SO TER 1 0 0 OUT4 OUT3 OUT2 OUT1 OUT0

SO TER 1 1 ADDR DATA

Field Bits Type Description

RB 6 rw Register Bank

0Read / write to the OUTx channel

1 Read / write to the other register

TER CS r Transmission Error

0Previous transmission was successful (modulo 8 clocks received)

1 Previous transmission failed or first transmission after reset

OUTx

x = 4 to 0

xrwOutput Control Register of Channel x

0OFF

1ON

ADDR 5:4 rw Address

Pointer to register for read and write command

DATA 3:0 rw Data

Data written to or read from register selected by address ADDR

LHI 6 r Limp Home Enable

0L-input signal at pin LHI

1 H-input signal at pin LHI

ERRx

x = 4 to 0

xrDiagnosis of Channel x

0No failure

1 Over temperature, over load or short circuit

SPOC - BTS5572E

Serial Peripheral Interface (SPI)

Data Sheet 42 Rev. 1.0, 2008-05-15

9.6 Register Overview

Name W/R RB 5 4 3 2 1 0 default1)

1) The default values are set after reset.

OUT W/R 0 0 OUT4 OUT3 OUT2 OUT1 OUT0 00H

Name W/R RB ADDR 3 2 1 0 default1)

PLCR W/R 1 0 1 PWM LED2 LED1 LED0 00H

HWCR R 1 1 0 0 x STB CTL 02H

W 11000RSTCTL -

DCR R 1 1 1 SBM MUX 07H

W1110 MUX -

Data Sheet 43 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Application Description

10 Application Description

Figure 21 Application Circuit Example

µC

e.g. XC2267

VSS

SPI

VBB

LHI

GND

OUT3

OUT2

OUT1

OUT0

OUT4

GND

Limp_Home

VCC

bat

3.9k Ω

VDD

100nF

500 Ω

Limp_Home

8kΩ

3.3k Ω

1k Ω

1nF

GPIO

SCLK

IN1

IN2

IN3

IN4

IN0

Circuit_5.emf

SPI

8kΩ

10nF.. 100nF

27 W

10 W

68nF

* For filter ing and

protection pur poses

SPOC - BTS5572E

Package Outlines SPOC - BTS5572E

Data Sheet 44 Rev. 1.0, 2008-05-15

11 Package Outlines SPOC - BTS5572E

Figure 22 PG-DSO-36-36 (Plastic Dual Small Outline Package)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

PG-DSO-36-36-PO V01

Exposed Diepad

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Does not include dambar protrusion of 0.05 max. per side

(spherical shape)

Package

Index Marking Ejector Mark

Leadframe

(flat shape)

Ex Ey

0.65

Bottom View

0 ... 0.1

0.35 x 45°

8° MAX.

0.17

A-B DC 36x

±0.08

0.33

C0.1

2.45-0.2

2.55 MAX.

-0.2

7.6

±0.2

0.7

±0.3

10.3 D

0.23

+0.09

118

1936

-0.2

12.8

3619

18 1

Index Marking

(spherical shape)

Exposed Diepad Dimensions

PG-DSO-36-36 C66065-A6940-C016 6.8 4.2

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Data Sheet 45 Rev. 1.0, 2008-05-15

SPOC - BTS5572E

Revision History

12 Revision History

Revision Date Changes

1.0 2008-05-15 Initial revision

Edition 2008-05-15

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

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