Data Sheet, Rev. 1.0, May 2008 SPOC - BTS5572E SPI Power Controller Automotive Power SPOC - BTS5572E Table of Contents Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignment SPOC - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 4.1 4.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 5.1 5.2 5.3 5.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 14 6 6.1 6.2 6.3 6.4 6.5 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 18 21 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 24 25 25 25 26 27 8 8.1 8.2 8.3 8.4 8.5 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 30 32 33 35 9 9.1 9.2 9.3 9.4 9.5 9.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 38 39 39 41 42 10 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 Package Outlines SPOC - BTS5572E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Sheet 2 Rev. 1.0, 2008-05-15 SPI Power Controller SPOC - BTS5572E for Advanced Light Control with Integrated LED Mode 1 Overview Features * * * * * * * * * 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnosis CMOS compatible parallel input pins for each channel provide direct PWM operation Selectable AND- / OR-combination for parallel inputs (PWM control) Very low stand-by current Enhanced electromagnetic compatibility (EMC) for bulbs as well as LED Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified PG-DSO-36-36 Description The SPOC - BTS5572E is a five channel high-side smart power switch in PG-DSO-36-36 package providing embedded protective functions. It is specially designed to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is designed to drive lamps up to 3*27W + 2*10W. Product Summary Operating Voltage Power Switch Logic Supply Voltage Over Voltage Protection Maximum Stand-By Current at 25 C On-State Resistance at Tj = 150 C VBB VDD VBB(AZ,min) IBB(OFF) RDS(ON,max) 5.5 ... 28 V fSCLK(max) 2 MHz channel 0, 1, 2 channel 3, 4 SPI Access Frequency 3.8 ... 5.5 V 40 V 3 A 100 m 260 m Type Package Marking SPOC - BTS5572E PG-DSO-36-36 BTS5572E Data Sheet 3 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Overview Configuration and status diagnosis are done via SPI. An 8 bit serial peripheral interface (SPI) is used. The SPI can be used in daisy chain configuration. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides short-circuit to VBB diagnosis. In order to use the same hardware, channels OUT0, OUT1 and OUT2 can be configured to bulb or LED mode. The SPOC - BTS5572E provides a fail-safe feature via a limp home input pin. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is monolithically integrated in SMART technology. Protective Functions * * * * * * * * Reverse battery protection with external components Short circuit protection Overload protection Multi step current limitation Thermal shutdown with latch and dynamic temperature sensor Overvoltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions * * * * * * * Multiplexed proportional load current sense signal (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs Very fast diagnosis in LED mode (>2% duty cycle at 100 Hz) Feedback on over temperature and over load via SPI Multiplexed switch bypass monitor provides short circuit to VBB detection Application Specific Functions * * Fail-safe activation via LHI pin and control via input pins Load type configuration via SPI (bulbs or LEDs) for optimized load control Applications * * * High-side power switch for 12 V grounded loads in automotive applications Especially designed for standard exterior lighting like tail light, brake light, parking light, license plate light, indicators and equivalent LEDs Replaces electromechanical relays, fuses and discrete circuits Data Sheet 4 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Block Diagram 2 Block Diagram VBB VD D pow er s upply IN 0 driv er logic IN 1 IN 2 IN 3 LH I ESD protec tion c lam p for induc tiv e load gate c ontrol & c harge pum p load c urrent s ens e IN 4 IS tem perature s ens or load c urrent lim itation 4 23 channel 0 1 c urrent s ens e m ultiplex er s w itc h by pas s m onitor lim p hom e c ontrol PW M c ontrol OU T4 OU T3 OU T2 OU T1 OU T0 CS SC LK SO SPI SI GN D Figure 1 Data Sheet Block Diagram SPOC - BTS5572E 5 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Block Diagram 2.1 Terms The following figure shows all terms used in this data sheet. VBB IBB VBB IIN 0 IIN 1 VIN 0 IN0 IN1 IIN 2 VIN 1 IN2 I L0 IIN 3 V IN 2 IN3 V OU T0 IIN 4 VIN 3 I L1 IN4 ID D ISO I SI VSO VD S1 OUT1 V IN 4 V DD V D S0 OUT0 VO U T1 I L2 VDD V D S2 OUT2 VOU T2 SO VD S3 I L3 OUT3 SI VO U T3 I CS V SI CS I L4 ISC L K VC S OUT4 SCLK V SC LK VD S 4 V O U T4 I IS IS VIS ILH I LHI VL H I GND IG N D Term s_5.em f Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 ... VDS4). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the values in bold letters (e.g. 0) are default values. Data Sheet 6 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Pin Configuration 3 Pin Configuration 3.1 Pin Assignment SPOC - BTS5572E WRSYLHZ *1' 9'' 62 6, 6&/. &6 ,1 ,1 ,1 ,1 ,1 Figure 3 Data Sheet 9%% QF /+, ,6 QF QF* QF* QF* H[SRVHGSDG ERWWRP 9%% QF 287 287 287 287 287 287 287 287 287 287 287 287 287 QF QF 9%% Pin Configuration PG-DSO-36-36 7 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol I/O Function 19, 36, 37 1) VBB - Positive power supply for high-side power switch 2 VDD - Logic supply (5 V) 1 GND - Ground connection Power Supply Pins Parallel Input Pins (integrated pull-down, leave unused input pins unconnected) 7 IN0 I Input signal of channel 0 8 IN1 I Input signal of channel 1 9 IN2 I Input signal of channel 2 10 IN3 I Input signal of channel 3 11 IN4 I Input signal of channel 4 32, 33, 34 2) OUT0 O Protected high-side power output of channel 0 29, 30, 31 2) OUT1 O Protected high-side power output of channel 1 22, 23, 24 2) Power Output Pins OUT2 O Protected high-side power output of channel 2 2) OUT3 O Protected high-side power output of channel 3 25,26 2) OUT4 O Protected high-side power output of channel 4 6 CS I Chip select of SPI interface (low active), Integrated pull up 5 SCLK I Serial clock of SPI interface 4 SI I Serial input of SPI interface 3 SO O Serial output of SPI interface 14 IS O Diagnosis output signal 27,28 SPI & Diagnosis Pins Limp Home Pin (integrated pull-down, leave unused limp home pin unconnected) 13 LHI I Limp home activation signal; Active high 12, 15, 20, 21, 35 n.c. - not connected, internally not bonded 16, 17, 18 n.c.* - not connected, internally not bonded, shorted together Not connected Pin 1) The exposed pad (pin 37) has to be connected to the power supply with a low impedance connection. The exposed pad must be connected with a low thermal resistance. 2) All outputs pins of each channel have to be connected. Data Sheet 8 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 C to +150 C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions min. max. VBB VDD -Vbat(rev) -0.3 28 V - -0.3 5.5 V - - 16 V Tj(Start) = 25 C t 2 min. 2) RECU = 20m RCable= 16m/m LCable= 1H/m l = 0 or 5m 3) Supply Voltage 4.1.1 Power supply voltage 4.1.2 Logic supply voltage 4.1.3 Reverse polarity voltage according Figure 21 4.1.4 Supply voltage for full short circuit protection (single pulse) (Tj(0) = -40 C ... 150 C) VBB(SC) 0 20 V 4.1.5 Voltage at power transistor - 40 V 4.1.6 Supply voltage for load dump protection VDS VBB(LD) - 40 4.1.7 Current through ground pin -100 25 4.1.8 Current through VDD pin IGND IDD -25 12 RI = 2 4) t = 400ms mA t 2 min. mA t 2 min. IL -IL(LIM) IL(LIM) A IIS -10 10 mA t 2 min. VIN IIN -0.3 8.0 V -0.75 -2.0 0.75 2.0 mA - VCS ICS -0.3 5.7 V -0.75 -2.0 0.75 2.0 mA - VSI ISI -0.3 5.7 V -0.75 -2.0 0.75 2.0 mA - VSCLK ISCLK -0.3 5.7 V -0.75 -2.0 0.75 2.0 mA - ISO -0.75 -2.0 0.75 2.0 mA - VLHI -0.3 8.0 V - V Power Stages 4.1.9 Load current 5) Diagnosis Pin 4.1.10 Current through sense pin IS Input Pins 4.1.11 Voltage at input pins 4.1.12 Current through input pins - t 2 min. SPI Pins 4.1.13 Voltage at chip select pin 4.1.14 Current through chip select pin 4.1.15 Voltage at serial input pin 4.1.16 Current through serial input pin 4.1.17 Voltage at serial clock pin 4.1.18 Current through serial clock pin 4.1.19 Current through serial output pin SO - t 2 min. - t 2 min. - t 2 min. t 2 min. Limp Home Pin 4.1.20 Voltage at limp home input pin Data Sheet 9 - Rev. 1.0, 2008-05-15 SPOC - BTS5572E Electrical Characteristics Absolute Maximum Ratings (cont'd)1) Tj = -40 C to +150 C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol 4.1.21 Current through limp home input pin Limit Values Unit Conditions min. max. ILHI -0.75 -2.0 0.75 2.0 mA - Tj Tj Tstg -40 150 C - - 60 K - -55 150 C - kV HBM 6) - - t 2 min. Temperatures 4.1.22 Junction temperature 4.1.23 Dynamic temperature increase while switching 4.1.24 Storage temperature ESD Susceptibility VESD 4.1.25 ESD resistivity OUT pins vs. VBB other pins incl. OUT vs. GND -4 -2 4 2 1) Not subject to production test, specified by design. 2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection feature. Operation in current limitation is considered as "outside" normal operating range. Protection features are not designed for continuous repetitive operation. 6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5k, 100pF). Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Pos. 4.2.1 4.2.2 Thermal Resistance Parameter Junction to Case Symbol 1) Junction to Ambient 1) RthJC RthJA Limit Values Unit Conditions Min. Typ. Max. - - 2 K/W - - 22 - K/W 2) 1) Not subject to production test, specified by design. 2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. Data Sheet 10 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Supply 5 Power Supply The SPOC - BTS5572E is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended as shown in Figure 21. There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB. The first SPI transmission after a reset contains at pin SO the read information from register OUT, the transmission error bit TER is set. 5.1 Power Supply Modes The following table shows all possible power supply modes for VBB, VDD and the pin LHI. Power Supply Modes Off Off SPI on Reset Off Limp Home mode without SPI Normal operation Limp Home mode with SPI 1) VBB VDD 0V 0V 0V 0V 13.5 V 13.5 V 13.5 V 13.5 V 0V 0V 5V 5V 0V 0V 5V 5V LHI 0V 5V 0V 5V 0V 5V 0V 5V PROFET operating - - - - - Limp home - - - - - - SPI (logic) - - reset reset reset Stand-by current - - - - - - 3) - Idle current - - - - - - Diagnosis - - - - - - 1) 2) 3) 4) reset 2) 4) SPI read only. When DCR.MUX = 111b . When all channels are in OFF-state and DCR.MUX!= 111b. Current sense disabled in limp home mode. Stand-by mode is entered as soon as the current sense multiplexer (DCR.MUX) is in default (stand-by) position 1). Additionally, all thermal latches are cleared automatically. As soon as stand-by mode is entered, register HWCR.STB is set. To wake-up the device, the current sense multiplexer (DCR.MUX) is programmed different to default (stand-by) position. Idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and VDD supply is available. Limp home (LHI = high) will wake-up the device and is working without VDD supply. As a result, all channels can be activated via the dedicated input pins. 1) Not affected by the inputs state Data Sheet 11 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Supply 5.2 Reset There are several reset triggers implemented in the device. They reset the SPI registers and errors flags to their default values. The power stages are not affected by the reset signals. The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT, the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(min). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode In Limp Home mode, the SPI write-registers are reset. Output OUTx will follow the input INx configuration only. For application example see Figure 21. The SPI interface is operating normally, so the limp home register bit LHI as well as the error flags can be read, but any write command will be ignored. To activate the Limp Home mode, LHI input pin voltage must be higher than VLHI(H). Data Sheet 12 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Supply 5.3 Electrical Characteristics Electrical Characteristics Power Supply Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8 V to 5.5 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 C Pos. Parameter Symbol VBB 5.3.2 Stand-by current for whole device with loads IBB(STB) 5.3.1 Operating voltage power switch Limit Values min. typ. max. 5.5 - 281) - - - 0.5 - - 3 3 58 - 3 8 Unit Test Conditions V - A VDD = 0 V VLHI = 0 V Tj = 25 C Tj 85 C 1) Tj = 150 C VDD = 5 V 2) 5.3.3 Idle current for whole device with loads, all channels off. IBB(idle) 5.3.4 Logic supply voltage 3.8 - 5.5 V - 5.3.5 Logic supply current VDD IDD - 55 120 A 5.3.6 Logic idle current IDD(idle) - 20 50 A VCS = 0 V fSCLK = 0 Hz VCS = VDD fSCLK = 0 Hz mA DCR.MUX = 110B Chip in Standby 5.3.7 Operating current for whole device IGND - 12 25 mA fSCLK = 0 Hz VLHI(L) VLHI(H) ILHI(L) ILHI(H) -0.3 - 1.0 V - 2.6 - 5.5 V - 3 - 85 A 7 30 85 A VLHI = 0.4 V VLHI = 5 V 500 s LHI Input Characteristics 5.3.8 L-input level at pin LHI 5.3.9 H-input level at pin LHI 5.3.10 L-input current through pin LHI 5.3.11 H-input current through pin LHI Reset 5.3.12 Power-On wake up time tWU(PO) 1) 1) Not subject to production test, specified by design. 2) In case of OUT.5 = 1b increased current consumption. Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VBB = 13.5 V, VDD = 4.3 V and Tj = 25 C. Data Sheet 13 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Supply 5.4 Command Description HWCR Hardware Configuration Register 1) W/R1) RB1) ADDR1) read 1 1 write 1 1 3 2 1 0 0 0 x STB CTL 0 0 0 RST CTL W/R Write/Read, RB Register Bank, ADDR Address Field Bits Type Description RST 1 w Reset Command 0 Normal operation 1 Execute reset command STB 1 r Stand-by 0 Device is awake 1 Device is in stand-by mode Data Sheet 14 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages 6 Power Stages The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register OUT. Channels 0, 1 and 2 provides a load type configuration for bulbs or LEDs in register PLCR. The load type configuration is allowed to be changed in OFF-state only. 6.1 Output ON-State Resistance The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 11. V BB = 13.5 V T j = 25 C 400 350 350 Channel 0, 1, 2 (bulb) Channel 0, 1, 2 (LED) Channel 3, 4 250 Channel 0, 1, 2 (bulb) Channel 0, 1, 2 (LED) Channel 3, 4 300 R DS(ON) [m] R DS(ON) [m] 300 200 150 100 250 200 150 100 50 50 0 0 -50 0 50 T j [C] 100 Figure 4 Typical On-State Resistance 6.2 Input Circuit 0 150 5 10 15 V BB [V] 20 25 30 There are two ways of using the input pins in combination with the OUT register by programming the HWCR.PWM parameter. * * PLCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin. PLCR.PWM = 1: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register OUT. Figure 5 shows the complete input switch matrix. Data Sheet 15 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages OUT4 OUT3 OUT2 OUT1 OUT0 OR IN0 I IN 0 & OR IN1 I IN 1 Gate Driver 1 & OR IN2 I IN 2 Gate Driver 2 & OR IN3 I IN 3 Gate Driver 3 & OR IN4 I IN 4 Gate Driver 0 Gate Driver 4 & PWM InputM atrix_5.em f Figure 5 Input Switch Matrix The current sink to ground ensures that the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses. 6.3 Power Stage Output The power stages are built to be used in high side configuration (Figure 6). VBB VDS V BB OUT GND VOUT Output.emf Figure 6 Data Sheet Power Stage Output 16 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission. IN / OUTx VOUT tON t OFF tdelay(ON) tdelay(OFF) t 90% 70% 30% 70% dV / dtON dV / dtOFF 30% 10% t Figure 7 SwitchOn.emf Switching a Load (resistive) When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent avalanche of the device, there is a voltage clamp mechanism implemented which limits that negative output voltage to a certain level (VDS(CL)). See Figure 6 for details. The maximum allowed load inductance is limited. Data Sheet 17 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages 6.4 Electrical Characteristics Electrical Characteristics Power Stages Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Output Characteristics 6.4.1 On-State resistance m RDS(ON) channel 0, 1, 2 channel 3, 4 - - 50 85 - 100 - - 170 300 - 375 - - 110 200 - 260 6.4.2 Output voltage drop limitation at small load VDS(NL) currents PLCR.LEDn = 0 1) Tj = 25 C / IL = 2.6 A Tj = 150 C / IL = 2.6 A PLCR.LEDn = 1 1) Tj = 25 C / IL = 0.6 A Tj = 150 C / IL = 0.6 A 1) Tj = 25 C / IL = 1.3 A Tj = 150 C / IL = 1.3 A mV channel 0, 1, 2 channel 3, 4 6.4.3 Output clamp VDS(CL) 6.4.4 Output leakage current per channel IL(OFF) - 25 - - 25 - 40 47 54 PLCR.LEDn = 0 IL = 35 mA V A IL = 35 mA IL = 20 mA 2) VIN = 0 V or floating OUT.OUTn = 0 channel 0, 1, 2 - - 0.1 - 10 40 stand-by idle channel 3, 4 - - 0.1 - 8 40 stand-by idle 6.4.5 Inverse current capability per channel -IL(IC) A 3) channel 0, 1, 2 - 2.5 - - channel 3, 4 - 1.0 - - -0.3 - 1.0 V - 2.6 - 5.5 V - 3 25 75 A 10 40 75 A VIN = 0.4 V VIN = 5 V Input Characteristics 6.4.6 L-input level 6.4.7 H-input level 6.4.8 L-input current 6.4.9 H-input current Data Sheet VIN(L) VIN(H) IIN(L) IIN(H) 18 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages Electrical Characteristics Power Stages (cont'd) Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Timings s 6.4.10 Turn-ON delay to tdelay(ON) 10% VBB (Logical propagation delay from input INx to output OUTx) channel 0, 1, 2 channel 3, 4 - 35 - - 20 - PLCR.LEDn = 0 RL = 6.8 s 6.4.11 Turn-OFF delay to tdelay(OFF) 90% VBB (Logical propagation delay from input INx to output OUTx) channel 0, 1, 2 channel 3, 4 - 50 - - 30 - channel 0, 1, 2 channel 3, 4 - - 250 - - 100 - - 150 channel 0, 1, 2 channel 3, 4 Data Sheet 19 PLCR.LEDn = 0 RL = 6.8 PLCR.LEDn = 1 RL = 33 - 290 - - 100 - - 150 0.1 0.2 0.5 0.1 0.75 1.9 PLCR.LEDn = 0 RL = 6.8 PLCR.LEDn = 1 RL = 33 0.1 0.45 0.9 RL = 18 channel 0, 1, 2 channel 3, 4 RL = 18 VBB = 13.5 V - dV/ dtON 6.4.14 Turn-ON slew rate 30% to 70% VBB RL = 18 VBB = 13.5 V PLCR.LEDn = 0 RL = 6.8 PLCR.LEDn = 1 RL = 33 s tOFF 6.4.13 Turn-OFF time to 10% VBB RL = 18 VBB = 13.5 V 1) PLCR.LEDn = 0 RL = 6.8 s tON 6.4.12 Turn-ON time to 90% VBB VBB = 13.5 V 1) RL = 18 V/s VBB = 13.5 V Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages Electrical Characteristics Power Stages (cont'd) Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol 6.4.15 Turn-OFF slew rate 70% to 30% VBB -dV/ dtOFF Limit Values Unit Test Conditions min. typ. max. V/s VBB = 13.5 V channel 0, 1, 2 channel 3, 4 0.1 0.2 0.1 0.75 1.9 PLCR.LEDn = 0 RL = 6.8 PLCR.LEDn = 1 RL = 33 0.1 0.5 RL = 18 0.5 0.9 1) Not subject to production test, specified by design. 2) The voltage increase until the current is reached. 3) Not subject to production test, specified by design. In case of inverse current (VOUT > VBB), the error flag ERR in the standard diagnosis of the affected channel is cleared. The inverse current capability in ON-state and OFF-state is defined for Tj < Tj(SC) and channel remains in same state (ON-state or OFF-state). Other channels can be affected (e.g. OUT latch due to junction temperature increase). Data Sheet 20 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Power Stages 6.5 Command Description OUT Output Configuration Registers W/R RB 5 4 3 2 1 0 read 0 x OUT4 OUT3 OUT2 OUT1 OUT0 write 0 0 OUT4 OUT3 OUT2 OUT1 OUT0 Field Bits Type Description OUTn n = 4 to 0 n rw Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on Note: In case of OUT.5 = 1b the device current consumption is increased. PLCR PWM and LED-Mode Configuration Register W/R RB read/write 1 0 1 Field Bits Type Description PWM 3 rw PWM Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit LEDn n = 2 to 0 n rw Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode Data Sheet ADDR 21 3 2 1 0 PWM LED2 LED1 LED0 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions 7 Protection Functions The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as "outside" normal operating range. Protective functions are neither designed for continuous nor for repetitive operation. 7.1 Over Load Protection The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS. Please note that the voltage at the OUT pin is VBB - VDS. Please refer to following figures for details. IL 25 WDLR.LED = 0 20 15 10 WDLR.LED = 1 5 5 10 15 20 25 VDS CurrentLimitation012.emf Figure 8 Current Limitation Channels 0, 1, 2 (minimum values) IL 8 6 4 2 5 10 15 20 25 V DS CurrentLimitation34 .emf Figure 9 Current Limitation Channels 3, 4 (minimum values) Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to rapid temperature rise inside. Data Sheet 22 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions 7.2 Over Temperature Protection Each channel has its own temperature sensor. If the temperature at the channel exceeds the thermal shutdown temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). In order to reactivate the channel, the temperature at the output must drop by at least the thermal hysteresis Tj and the over temperature latch must be cleared by SPI command HWCR.CTL = 1. All over temperature latches are cleared by SPI command HWCR.CTL = 1. IN / OUTx IL t I L(LIM) t IIS t ERR CTL = 1 t OverLoad.emf Figure 10 Shut Down by Over Temperature Additionally, all channels have their own dynamic temperature sensors. The dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. The dynamic temperature sensor turns off the channel if its sudden temperature increase exceeds the dynamic temperature sensor threshold Tj(SW). Please refer to the following figure for details. Data Sheet 23 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions IN / OUTx t IL IL(LIM) t Tj Tj(SC) T jSW TjSW TjSW t IIS t ERR CTL = 1 t deltaT.emf Figure 11 Dynamic Temperature Sensor Operations The ERR-flag will be set during dynamic temperature sensor shut down. It can be reset by reading the ERR-flag. If the channel is still in dynamic temperature sensor shut down, the ERR-flag will be set again. 7.3 Reverse Polarity Protection In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads. The current through the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the limp home input pin has to be limited as well (please refer to the maximum ratings listed on Page 9). Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity. Data Sheet 24 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions 7.4 Over Voltage Protection In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection. The current through the ground connection has to be limited during over voltage. Please note that in case of over voltage the pin GND might have a high voltage offset to the module ground. 7.5 Loss of Ground In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5572E securely changes to or stays in off-state. 7.6 Loss of VBB In case of loss of VBB connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for reverse polarity reason, the ground connection is not available for demagnetization. Then for example, a resistor can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND. Data Sheet 25 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions 7.7 Electrical Characteristics Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. 24 - 40 PLCR.LEDn = 0 1) 6 - 12 PLCR.LEDn = 1 1) 8 - 18 1) 150 170 190 C 2) - 7 - K 2) - 60 - K 2) 40 47 54 V IBB = 4 mA Over Load Protection IL(LIM) 7.7.1 Load current limitation A channel 0, 1, 2 channel 3, 4 VDS = 7 V Over Temperature Protection Tj(SC) 7.7.3 Thermal hysteresis Tj 7.7.4 Dynamic temperature increase limitation Tjsw 7.7.2 Thermal shut down temperature while switching Over Voltage 7.7.5 Overvoltage protection VBB(AZ) 1) For Tj = 150 C, not subject to production test. Device will shutdown due to the maximum junction temperature sensor. 2) Not subject to production test, specified by design. Data Sheet 26 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Protection Functions 7.8 Command Description HWCR Hardware Configuration Register W/R RB write 1 ADDR 1 0 3 2 1 0 0 0 RST CTL Field Bits Type Description CTL 0 rw Clear Thermal Latch 0 Thermal latches are untouched 1 Command: Clear all thermal latches Data Sheet 27 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis 8 Diagnosis For diagnosis purpose, the SPOC - BTS5572E provides a current sense signal at pin IS and the diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 12 for details. VBB IIS 0 latch tem perature sensor T gate control OR OUT4 OUT3 OUT2 OUT1 OUT0 load current lim itation latch load current sense ERR0 channel 0 V BB DCR.MUX VD S( SB ) DCR. SBM current sense m ultiplexer IS R IS Diagnosis_5.em f Figure 12 Data Sheet Block diagram: Diagnosis 28 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis For diagnosis feedback at different operation modes, please see Table 1. Table 1 Operation Modes 1) Operation Mode Input Level Output OUT.OUTn Level VOUT Current Sense IIS Error Flag ERRn2) DCR. SBM Normal Operation (OFF) L/0 (OFF-state) GND Z 0 1 GND Z 0 Short Circuit to GND 1 3) Thermal shut down Z Z 0 Short Circuit to VBB VBB Z 0 0 Open Load Z Z 0 x ~VBB IL / kILIS 0 0 Normal Operation (ON) H/1 (ON-state) x < VBB Z 1 x Short Circuit to GND ~GND Z 1 1 Dynamic Temperature Sensor shut down Z Z 1 Current Limitation x 3) Thermal shut down Z Z 1 Short Circuit to VBB VBB VBB < IL / kILIS 0 0 Z 0 0 Open Load x 1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit. x = undefined. 2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI. 3) The over temperature flag is set latched (in OFF states also) and can be cleared by SPI command HWCR.CTL. 8.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. The latches are cleared by SPI command HWCR.CTL. Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CTL), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. Data Sheet 29 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. Current Sense Signal The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs.The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register PLCR for channels 0 to 2. Usually a resistor RIS is connected to the current sense pin. It is recommended to use resistors 2.5 k < RIS < 7 k. A typical value is 3.3 k. 5000 kilis bulb max kilis bulb typ Normalized kilis value 4500 4000 kilis bulb min kilis led max kilis led typ 3500 kilis led min 3000 2500 2000 1500 1000 500 0 0 Figure 13 Data Sheet 1 2 3 Load current / Proportion of ILnom 4 5 Current Sense Ratio kILIS Channel 0, 1, 2 Bulb and LED mode 1) 30 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis 4000 kilis bulb max kilis bulb typ kilis bulb min 3500 Normalized kilis value 3000 2500 2000 1500 1000 500 0 0 0,5 1 1,5 Load current / Proportion of ILnom 2 2,5 Current Sense Ratio kILIS Channel 3, 41) Figure 14 In case of over current as well as over temperature, the current sense signal of the affected channel is switched off. To distinguish between over temperature and over load, the SPI diagnosis word can be used. Whereas the over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated SPI command (HWCR.CTL). Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 15. IN V OUT OFF ON OFF tON tOFF t t IL IIS ts IS (ON) t s IS (LC) t dIS (OFF) t t SenseTiming.emf Figure 15 Timing of Current Sense Signal 1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 8.4 (Position 8.4.1). Data Sheet 31 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis Current Sense Multiplexer There is a current sense multiplexer implemented in the SPOC - BTS5572E that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 16. CS DCR.MUX 110 000 001 110 ts IS (MUX ) IIS t dIS (MUX ) t tsIS (E N) t MuxTiming.emf Figure 16 Timing of Current Sense Multiplexer 8.3 Switch Bypass Diagnosis To detect short circuit to VBB, there is a switch bypass monitor implemented. In case of short circuit between the output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS. The switch bypass monitor compares the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI register DCR.SBM. Data Sheet 32 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis 8.4 Electrical Characteristics Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. typ. Unit Test Conditions max. Load Current Sense 8.4.1 Current sense ratio kILIS channel 0, 1, 2 (bulb): PLCR.LEDn = 0 2450 2450 2700 2700 0.600 A 1.3 A 2.6 A 4.0 A 3100 3100 3100 3100 3900 3700 3500 3500 channel 0, 1, 2 (LED): - - - - PLCR.LEDn = 1 0.020 A 0.050 A 0.300 A 0.600 A 1.0 A 500 590 680 730 750 950 910 830 830 830 1400 1250 990 930 910 - - - - - 800 1000 1200 1250 1250 1350 1370 1800 1800 1700 1600 1550 1550 1550 2750 2400 2200 1950 1850 1750 1730 - - - - - - - 1.1VDD V IIS = 1 mA channel 3, 4: 0.020 A 0.050 A 0.150 A 0.300 A 0.600 A 1.3 A 2.0 A 8.4.2 Current sense voltage limitation Data Sheet VIS(LIM) 33 0.9VDD VDD Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C typical values: VBB = 13.5 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 8.4.3 Current sense leakage / offset current IIS(en) - - 1 A IL = 0 DCR.MUX = 000B 8.4.4 Current sense leakage, while diagnosis disabled IIS(dis) - - 1 A DCR.MUX = 110B s VBB = 13.5 V RIS = 3.3 k 8.4.5 Current sense settling time after channel tsIS(ON) activation channel 0, 1, 2 channel 3, 4 8.4.6 Current sense desettling time after channel deactivation PLCR.LEDn = 0 - - 300 RL = 6.8 - - 115 PLCR.LEDn = 1 RL = 33 - - 180 s tdIS(OFF) - - 25 PLCR.LEDn = 0 - - 25 PLCR.LEDn = 1 s 8.4.7 Current sense settling time after change tsIS(LC) of load current channel 0, 1, 2 channel 3, 4 RL = 18 VBB = 13.5 V 1) RIS = 3.3 k VBB = 13.5 V 1) RIS = 3.3 k PLCR.LEDn = 0 - - 30 - - 30 - - 25 8.4.8 Current sense settling time after current sense activation tsIS(EN) 8.4.9 Current sense settling time after multiplexer channel change tsIS(MUX) 8.4.10 Current sense deactivation time tdIS(MUX) - VDS(SB) 0.7 IL = 2.6 A to 1.3 A IL = 1.3 A to 0.6 A s RIS = 3.3 k DCR.MUX: 110B -> 000B - - 30 s RIS = 3.3 k DCR.MUX: 000B -> 001B - 25 s RIS = 3.3 k DCR.MUX: 1) 001B -> 110B Switch Bypass Monitor 8.4.11 Switch bypass monitor threshold - 2.5 V - 1) Not subject to production test, specified by design. Data Sheet 34 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis 8.5 Command Description DCR Diagnosis Control Register W/R RB read 1 1 1 SBM MUX write 1 1 1 0 MUX Input Level OUT.OUTn Field Bits Type Description MUX 2:0 rw Set Current Sense Multiplexer Configuration 000 IS pin is high impedance 001 IS pin is high impedance 010 IS pin is high impedance 011 IS pin is high impedance 100 IS pin is high impedance 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) SBM 3 r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) MUX 2:0 rw Set Current Sense Multiplexer Configuration 000 current sense of channel 0 is routed to IS pin 001 current sense of channel 1 is routed to IS pin 010 current sense of channel 2 is routed to IS pin 011 current sense of channel 3 is routed to IS pin 100 current sense of channel 4 is routed to IS pin 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) SBM 3 r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) L/0 (OFF-state) H/1 (ON-state) ADDR 3 2 1 0 1) Invalid in stand-by mode Data Sheet 35 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Diagnosis Standard Diagnosis CS 7 6 5 4 3 2 1 0 TER 0 LHI x ERR4 ERR3 ERR2 ERR1 ERR0 Field Bits Type Description ERRn n = 4 to 0 n r Error flag Channel n 0 normal operation 1 failure mode occurred Data Sheet 36 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB CS SCLK time SPI.emf Figure 17 Serial Peripheral Interface 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS5572E by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: * * The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. CS Low to High transition: * * Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, ...) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for further information. Data Sheet 37 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5 for further information. 9.2 Daisy Chain Capability The SPI of SPOC - BTS5572E provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 18), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. SO SPI SI SO SPI SCLK SI device 3 SCLK SCLK CS MI MCS MCLK Figure 18 SO SPI CS SI MO device 2 CS device 1 SPI_DaisyChain .emf Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 19). MI SO device 3 SO device 2 SO device 1 MO SI device 3 SI device 2 SI device 1 MCS MCLK time SPI_DasyChain2.emf Figure 19 Data Sheet Data Transfer in Daisy Chain Configuration 38 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) 9.3 Timing Diagrams tCS(lead) tCS(lag) tCS(td) tSCLK(P) CS 0.7VDD 0.2VDD tSCLK(H) tSCLK(L) 0.7VDD SCLK tSI(su) 0.2VDD tSI(h) 0.7VDD SI 0.2VDD tSO(en) tSO(v) tSO(dis) 0.7VDD SO 0.2VDD SPI Timing.emf Figure 20 Timing Diagram SPI Access 9.4 Electrical Characteristics Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C, VDD = 3.8 V to 5.5 V typical values: VBB = 13.5 V, Tj = 25 C, VDD = 4.3 V Pos. Parameter Symbol Limit Values min. typ. max. CS VCS(L) SCLK VSCLK(L) SI VSI(L) -0.3 -0.3 -0.3 - - - 1.0 1.0 1.0 CS VCS(H) SCLK VSCLK(H) SI VSI(H) 2.6 2.6 2.6 - - - 5.5 5.5 5.5 10 30 85 Unit Test Conditions Input Characteristics (CS, SCLK, SI) V 9.4.1 L level of pin 9.4.2 H level of pin V -ICS(L) 9.4.3 L-input pull-up current at CS pin VDD = 4.3 V - - - VDD = 4.3 V - - - A VDD = 4.3 V VCS = 0 V 9.4.4 H-input pull-up current at CS pin -ICS(H) 3 - 85 A VDD = 4.3 V VCS = 2.6 V A 9.4.5 L-input pull-down current at pin SCLK ISCLK(L) SI ISI(L) 3 3 - - 75 75 SCLK ISCLK(H) SI ISI(H) 10 10 30 30 75 75 0 - 0.5 VSCLK = 0.4 V VSI = 0.4 V A 9.4.6 H-input pull-down current at pin VDD = 4.3 V VDD = 4.3 V VSCLK = 4.3 V VSI = 4.3 V Output Characteristics (SO) 9.4.7 L level output voltage Data Sheet VSO(L) 39 V ISO = -0.5 mA Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 C to +150 C, VDD = 3.8 V to 5.5 V typical values: VBB = 13.5 V, Tj = 25 C, VDD = 4.3 V Pos. Parameter Symbol Limit Values min. typ. Unit Test Conditions max. 9.4.8 H level output voltage VSO(H) VDD - - 0.5 V VDD V ISO = 0.5 mA VDD = 4.3 V 9.4.9 Output tristate leakage current ISO(OFF) -10 - 10 A VCS =VDD fSCLK tSCLK(P) tSCLK(H) tSCLK(L) tCS(lead) 0 - 2 MHz - 500 - - ns - 250 - - ns - 250 - - ns - 1 - - s - 1 - - s - Timings 9.4.10 Serial clock frequency 9.4.11 Serial clock period 9.4.12 Serial clock high time 9.4.13 Serial clock low time 9.4.14 Enable lead time (falling CS to rising SCLK) 9.4.15 Enable lag time (falling SCLK to rising tCS(lag) CS) 9.4.16 Transfer delay time (rising CS to falling CS) tCS(td) 1 - - s - 9.4.17 Data setup time (required time SI to falling SCLK) tSI(su) 100 - - ns - 9.4.18 Data hold time (falling SCLK to SI) tSI(h) tSO(en) 100 - - ns - - - 1 s CL = 20 pF 1) tSO(dis) - - 1 s CL = 20 pF 1) - - 250 ns CL = 20 pF 1) 9.4.19 Output enable time (falling CS to SO valid) 9.4.20 Output disable time (rising CS to SO tri-state) 9.4.21 Output data valid time with capacitive tSO(v) load 1) Not subject to production test, specified by design. Data Sheet 40 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) 9.5 SPI Protocol CS1) 7 6 5 4 3 2 1 0 0 OUT4 OUT3 OUT2 OUT1 OUT0 x x x x x 0 Write OUT Register SI 1 0 Read OUT Register SI 0 0 Write Configuration Register SI 1 1 DATA ADDR Read Configuration Register SI 0 1 ADDR x x x 0 Read Standard Diagnosis SI 0 x x x x x x 1 x ERR4 ERR3 ERR2 ERR1 ERR0 OUT4 OUT3 OUT2 OUT1 OUT0 Standard Diagnosis SO TER 0 LHI Second Frame of Read Command SO TER 1 0 SO TER 1 1 0 ADDR DATA 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. Field Bits Type Description RB 6 rw Register Bank 0 Read / write to the OUTx channel 1 Read / write to the other register TER CS r Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset OUTx x = 4 to 0 x rw Output Control Register of Channel x 0 OFF 1 ON ADDR 5:4 rw Address Pointer to register for read and write command DATA 3:0 rw Data Data written to or read from register selected by address ADDR LHI 6 r Limp Home Enable 0 L-input signal at pin LHI 1 H-input signal at pin LHI ERRx x = 4 to 0 x r Diagnosis of Channel x 0 No failure 1 Over temperature, over load or short circuit Data Sheet 41 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Serial Peripheral Interface (SPI) 9.6 Register Overview Name W/R RB 5 4 3 2 1 0 default1) OUT W/R 0 0 OUT4 OUT3 OUT2 OUT1 OUT0 00H Name W/R RB 3 2 1 0 default1) PLCR W/R 1 0 1 PWM LED2 LED1 LED0 00H HWCR R 1 1 0 0 x STB CTL 02H W 1 1 0 0 0 RST CTL - R 1 1 1 SBM MUX 07H W 1 1 1 0 MUX - DCR ADDR 1) The default values are set after reset. Data Sheet 42 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Application Description 10 Application Description Vbat 5V * 500 68nF 100nF VDD VBB Limp_Home VCC GPIO 8k IN0 GPIO 8k IN1 IN2 OUT0 IN3 OUT1 IN4 OUT2 27 W 27 W 27 W OUT3 C e.g. XC2267 10 W OUT4 IS 10 W 1k AD GND 3.3k 1nF VDD SPI SPI 3.9k CS 3.9k SCLK 3.9k SO 3.9k SI LHI 8k Limp_Home VSS GND 10nF.. 100nF * For filtering and protection purposes Figure 21 Data Sheet Circuit_5.emf Application Circuit Example 43 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Package Outlines SPOC - BTS5572E 2.55 MAX. Package Outlines SPOC - BTS5572E 7.6 -0.2 1) 0.7 0.2 0.65 0.1 C 0.33 0.08 2) 0.17 M D A-B C D 36x Bottom View A 19 19 36 Ey 36 10.3 0.3 8 MAX. 0.35 x 45 0.23 +0.09 0 ... 0.1 2.45 -0.2 11 Exposed Diepad 1 18 18 B Ex 1 12.8 -0.2 1) Index Marking (spherical shape) Index Marking (spherical shape) Ejector Mark (flat shape) Exposed Diepad Dimensions Package Leadframe Ex Ey PG-DSO-36-36 C66065-A6940-C016 6.8 4.2 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side PG-DSO-36-36-PO V01 Figure 22 PG-DSO-36-36 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 44 Rev. 1.0, 2008-05-15 SPOC - BTS5572E Revision History 12 Revision History Revision Date Changes 1.0 2008-05-15 Initial revision Data Sheet 45 Rev. 1.0, 2008-05-15 Edition 2008-05-15 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.