ispLSI® 2096/A
In-System Programmable High Density PLD
2096_09 1
USE ispLSI 2096E FOR NEW DESIGNS
Lead-
Free
Package
Options
Available!
Features
• ENHANCEMENTS
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
— ispLSI 2096A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 125 MHz Maximum Operating Frequency
—tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Functional Block Diagram
Global Routing Pool
(GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096
C7 C4
C5
C6
A4 A7
A6
A5
GLB
Logic
Array
DQ
DQ
DQ
DQ
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3 C0
C1
C2
B0 B3
B2
B1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
B7
B6
B4
B5
A0
A1
A3
A2
Description
The ispLSI 2096 and 2096A are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure 1). There are a total of 24 GLBs in the ispLSI 2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2006
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
2
USE ispLSI 2096E FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 2096/A Functional Block Diagram
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096 and 2096A device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096 and 2096A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
A0
A3
A1
A2
B7
B4
B6
B5
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
I/O 95
I/O 94
I/O 93
I/O 92
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
IN 2
SCLK/IN 3
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
Y0
Y1
Y2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
SDI/IN 0
MODE/IN 1
SDO
RESET
ispEN
GOE 1
GOE 0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
Input Bus
0917
Megablock
C7 C6 C5 C4
A4 A5 A6 A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B0 B1 B2 B3
Output Routing Pool (ORP)
C3 C2 C1 C0
Output Routing Pool (ORP)
Input Bus
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 5
IN 4
Generic Logic
Blocks (GLBs)
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
3
USE ispLSI 2096E FOR NEW DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Capacitance (TA=25°C, f=1.0 MHz)
Data Retention Specifications
TA = 0°C to + 70°C
TA = -40°C to + 85°C
SYMBOL
Table 2 - 0005/2096
V
cc
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
Vcc+1
0.8
V
V
V
V
Commercial
Industrial
Table 2-0008A-isp
PARAMETER
Data Retention
MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles
20
10000
–
–
Years
Cycles
SYMBOL
Table 2-0006a
C
PARAMETER
Clock Capacitance 15
UNITSTYPICAL TEST CONDITIONS
2
C
1
I/O and Dedicated Input Capacitance
pf V = 5.0V, V = 2.0V
CC Y
8 pf V = 5.0V, V = 2.0V
CC I/O, IN
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
4
USE ispLSI 2096E FOR NEW DESIGNS
Switching Test Conditions
Output Load Conditions (see Figure 2)
Figure 2. Test Load
Input Pulse Levels
Table 2-0003/2096
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
≤ 3 ns
≤ 2 ns
Others
-125
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C
470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2096
DC Electrical Characteristics
Over Recommended Operating Conditions
+ 5V
R1
R2CL*
Device
Output
Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213/2096
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V = 5V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007/2096
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V ≤ V ≤ V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
V = 5V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
150
150
0.4
–
10
-10
-150
-150
-200
295
–
V
V
μA
μA
μA
μA
mA
mA
mA
CC A
OUT
CC
CC
Commercial
Industrial
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
5
USE ispLSI 2096E FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-100
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030/2096
1
4
3
1
tsu2 + tco1
( )
-80
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns
t
pd2 A 2 Data Propagation Delay – – ns
f
max A 3 Clock Frequency with Internal Feedback 100 – 81.0 – MHz
f
max (Ext.) – 4 Clock Frequency with External Feedback – – MHz
f
max (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz
t
su1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
t
co1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – ns
t
h1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
t
su2 – 9 GLB Reg. Setup Time before Clock 8.0 – ns
t
co2 – 10 GLB Reg. Clock to Output Delay – – ns
t
h2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns
t
r1 A 12 Ext. Reset Pin to Output Delay – – ns
t
rw1 – 13 Ext. Reset Pulse Duration 6.5 – ns
t
ptoeen B 14 Product Term OE, Enable – – ns
t
ptoedis C 15 Product Term OE, Disable – – ns
t
goeen B 16 Global OE, Enable – – ns
t
goedis C 17 Global OE, Disable – – ns
t
wh – 18 External Synchronous Clock Pulse Duration, High 5.0 – – ns
t
wl – 19 External Synchronous Clock Pulse Duration, Low 5.0 – – ns
77.0
100
6.5
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
13.0
57.0
83.0
9.0
0.0
11.0
0.0
10.0
6.0
6.0
18.5
6.5
8.0
17.0
18.0
18.0
12.0
12.0
-125
MIN.
– 7.5
–
125 –
–
–
–
–
0.0
6.0
–
0.0
–
5.0
–
–
–
–
4.0 –
4.0 –
100
125
5.0
4.0
–
–
4.5
–
10.0
–
12.0
12.0
7.0
7.0
10.0
MAX.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
6
USE ispLSI 2096E FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2096
Inputs
UNITS
-100
MIN.
-80
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay – – 1.8 ns
t
din 21 Dedicated Input Delay – – 4.4 ns
t
grp 22 GRP Delay – – 2.6 ns
GLB
t
1ptxor
24
1 Product Term/XOR Path Delay – – 8.0 ns
t
20ptxor
25
20 Product Term/XOR Path Delay – – 8.8 ns
t
xoradj
26
XOR Adjacent Path Delay – – 9.8 ns
t
gbp
27
GLB Register Bypass Delay – – 1.3 ns
t
gsu
28
GLB Register Setup Time before Clock – 1.4 – ns
t
gh
29
GLB Register Hold Time after Clock – 6.0 – ns
t
gco
30
GLB Register Clock to Output Delay – – 0.4 ns
3
t
gro
31
GLB Register Reset to Output Delay – – 1.6 ns
t
ptre
32
GLB Product Term Reset to Register Delay – – 8.6 ns
t
ptoe
33
GLB Product Term Output Enable to I/O Cell Delay – – 9.0 ns
t
ptck 35 GLB Product Term Clock Delay 5.6 10.2 ns
ORP
0.5
2.2
GRP
1.7
t
4ptbpc 23 4 Product Term Bypass Comb. Path Delay – – 8.1 ns
6.8
7.3
8.0
0.5
5.8
1.2
4.0
0.3
1.3
6.1
8.6
4.1 7.1
t
orp 36 ORP Delay – – 2.0 ns
t
orpbp 37 ORP Bypass Delay – – 0.5 ns
1.4
0.4
-125
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
0.2
1.5
1.3
–
5.7
6.0
6.5
0.5
4.5
0.8
3.0
0.2
1.1
4.8
7.3
3.3 5.6
–
–
0.8
0.3
34
t
4ptbpr 4 Product Term Bypass Reg. Path Delay – – 6.8 ns5.8– 5.0
Outputs
t
ob 38 Output Buffer Delay – – 2.0 ns
t
sl 39 Output Slew Limited Delay Adder – – 10.0 ns
1.6
10.0
–
–
1.2
10.0
t
oen 40 I/O Cell OE to Output Enabled – – 4.6 ns
t
odis 41 I/O Cell OE to Output Disabled – – 4.6 ns
4.2
4.2
–
–
3.2
3.2
t
goe 42 Global Output Enable – – 7.4 ns4.8– 3.8
Clocks
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. Clock) 2.7 3.6 3.6 ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.7 3.6 3.6 ns
2.7
2.7
2.3
2.3
2.3
2.3
Global Reset
t
gr 45 Global Reset to GLB – – 11.4 ns9.2
– 6.9
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
7
USE ispLSI 2096E FOR NEW DESIGNS
ispLSI 2096/A Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0,1 #42
#40, 41
0491/2000
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
t
su Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
=
=
=
=
t
co Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
3.5 ns
2.6 ns
9.3 ns
Table 2-0042B/2096
Note: Calculations are based upon timing specifications for the ispLSI 2096/A-125L.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
8
USE ispLSI 2096E FOR NEW DESIGNS
Power Consumption
Power consumption in the ispLSI 2096 and 2096A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
50
150
250
0 20 40 60 80 100 120 140
fmax (MHz)
ICC (mA)
Notes: Configuration of six 16-bit counters
Typical current at 5V, 25°C
ispLSI 2096/A
200
100
0127/2096
ICC can be estimated for the ispLSI 2096/A using the following equation:
ICC(mA) = 20 + (# of PTs * 0.67) + (# of nets * Max freq * 0.011)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
300
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
9
USE ispLSI 2096E FOR NEW DESIGNS
Pin Description
Input - This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the isp state machine.
When ispEN is high, it functions as a dedicated input pin.
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2-0002-2096
PQFP & TQFP PIN NUMBERS DESCRIPTION
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
18
46
78
15
19
50
20
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
64, 114
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
110
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
26
32
39
45
57
63
71
77
90
96
103
109
122
128
7
13
1,
97,
17,
112
33, 49,
16, 48, 82, 113
65, 81,
Global Output Enables input pins.GOE 0, GOE 1
GND
V
CC
VCC
Ground (GND)
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN0 also is used as one of the two control pins for the isp state
machine. When ispEN is high, it functions as a dedicated input pin.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
RESET
Y0, Y1, Y2
SDI/IN 0
2
ispEN
MODE/IN 1
2
51, 84,
80
83,
Dedicated input pins to the device.IN 2, IN 4, IN 5
Output - When ispEN is logic low, it functions as an output pin to read
serial shift register data.
SDO
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
SCLK/IN 3
2
14, 47, 79, 111, 115, 116 No Connect.
NC
1
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
10
USE ispLSI 2096E FOR NEW DESIGNS
Pin Configuration
ispLSI 2096/A 128-pin PQFP and TQFP Pinout Diagram
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
1
NC
Y0
VCC
GND
ispEN
RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
GND
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
VCC
GND
Y2
SCLK/IN 3
2
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
NC
1
NC
1
VCC
NC
1
IN 5
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
2
MODE/IN 1
VCC
GND
SDO
IN 2
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
ispLSI 2096/A
Top View
I/O 10
2
SDI/IN 0
I/O 59
GND
NC
1
GND
GND
1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
9764
96
122
GOE 0
GOE 1
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
0124A-2096
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
11
USE ispLSI 2096E FOR NEW DESIGNS
Part Number Description
ispLSI 2096/A Ordering Information
Conventional Packaging
Device Number
2096
1
2096A
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
ispLSI XXXXX XXX X X
Grade
Blank = Commercial
I = Industrial
X
Speed
125 = 125 MHz
f
max
100 = 100 MHz
f
max
80 = 81 MHz
f
max Power
L = Low
Package
T = TQFP
Q = PQFP
TN = Lead-Free TQFP
QN = Lead-Free PQFP
–
Device Family
81
81
128-Pin PQFP15
15
ispLSI 2096A-80LQ128
128-Pin TQFPispLSI 2096A-80LT128
FAMILY fmax (MHz)
125
125
100
ORDERING NUMBER PACKAGE
128-Pin PQFP
128-Pin TQFP
tpd (ns)
7.5
7.5
10
ispLSI
ispLSI 2096A-125LQ128
ispLSI 2096A-125LT128
128-Pin PQFPispLSI 2096A-100LQ128
100 128-Pin TQFP10 ispLSI 2096A-100LT128
81
81
128-Pin PQFP15
15
ispLSI 2096-80LQ1
128-Pin TQFPispLSI 2096-80LT1
125
125
100
128-Pin PQFP
128-Pin TQFP
7.5
7.5
10
ispLSI 2096-125LQ1
ispLSI 2096-125LT1
128-Pin PQFPispLSI 2096-100LQ1
100 128-Pin TQFP10 ispLSI 2096-100LT1
COMMERCIAL
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
FAMILY fmax (MHz)
81
81
ORDERING NUMBER PACKAGE
128-Pin PQFP
128-Pin TQFP
tpd (ns)
15
15
ispLSI
ispLSI 2096A-80LQ128I
ispLSI 2096A-80LT128I
81
81
128-Pin PQFP
128-Pin TQFP
15
15
ispLSI 2096-80LQI
1
ispLSI 2096-80LTI
1
INDUSTRIAL
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2096/A
12
USE ispLSI 2096E FOR NEW DESIGNS
ispLSI 2096/A Ordering Information (Cont.)
Lead-Free Packaging
81
81
Lead-Free 128-Pin PQFP15
15
ispLSI 2096A-80LQN128
Lead-Free 128-Pin TQFPispLSI 2096A-80LTN128
FAMILY fmax (MHz)
125
125
100
ORDERING NUMBER PACKAGE
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
tpd (ns)
7.5
7.5
10
ispLSI
ispLSI 2096A-125LQN128
ispLSI 2096A-125LTN128
Lead-Free 128-Pin PQFPispLSI 2096A-100LQN128
100 Lead-Free 128-Pin TQFP10 ispLSI 2096A-100LTN128
COMMERCIAL
FAMILY fmax (MHz)
81
81
ORDERING NUMBER PACKAGE
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
tpd (ns)
15
15
ispLSI ispLSI 2096A-80LQN128I
ispLSI 2096A-80LTN128I
INDUSTRIAL
Revision History
Date Version
09
08
August 2006
—
Change Summary
Updated for lead-free package options.
Previous Lattice release.
Select devices have been discontinued.
See Ordering Information section for product status.
