ATETHMAC-SSN8006 - Atmel Corporation

Features

•Designer-selected RX/TX FIFO Depths

•Approximately 8K Gates (not including FIFOs)

•Simple Request/Acknowledge Type Interface to Application

•IEEE 802.3 Compatible

•Supports IEEE 802.3x and IEEE 802.3Q for Flow Control

•Optional Two-part Deferral Implemented

•Full and Half Duplex

•Automatic Retries after Collision; Programmable Retry Counter

•Automatic Padding/Removal of Padded Bytes for Frame Size Requirement

•RMII or MII Interface to PHY

•Wakeup, Magic Packet (available on special request)

•MIB Counters for Network Management (available on special request)

•FCS Generation and Checking on Received Packets

•MDIO Interface

•Programmable Address Filtering

•Includes Test Environment

•8- or 32-bit Application Interface

•Verilog Model

Overview

The ATETHMAC-SSN8006 is a fully synthesizable core that can be implemented in

any Atmel ASIC library (gate array or standard cell). It is designed to interface with any

standard MII or RMII PHY chip or can be used with the Atmel ATETHPHY core for a

single-chip solution. Half-duplex mode is supported by means of Jam sequence inser-

tion, per the IEEE 802.3 standard. Extensive status-reporting mechanisms are

included for both receive and transmit. FIFO sizes can be chosen by the designer.

The core is supported by a comprehensive test environment. MII interface simulation

is included. The suite covers standard transmit and receive flows, collisions, runt

packets, FCS error simulation, loopback, address filtering, frame alignment errors and

pause frames.

System Overview

LAN Controller

DMA and

Host Int.

ATETHMAC-

SSN8006

Media

MII/RMII

PHY

Chip

10/100T

Ethernet MAC

ASIC Core

ATETHMAC-

SSN8006

Summary

Rev. 1922AS–04/01

Note: This is a summary document. A complete document is avail-

able under NDA. For more information, please contact your local

Atmel sales office.

ATETHMAC-SSN8006

Block Diagram and Module Hierarchy

tx_fsm.v

rx_fsm.v

cfg_mgmt.v

PHY

TX FIFO

tx_fifo_mgmt.v

rx_fifo_mgmt.v

RX FIFO

tx_crc32.v

deferral.v

backoff.v

rx_crc32.v

rx_top.v

tx_top.v mii_intfc.v

Application

ssn8006_top.v

mac core.v

ATETHMAC-SSN8006

I/O Diagram

PHY Chip

(MII/RMII)

Application

Interface

SSN8006

tx clk

txd[3:0]

tx_en

mdio_out

mdio_out_en

mdio_in

mdio_clk

mdc

rx_dv

col

rxd[3:0]

crs

rx clk

Configuration

app_clk

reset

app_tx_dt[8:0]/[35:0]

app_tx_wrt

clr_tx_error

tx_fifo_full

tx_fifo_p_full

tx_fifo_empty

tx_fifo_p_empty

tx_sts[31:0]

tx_sts_vld

app_data_in[7:0]

app_rw

app_addr[7:0]

app_addr_out[7:0]

send_jam_sequence

app_rx_dt[8:0]/[35:0]

app_rx_rd

clr_rx_error

rx_fifo_full

rx_fifo_p_full

rx_fifo_empty

rx_fifo_p_empty

rx_sts[31:0]

rx_sts_vld

ATETHMAC-SSN8006

Pinout

Table 1. Application to ATETHMAC-SSN8006

Signal Description

reset

Active-high signal indicates that the application intends to reset the device, including ATETHMAC-

SSN8006. This signal is usually asserted at the time of power cycle or if the application wants to

recover from a deadlock situation. This signal resets ATETHMAC-SSN8006 asynchronously. Any

pending TX and RX operations will be discarded and TX and RX FIFOS will be flushed out. The

configuration information in the register space is also initialized.

app_tx_dt[8:0]/[34:0]

The application puts the data to be transmitted on the line on this bus. The core registers the data on

this bus with the positive edge of the app_clk when app_tx_wrt is high. This bus can be configured to

interface with the application bus width of 8 bit or 32 bit. The description for configuring the core for 8

bit or 32 bit during synthesis and simulation is in the Application Note. In the 8-bit mode, the

application should set the app_tx_dt[8] high only while writing the last byte of the packet to be

transmitted. In the 32-bit mode, the application should set the app_tx_dt[34] high only while writing the

last double word (32 bits) of the packet to be transmitted. app_tx_dt[33:32] should contain the valid

byte count in the double word written by the application. The first byte of a packet should always be

aligned to the first byte of the word being written; that is, app_tx_dt[7:0] should contain the first byte of

the packet.

app_tx_wrt:

ATETHMAC-SSN8006 samples app_tx_wrt on the rising edge of the app_clk to load the app_tx_dt

into the TX FIFO. Active high app_tx_wrt indicates that the app_tx_dt is valid in the current cycle. This

signal is generated by the application synchronous to the app_clk. The application should not

advance to the next data if tx_fifo_full is asserted for the current active app_tx_wrt signal. Burst writes

to the TX FIFO can be performed by keeping the app_tx_wrt cycle asserted for multiple cycles and

app_tx_dt reloaded every subsequent cycle by the application.

app_data_in[7:0]

app_data_in is used by the application to configure the core. When app_rw is asserted, the core

registers app_data_in into the configuration register set addressed by app_addr[7:0]. This is

synchronous with app_clk.

app_rw

This signal is synchronous with app_clk. Write operations to the configuration space are performed

when this signal is asserted. Illegal addresses are ignored. Please refer to the later sections for the

details on address space.

app_addr[7:0]

This bus is used to address the configuration space. When app_rw is asserted, the core registers

app_data_in into the configuration register set addressed by app_addr[7:0]. This is synchronous with

app_clk.

app_rx_rd

The application asserts this signal to read the data from the RX FIFO in the core. This is synchronous

to app_clk. Current read would return the app_rx_dt from the RX FIFO in the same cycle. Please refer

to the waveforms in the RX Data Flow section, page 13.

clr_tx_error

The application will assert clr_tx_error to reset the transmit flow. This would flush the TX FIFO and

reset the TX FSM to IDLE state. Pending frames in the TX FIFO will be flushed. This is an

asynchronous signal.

clr_rx_error

The application will assert clr_rx_error to reset the receive flow. This would flush the RX FIFO and

reset the RX FSM to IDLE state. Pending frames in the RX FIFO will be flushed. This is an

asynchronous signal.

send_jam_sequence

Send_jam_sequence is a level signal set by the application in half_duplex mode to control the flow. If

it is asserted during the beginning of a receive packet, the core will jam the line and force a backoff on

the transmitting device.

Note: This signal is sampled only at the beginning of a packet being received. If it is asserted while a

packet reception is in progress, it has no effect on the current packet.

ATETHMAC-SSN8006

Table 2. ATETHMAC-SSN8006 to Application

Signal Description

app_rx_dt[8:0]/

[34:0]

The core puts the data received from the link on this bus. The application should assert app_rx_rd and

interface with the application bus width of 8 bit or 32 bit. The description for configuring the core for

8 bit or 32 bit during synthesis and simulation is in the Application Note. In the 8-bit mode, the core

sets app_rx_dt[8] high only when the last byte of the packet is being read. In the 32-bit mode, the core

sets the app_rx_dt[34] high only when the last double word (32 bits) of the packet is being read.

app_tx_dt[33:32] contains the valid byte count of the double word written by the application. The first

byte of a packet will always be aligned to the first byte of the word being read; that is, app_rx_dt[7:0]

will contain the first byte of the packet.

app_data_out[7:0]

The application uses this bus to read the configuration register selected by app_addr.

tx_sts_vld

ATETHMAC-SSN8006 qualifies the tx_sts with an active tx_sts_vld signal. These signals are

synchronous with respect to app_clk. Transmit status is returned to the application when a frame is

successfully transferred on to the line or dropped on excessive collisions. No status information is

returned on a deferral.

tx_sts[31:0]

tx_sts is qualified on tx_sts_vld. Transmit status would convey if the frame has been successfully

transferred or if it has been dropped on excessive collisions. This signal is synchronous to app_clk.

See Table 45 (page 26) for details of the data content. A status information is returned on every frame;

hence, it is completely in sequence to the frames scheduled for transmit.

rx_sts_vld

ATETHMAC-SSN8006 qualifies the rx_sts with an active rx_sts_vld signal. These signals are

synchronous with respect to app_clk. Receive status is returned for every frame received successfully.

Frames that do not pass the address and minimum size requirement are not loaded in the RX FIFO,

and a status is not returned to the application.

rx_sts[31:0]

rx_sts is qualified on rx_sts_vld. Receive status will indicate if the current frame has invalid FCS, size

violation, byte alignment problem, etc. Frames that do not pass the address and minimum size

requirement are not loaded in the RX FIFO, and a status is not returned to the application.

tx_fifo_full

Synchronous to app_clk. This signal is asserted when the TX FIFO is full, and it is a level signal.

tx_fifo_p_full

Synchronous to app_clk. This signal is asserted when the TX FIFO has valid data more than the

difference of maximum FIFO size and the value in the threshold_for_p_full register. This is a level

signal.

rx_fifo_full

Synchronous to app_clk. This signal is asserted when the RX FIFO is full, and it is a level signal.

rx_fifo_p_full

Synchronous to app_clk. This signal is asserted when the RX FIFO has valid data more than the

difference of maximum FIFO size and the value in the threshold_for_p_full register. This is a level

signal.

tx_fifo_empty

Synchronous to app_clk. This signal is asserted when the TX FIFO is empty, and it is a level signal.

tx_fifo_p_empty

Synchronous to app_clk. This signal is asserted when the TX FIFO has valid data count less than the

value in the threshold_for_p_empty register. This is a level signal.

rx_fifo_empty

Synchronous to app_clk. This signal is asserted when the RX FIFO is empty, and it is a level signal.

tx_fifo_p_empty

Synchronous to app_clk. This signal is asserted when the TX FIFO has valid data count less than the

value in the threshold_for_p_empty register. This is a level signal.

ATETHMAC-SSN8006

Table 3. MII Interface

Signal Description

rx_clk/tx_clk

PHY provides a 25-MHz clock. Transmit and receive functions are performed independently using this

clock.

tx_en

Indicates to the PHY that data is present on txd[3:0]. It is asserted synchronously with the first nibble

of the preamble and remains asserted until all the nibbles have been sent to the PHY. This signal is

synchronous with respect to tx_clk.

txd[3:0]

txd is a bundle of four data signals that are driven by ATETHMAC-SSN8006. txd is asserted

synchronously with respect to tx_clk. For each tx_clk period in which tx_en is asserted, data on this

bus is accepted for transmission by the PHY.

rxd[3:0]

rxd is a bundle of four data signals that transition synchronously with respect to rx_clk. rxd is driven by

PHY. For each rx_clk period in which CRS is asserted, rxd transfers nibble bits of data to the MAC.

rx_er

rx_er is driven by PHY. rx_er is asserted for one or more rx_clk periods to indicate to the MAC layer

that an error was detected somewhere in the frame presently being transferred from the PHY to the

MAC layer. This signal is synchronous with respect to rx_clk.

CRS

CRS is asserted by the PHY when the transmit or receive medium is not idle. CRS will be deasserted

by the PHY when both the transmit and receive media are idle. CRS remains asserted throughout the

duration of a collision condition. PHY asserts CRS asynchronously and deasserts synchronously with

respect to rx_clk.

COL

COL is asserted by the PHY when a collision is detected by PHY.

rx_dv

rx_dv is valid for the duration of the rx_clk.

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1922AS–04/01

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