QT60248-ASG - ATMEL - Product.Network

lQQProx™ QT60168, QT60248

16, 24 K

ATRIX

™ IC

APPLICATIONS

yAutomotive panels

yMachine tools

yATM machines

yTouch-screens

yAppliance controls

yOutdoor keypads

ySecurity keypanels

yIndustrial keyboards

These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up to 16 or 24 keys when used with a

scanned, passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, and even

wood, up to thicknesses of 5 cm or more. The touch areas are defined as simple 2-part interdigitated electrodes of conductive material,

like copper or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and placement are almost entirely

arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area. The

sensitivity of each key can be set individually via simple functions over the serial port by a host microcontroller. Key setups are stored

in an onboard eeprom and do not need to be reloaded with each powerup.

These devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, or

similar products that are subject to environmental influences or even vandalism. They permit the construction of 100% sealed,

watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel surface

from abrasion, chemicals, or abuse. To this end they contain Quantum-pioneered adaptive auto self-calibration, drift compensation, and

digital filtering algorithms that make the sensing function robust and survivable.

These devices feature continuous FMEA self-test and reporting diagnostics, to allow their use in critical consumer appliance

applications, for example ovens and cooktops.

Common PCB materials or flex circuits can be used as the circuit substrate; the overlying panel can be made of any non-conducting

material. External circuitry consists of only a few passive parts. Control and data transfer is via an SPI port.

These devices makes use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that

minimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.

QT60248-AS R4.02/0405

zSecond generation charge-transfer QMatrix technology

zKeys individually adjustable for sensitivity, response

time, and many other critical parameters

zPanel thicknesses to 50mm through any dielectric

z16 and 24 touch key versions

z100% autocal for life - no adjustments required

zSPI slave interface

zAdjacent key suppression feature

zSynchronous noise suppression feature

zSpread-spectrum modulation - high noise immunity

zMix and match key sizes & shapes in one panel

zLow overhead communications protocol

zFMEA compliant design features

zNegligible external component count

zExtremely low cost per key

z+3 to +5V single supply operation

z32-pin lead-free TQFP package

/RST

Y2A

Y1A

Y0A

Y2B

VREF

SYNC

SMP

DRDY

MOSI

MISO

VSS

VDD

VSS

VDD

X6 SCK

VDD

SYNC

VDD

VSS

n/c

Y0B

Y1B1

817

32 31 30 29 28 27 26 25

910 11 161514

QT60248

QT60168

TQFP-32

YesQT60248-ASG24-40

C to +105

YesQT60168-ASG16-40

C to +105

Lead-FreePart Number# KeysT

AVAILABLE OPTIONS

4.8 Report Error Flags for All Keys - 0x0b

..............

Table 4.1 Bits for key reporting and numbering

............

4.7 Report Detections for All Keys - 0x07

..............

4.6 Report 1st Key - 0x06

......................

4.5 General Status - 0x05

......................

4.4 Force Reset - 0x04

.......................

4.3 Cal All - 0x03

..........................

4.2 Enter Setups Mode - 0x01

....................

4.1 Null Command - 0x00

......................

4 Control Commands

.......................

3.3 Command Error Handling

....................

3.2 SPI Communications

......................

3.1 DRDY Pin

............................

3 Serial Communications

.....................

Figure 2.7 Wiring Diagram

......................

Table 2.2 - Pin Listing

.......................

2.17 Wiring

.............................

2.16 FMEA Tests

..........................

2.15 Detection Integrators

......................

2.14 Spread Spectrum Acquisitions

.................

2.13 Reset Input

..........................

Table 2-1 Basic Timings

......................

2.12 Startup / Calibration Times

...................

2.11 Power Supply Considerations

.................

2.10.2 PCB Cleanliness

.......................

2.10.1 LED Traces and Other Switching Signals

............

2.10 PCB Layout, Construction

...................

2.9 Key Design

...........................

2.8 Matrix Series Resistors

.....................

2.7 Signal Levels

..........................

2.6 Sample Resistors

........................

2.5 Sample Capacitors; Saturation

.................

2.4 Oscillator

............................

2.3 Response Time

.........................

2.2 Disabling Keys; Burst Paring

...................

2.1 Matrix Scan Sequence

......................

2 Hardware & Functional

.....................

1.2 Enabling / Disabling Keys

....................

1.1 Part differences

.........................

1 Overview

..............................

7.3 PCB Layout

...........................

7.2 1-Sided Key Layout

.......................

7.1 8-Bit CRC Algorithm

.......................

7 Appendix

.............................

6.6 Marking

.............................

6.5 Mechanical Dimensions

.....................

6.4 Timing Specifications

......................

6.3 DC Specifications

........................

6.2 Recommended operating conditions

...............

6.1 Absolute Maximum Electrical Specifications

...........

6 Specifications

..........................

Table 5.3 Setups Block Summary

..................

Table 5.2 Key Mapping

.......................

Table 5.1 Setups Block

.......................

5.13 Host CRC - HCRC

.......................

5.12 Lower Signal Limit - LSL

....................

5.11 Burst Spacing - BS

.......................

5.10 Mains Sync - MSYNC

.....................

5.9 Oscilloscope Sync - SSYNC

...................

5.8 Adjacent Key Suppression - AKS

................

5.7 Burst Length - BL

........................

5.6 Positive Recalibration Delay - PRD

...............

5.5 Negative Recal Delay - NRD

...................

5.4 Detect Integrators - NDIL, FDIL

.................

5.3 Drift Compensation - NDRIFT, PDRIFT

.............

5.2 Positive Threshold - PTHR

...................

5.1 Negative Threshold - NTHR

...................

5 Setups

...............................

Table 4.2 Command Summary

....................

4.18 Command Sequencing

.....................

4.17 Cal Key ‘k’ - 0xck

........................

4.16 Status for Key ‘k’ - 0x8k

....................

4.15 Data Set for One Key - 0x4k

..................

4.14 Internal Code - 0x12

......................

4.13 Internal Code - 0x10

......................

4.12 Return Last Command - 0x0f

..................

4.11 Eeprom CRC - 0x0e

......................

4.10 Dump Setups Block - 0x0d

...................

4.9 Report FMEA Status - 0x0c

...................

2 QT60248-AS R4.02/0405

Contents

1 Overvie

QMatrix devices are digital burst mode charge-transfer (QT)

sensors designed specifically for matrix geometry touch

controls; they include all signal processing functions necessary

to provide stable sensing under a wide variety of changing

conditions. Only a few external parts are required for operation.

The entire circuit can be built within a few square centimeters of

single-sided PCB area. CEM-1 and FR1 punched, single-sided

materials can be used for possible lowest cost. The PCB’s rear

can be mounted flush on the back of a glass or plastic panel

using a conventional adhesive, such as 3M VHB 2-sided

adhesive acrylic film.

QMatrix parts employ transverse charge-transfer ('QT') sensing,

a technology that senses changes in electrical charge forced

across an electrode by a pulse edge (Figure 1-1). QMatrix

devices allow for a wide range of key sizes and shapes to be

mixed together in a single touch panel.

The devices use an SPI interface to allow key data to be

extracted and to permit individual key parameter setup. The

interface protocol uses simple single byte commands and

responds with single byte responses in most cases. The

command structure is designed to minimize the amount of data

traffic while maximizing the amount of information conveyed.

In addition to normal operating and setup functions the device

can also report back actual signal strengths and error codes.

QmBtn software for the PC can be used to program the

operation of the IC as well as read back key status and signal

levels in real time.

The QT60168 and QT60248 are electrically identical with the

exception of the number of keys which may be sensed.

1.1 Part differences

Versions of the device are capable of a maximum of 16 or 24

keys (QT60168, QT60248 respectively).

These devices are identical in all respects, except that each is

capable of only the number of keys specified. These keys can

be located anywhere within the electrical grid of 8 X and 3 Y

scan lines.

Unused keys are always pared from the burst sequence in

order to optimize speed. Similarly, in a given part a lesser

number of enabled keys will cause any unused acquisition burst

timeslots to be pared from the sampling sequence to optimize

acquire speed. Thus, if only 14 keys are actually enabled, only

14 timeslots are used for scanning.

1.2 Enabling / Disabling Keys

The NDIL parameter is used to enable and disable keys in the

matrix. Setting NDIL = 0 for a key disables it (Section 5.4). At

no time can the number of enabled keys exceed the maximum

specified for the device in the case of the QT60168.

On the QT60168, only the first 2 Y lines (Y0, Y1) are

operational by default. On the QT60168, to use keys located on

line Y2, one or more of the pre-enabled keys must be disabled

simultaneously while enabling the desired new keys. This can

be done in one Setups block load operation.

2 Hardware & Functional

2.1 Matrix Scan Sequence

The circuit operates by scanning each key sequentially, key by

key. Key scanning begins with location X=0 / Y=0 (key #0). X

axis keys are known as rows while Y axis keys are referred to

as columns. Keys are scanned sequentially by row, for example

the sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys are

also numbered from 0..24. Key 0 is located at X0Y0. A table of

key numbering is located on page 22.

Each key is sampled in a burst of acquisition pulses whose

length is determined by the Setups parameter BL (page 20),

which can be set on a per-key basis. A burst is completed

entirely before the next key is sampled; at the end of each burst

the resulting signal is converted to digital form and processed.

The burst length directly impacts key gain; each key can have a

unique burst length in order to allow tailoring of key sensitivity

on a key by key basis.

2.2 Disabling Keys; Burst Paring

Keys that are disabled by setting NDIL =0 (Section 5.4, page

19) have their bursts pared from the scan sequence to save

time. This has the consequence of affecting the scan rate of the

entire matrix as well as the time required for initial matrix

calibration.

Reducing the number of enabled keys also reduces the time

required to calibrate an individual key once the matrix is initially

calibrated after power-up or reset, since the total cycle time is

proportional to the number of enabled keys.

Keys that are disabled report as follows:

Signal = 0

Reference = 0

Low-signal error flag (provided LSL >0)

Calibrating flag for key set only just after device reset or

after a CAL command, for one scan cycle only

Failed calibration error for key always set

Detect flag for key never set

See also Section 5.4, page 19.

The devices feature a detection integration mechanism, which

acts to confirm a detection in a robust fashion. The basic idea is

to increment a per-key counter each time the key has crossed

its threshold. When this counter reaches a preset limit the key

is finally declared to be touched. Example: If the limit value is

10, then the device has to detect a threshold crossing 10 times

in succession without interruption, before the key is declared to

be touched. If on any sample the signal is not seen to cross the

threshold level, the counter is cleared and the process has to

start over from the beginning.

The QT60xx8 uses a two-tier confirmation mechanism having

two such counters for each key. These can be thought of as

‘inner loop’ and ‘outer loop’ confirmation counters.

The ‘inner’ counter is referred to as the ‘fast-DI’; this acts to

attempt to confirm a detection via rapid successive acquisition

bursts, at the expense of delaying the sampling of the next key.

Each key has its own fast-DI counter and limit value; these

limits can be changed via the Setups block on a per-key basis.

The ‘outer’ counter is referred to as the ‘normal-DI’; this DI

counter increments whenever the fast-DI counter has reached

its limit value. If a fast-DI counter failed to reach its terminal

count, the corresponding normal-DI counter is also reset. The

normal-DI counter also has a limit value which is settable on a

per-key basis. If a normal-DI counter reaches its terminal count,

the corresponding key is declared to be touched and becomes

‘active’. Note that the normal-DI can only be incremented once

per complete keyscan cycle, ie more slowly, whereas the

fast-DI is incremented ‘on the spot’ without interruption.

The net effect of this mechanism is a multiplication of the inner

and outer counters and hence a highly noise-resistance

sensing method. If the inner limit is set to 5, and the outer to 3,

the net effect is 5x3=15 successive threshold crossings to

declare a key as active.

2.16 FMEA Tests

FMEA (Failure Modes and Effects Analysis) is a tool used to

determine critical failure problems in control systems. FMEA

analysis is being applied increasingly to a wide variety of

applications including domestic appliances. To survive FMEA

testing the control board must survive any single problem in a

way that the overall product can either continue to operate in a

safe way, or shut down.

The most common FMEA requirements regard opens and

shorts analysis of adjacent pins on components and

connectors. However other criteria must usually be taken into

account, for example complete device failure, and the use of

redundant signaling paths.

QT60xx8 devices incorporate special self-test features which

allow products to pass such FMEA tests easily. These tests are

performed during a dummy timeslot after the last enabled key.

The FMEA testing is done on all enabled keys in the matrix, and

results are reported via the serial interface through a dedicated

status command (page 13). Disabled keys are not tested. The

existence of an error is also reported in normal key reporting

commands such as Report 1st Key, page 13.

All FMEA tests are repeated every second or faster during

normal run operation. Sometimes, FMEA errors can occur

intermittently, for example due to momentary power

fluctuations. It is advisable to confirm a true FMEA fault

condition by making sure the error flags persist for a several

seconds.

Since the devices only communicate in slave mode, the host

can determine immediately if the QT has suffered a

catastrophic failure.

The FMEA tests performed are:

X drive line shorts to Vdd and Vss

X drive line shorts to other pins

X drive signal deviation

Y line shorts to Vdd and Vss

Y line shorts to other pins

X to Y line shorts

Cs capacitor checks including shorts and opens

Vref test

Key gain test

Other tests incorporated into the devices include:

A test for signal levels against a preset min value (LSL

setup, see page 21). If any signal level falls below this

level, an error flag is generated.

CRC communications checks on all critical command and

data transmissions.

‘Last-command’ command to verify that an instruction was

properly received.

Some very small key designs have very low X-Y coupling. In

these cases, the amount of signal will be very small, and the

key gain will be low. As a result, small keys can fail the LSL

test (page 21) or the FMEA key gain test (above). In such

cases, the burst length of the key should be increased so that

the key gain increases. Failing that, a small ceramic capacitor,

for example 3pF, can be added between the X and Y lines

serving the key to artificially boost signal strength.

For those applications requiring it, Quantum can supply sample

FMEA test data on special request.

7 QT60248-AS R4.02/0405

2.17 Wiring

Table 2.2 - Pin Listing

Leave openX2 matrix drive lineOX232

Leave openX1 matrix drive lineOX131

Leave openX0 matrix drive lineOX030

Leave open or Vdd

Reset low;

has internal 30K ~ 80K pull-up

I/RST29

Y2A line connectionIY2A28 Leave open

Y1A line connectionIY1A27

Y0A line connectionIY0A26 Leave open

Y2B line connectionIY2B25

Y1B line connectionIY1B24 Leave open

Y0B line connectionIY0B23

Leave openNot usedN/ANC22

-Supply groundPVss21

-Power, +3 ~ +5VPVdd20

VddMains sync inputISYNC19

-Power, +3 ~ +5VPVdd18

-SPI clock inputISCK17

-SPI data outputOMISO16

-SPI data inputIMOSI15

SPI slave select;

has internal 20K ~ 50K pull-up

I/SS14

1= Comms ready;

has internal 20K ~ 50K pull-up

ODRDY13

-Sample drive outputOSMP12

Leave openScope Sync: Synchronization test signal outputOS_Sync11

-0.05V nominal +/-10% via external dividerIVref10

Leave openX7 matrix drive lineOX79

Leave openX6 matrix drive lineOX68

Leave openX5 matrix drive lineOX57

-Power, +3 ~ +5VPVdd6

-Supply groundPVss5

-Power, +3 ~ +5VPVdd4

-Supply groundPVss3

Leave openX4 matrix drive lineOX42

Leave openX3 matrix drive lineOX31

If Unused, Connect To..CommentsI/OFunctionPin

8 QT60248-AS R4.02/0405

Figure 2.7 Wiring Diagram

See Table 2.2 for further connection information.

9 QT60248-AS R4.02/0405

MATRIX Y SCAN IN MATRIX X DRIVE

MISO

MOSI

DRDY

Note 1

SCLK

10K

100

RS2

470K

RS0

470K

1KRX2

1KRX6

1KRY1

1KRY2

1KRY0

1KRX0

1KRX4

Vunreg +3 to +5V

VREG

VDD

QT60248

QT60168

100nF

LINE SYNC

SCOPE SYNC

Note 2

VDD

SPI

4.7uF 4.7uF

RS1

470K

Note 1: Wire 100nF bypass cap

very close to pins 3, 4, 5, 6

Note 2: Leave Y2A, Y2B unconnected

for QT60168

CS1 4.7nF

1KRX1

1KRX3

1KRX7

CS2 4.7nF

4.7nFCS0

1KRX5

3 Serial Communications

These devices use SPI communications, in slave mode.

The host device always initiates communications sequences;

the QT is incapable of chattering data back to the host. This is

intentional for FMEA purposes so that the host always has total

control over the communications with the QT60xx8. In SPI

mode the device is a slave, so that even return data following a

command is controlled by the host.

A command from the host always ends in a response of some

kind from the QT. Some transmission types from the host or the

QT employ a CRC check byte to provide for robust

communications.

A DRDY line is provided that handshakes transmissions.

Generally this is needed by the host from the QT to ensure that

transmissions are not sent when the QT is busy or has not yet

processed a prior command.

Initiating or Resetting Communications: After a reset, or,

should communications be lost due to noise or out-of-sequence

reception, the host should send a 0x0f (return last command)

command repeatedly until the compliment of 0x0f, i.e. 0xf0, is

received back. Then, the host can resume normal run mode

communications from a clean start.

Poll rate: The typical poll rate in normal ‘run’ operation should

be no faster than once per 10ms; 25ms is more than fast

enough to extract status data using the 0x06 command (report

first key: see page 13) in most situations. Streaming multi-byte

response commands like the 0x0d command (dump setups: see

page 13) or multi-byte response commands like 0x07 can and

should pace at the maximum possible rate.

Run Poll Sequence: In normal run mode the host should limit

traffic with a minimalist control structure (see also Section 4.18).

The host should just send a 0x06 command until something

requires a deeper state inspection. If there is more than one key

in detect, the host should use 0x07 to find which additional keys

are in detect. If there is an error, the host should ascertain the

error type based on commands 0x0b and 0x0c and take

appropriate action. Issuing a 0x07 command all the time is

wasteful of bandwidth, requires more host processor time, and

actually conveys less information (no error flags are sent via a

0x07 command).

3.1 DRDY Pin

DRDY is an open-drain output with an internal 20K ~ 50K pullup

resistor.

Serial communications pacing is controlled by this pin. The host

is permitted to send data only when DRDY is high. After a byte

is received DRDY will always go low even if only for a few

microseconds; during this period the host should not send data.

Therefore, after each byte transmission the host should first

check that DRDY is high again.

If the host desires to send a byte to the QT it should behave as

follows:

1. If DRDY is low, wait

2. If DRDY is high: send a command to QT

3. Wait at least 40µs (time S5 in Figure 3-3: DRDY is

guaranteed to go low before this 40µs expires)

4. Wait until DRDY is high (it may already be high again)

5. Send next command or a null byte 0x00 to QT

The time it takes for DRDY to go high again after a command

depends on the command. Following is a list of commands and

the time required to process them and then raise DRDY:

0x0E Eeprom CRC [ 25ms

0x01 Load Setups [ 25ms

All other commands: [ 2ms between bytes;

[ 40µs after CRC byte is sent

Other DRDY specs:

Min time DRDY is low: 1µs

Min time DRDY is low

after reset: 1ms

3.2 SPI Communications

SPI communications operates in slave mode only, and obeys

DRDY control signaling. The clocking is as follows:

Clock idle: High

Clock shift out edge: Falling

Clock data in edge: Rising

Max clock rate: 1.5MHz

SPI mode requires 5 signals to operate:

MOSI - Master out / Slave in data pin; used as an input for

data from the host (master). This pin should be connected

to the MOSI (DO) pin of the host device.

MISO - Master in / Slave out data pin; used as an output for

data to the host. This pin should be connected to the MISO

10 QT60248-AS R4.02/0405

Figure 3-2 Filtered SPI Connections

MOSI

MISO

SCK

DRDY

QT60

8 Circuit

RESET

Host MCU

X drives

(1 of 8

shown)

Y Lines

(1 of 3

shown)

1nF

SCK

MISO

MOSI

P_IN

P_OUT1

P_OUT2

1nF2,20050kHz

470pF2,200100kHz

270pF1,000400kHz

100pF6801.5MHz

CaRaSPI Clock Rate

Recommended Values of Ra & Ca

Figure 3-1 Basic SPI Connections

MOSI MOSI

MISOMISO

SCK SCK

DRDY

P_OUT

P_IN

Host MCU QT60xx8

(DI) pin of the host. MISO floats when /SS is high to allow

multi-drop communications along with other slave parts.

SCK - SPI clock - input only clock from host. The host must

shift out data on the falling SCK edge; the QT60xx8 clocks

data in on the rising edge. The QT60xx8 likewise shifts data

out on the falling edge of SCK back to the host so that the

host can shift the data in on the rising edge. Important:

SCK must idle high; it should never float.

/SS - Slave select - input only; acts as a framing signal to the

sensor from the host. /SS must be low before and during

reception of data from the host. It must not go high again

until the SCK line has returned high; /SS must idle high.

This pin includes an internal pull-up resistor of 20K ~ 50K.

When /SS is high, MISO floats.

DRDY - Data Ready - active-high - indicates to the host that

the QT is ready to send or receive data. This pin idles high.

This pin includes an internal pull-up resistor of 20K ~ 50K.

In SPI mode this pin is an output only (i.e. open drain with

internal pull-up).

The MISO pin on the QT floats in 3-state mode between bytes

when /SS is high. This facilitates multiple devices on one SPI

bus.

Null Bytes: When the QT responds to a command with one or

more response bytes, the host should issue a null commands

(0x00) to get the response bytes back. The host should not

send new commands until all the responses are accepted back

from the QT from the prior command via nulls.

New commands attempted during intermediate byte transfers

are ignored.

SPI Line Noise: In some designs it is necessary to run SPI

lines over ribbon cable across a lengthy distance on a PCB.

This can introduce ringing, ground bounce, and other noise

problems which can introduce false SPI clocking or false data.

Simple RC networks and slower data rates as shown in Figure

3-2 are helpful to resolve these issues.

CRC checks have been added to critical commands in order to

detect transmission errors to a high level of certainty.

3.3 Command Error Handling

If an unrecognized command is received, the device will release

DRDY high and the communications error flag will be set in the

General Status byte (see Section 4.5).

4 Control Commands

Refer to Table 4.2, page 16 for further details.

The devices feature a set of commands which are used for

control and status reporting. The host device has to send the

command to the QT60xx8 and await a response.

SPI mode: While waiting the host should delay for 40µs from

the end of the command, then start to check if DRDY is or goes

high. If it is high, then the host master can clock out the

resulting byte(s).

Command timeouts: Where a command involves multi-byte

transfers in either direction, each byte must be transmitted

within 100ms of the prior byte or the command will timeout. No

error is reported for this condition; the command simply ceases.

Word return byte order: Where a word or long word is

returned (16 or 24 bit number or bit pattern) the low order byte

is sent or received first.

4.1 Null Command - 0x00

Used to shift back data from the QT. Since the host device is

always the master in SPI mode, and data is clocked in both

directions, the Null command is required frequently to act as a

placeholder where the desire is to only get data back from the

QT, not to send a command.

In SPI communications, when the QT60xx8 responds to a

command with one or more response bytes, the host can issue

a new command instead of a null on the last byte shift

operation.

New commands during intermediate byte shift-out operations

are ignored, and null bytes should always be used.

11 QT60248-AS R4.02/0405

Figure 3-3 SPI Slave-Only Mode Timing

S1: m333ns S2: [20ns S3: m25ns S4: [20ns

S5: [40µs S6: m1µs S7: m333ns S8: m333ns S9: m667ns

high via pullup-R

DRDY

(from QT)

S1 S5

/SS

(from Host)

CLK

(from Host)

MOSI

(Data from Host)

MISO 3-state 3-state

(Data from QT)

023671210 45

450123765 67210 ??43

543

076? 7654321

76543210

Data shifts out of QT on falling edge

data response

{optional 2nd command byte} {null byte or next command to get QT response}

Data shifts in to QT on rising edge

{Command byte} S4S2

4.2 Enter Setups Mode - 0x01

This command is used to initiate the Setups block transfer from

Host to QT.

The command must be repeated 2x within 100ms or the

command will fail; the repeating command must be sequential

without any intervening command. After the 2nd 0x01 from the

host, the QT will stop scanning keys and reply with the

character 0xFE. In SPI mode this character must be shifted out

by sending a null (0x00) from the host. This command

suspends normal sensing starting from the receipt of the

second 0x01. A failure of the command will cause a timeout.

Each byte in the block must arrive at the QT no later than

100ms after the previous one or a timeout will occur.

Any timeout will cause the device to cancel the block load and

go back to normal operation.

If no response comes back, the command was not received and

the device should preferably be reset from the host by hardware

reset just in case there are any other problems.

If 0xFE is received by the host, then the host should begin to

transmit the block of Setups to the QT. DRDY handshakes the

data. The delay between bytes can be as short as 10µs but the

host can make it longer than this if required, but no more than

100ms. The last byte the host should send is the CRC for the

block of data only, ie the command itself should not be folded

into the CRC.

After the block transfer the QT will check the CRC and respond

with 0x00 if there was an error. Regardless, it will program the

internal eeprom. If the CRC was correct it will reply with a

second 0xFE after the eeprom was programmed.

At the end of the full block load sequence, the device restarts

sensing without recalibration.

It is highly recommended that

the part be reset after a block load to allow the part to

properly initialize itself, clear any setup flags, using the reset

command or the reset pin.

4.3 Cal All - 0x03

This command must be repeated 2x within 100ms or the

command will fail; the repeating command must be sequential

without any intervening command.

After the 2nd 0x03 from the host, the QT will reply with the

character 0xFC. Shortly thereafter the device will recalibrate all

keys and restart operation.

If no 0xFC comes back, the command was not properly

received and the device should preferably be reset.

The host can monitor the progress of the recalibration by

checking the status byte, using command 0x05.

A key will show an error flag (via command 0x8k) indicating the

key has failed calibration if its signal is too noisy or if its signal is

below the low signal threshold. A key is deemed too noisy if, at

the end of calibration, the signal is no longer between its

computed negative hysteresis level and positive thresholds.

4.4 Force Reset - 0x04

The command must be repeated 2x within 100ms or the

command will fail; the repeating command must be sequential

without any intervening command. After the 2nd 0x04, the QT

will reply with the character 0xFB just prior to executing the

reset operation.

The host can monitor the progress of the reset by checking the

status byte for recalibration, using command 0x05. The

complete reset sequence is as follows:

1. Reset command received by QT

2. Response byte (0xFB) recovered by host

3. DRDY floats high

4. 20ms elapses until device completes reset

5. DRDY clamped low

6. 4ms or 22ms elapses - (see Section 2.12)

7. DRDY floats high again - device reset has completed

If the host does not recover the response byte in step 2, the

QT device will self-reset within 2 seconds.

4.5 General Status - 0x05

This command returns the general status bits. They are as

follows:

1= any key in detect0

1= any key in calibration1

1= calibration has failed on an

enabled key or, an LSL failure

1= mains sync error3

Reserved4

1= FMEA failure detected5

1= communications error6

Reserved7

DescriptionBIT

Notes:

Bit 7: Reserved

Bit 6: Set if a communications failure, such as an unrecognized

command. This bit can be reset by sending command 0x0f

(“last command command”) repeatedly until a response of 0xf0

is received.

Bit 5: Set if an FMEA error was detected during operation. See

Section 2.16. A further amplification of what the FMEA error

consisted of is described in Section 4.9.

Bit 4: Reserved

Bit 3: Set if there was a mains sync error, for example there

was no Sync signal detected within the allotted 100ms amount

of time. See Section 5.10. This condition is not necessarily fatal

to operation, however the device will operate very slowly and

may suffer from noise problems if the sync feature was required

for noise reasons.

Bit 2: Reports either a cal failure (failed in 5 sequential

attempts) on any enabled key or, that an enabled key has a

very low signal reference value, lower than the user-settable

LSL value (Section 5.12). Disabled keys do not cause this bit 2

error flag to be set even if they generate an error flag in the

0x8k response.

Bit 1: Set if any key is in the process of calibrating.

Bit 0: Set if any key is in detection (touched).

A CRC byte is appended to the response to the 0x05 command;

this CRC folds in the command value 0x05 itself initially.

12 QT60248-AS R4.02/0405

4.6 Report 1st Key - 0x06

Reports the first or only key to be touched, plus indicates if

there are yet other keys that are also touched.

The return bits are as follows:

Key bit 00

Key bit 11

Key bit 22

Key bit 33

Key bit 44

Unused5

1= any error condition is present6

1= more than 1 key is active7

DescriptionBIT

Bits 4..0 encode for the first detected key in range 0..23. If no

keys are active, these 5 bits are all 1’s (0x1F, 31 decimal when

bits 5, 6, 7 are masked off). Disabled keys do not report as

active and do not generate an error flag in bit 6, even if they are

reporting an error via command 0x8k.

If 2 or more keys in detection, bit 7 is set and the host should

interrogate the part via the 0x07 command to read out all the

key detections. This one command should be the dominant

interrogation command in the host interface; further commands

can be issued if the response to 0x06 warrants it.

A CRC byte is appended to the response; this CRC folds in the

command 0x06 itself initially.

4.7 Report Detections for All Keys - 0x07

Returns three bytes which indicate all keys in detection if any,

as a bitfield; active keys report as 1’s.. Key 0 reports in bit 0 of

the first byte returned; key 23 is reported in bit 7 of the last byte

returned. See Table 4.1 and Table 5.2. Disabled keys report as

inactive (0).

A CRC byte is appended to the response; this CRC folds in the

command 0x07 itself initially.

Table 4.1 Bits for key reporting and numbering

1617181920212223

89101112131415

01234567

Byte Number

Returned

(Y line #)

01234567

Bit Number (X line #)Key #

4.8 Report Error Flags for All Keys - 0x0b

Returns three bytes which show error flags as a bitfield for all

keys. Key 0 reports in bit 0 of the first byte returned; key 23 is

reported in bit 7 of the last byte returned. See Table 4.1 and

Table 5.2.

A key that is in calibration also is reported as an error in the

response. The error flag is self-cleared once the key

successfully exits from calibration.

Important note: These error bits exclude FMEA error flags.

A CRC byte is appended to the response; this CRC folds in the

command 0x0b itself initially.

4.9 Report FMEA Status - 0x0c

Returns one byte which shows the FMEA error status of the X

and/or Y matrix scan lines. If an X line is in error, the

corresponding bit (below) is set. If a Y line has an FMEA error,

the entire field is set to ones (0xFF).

Due to the physics of matrix wiring, a fault on any Y line will

cause faults to be reported on all X lines as well. It is not

possible to separate out these faults for reporting purposes.

X0X1X2X3X4X5X6X7

b0b1b2b3b4b5b6b7

A CRC byte is appended to the response; this CRC folds in the

command 0x0C itself initially.

Sometimes, FMEA errors can occur intermittently, for example

due to momentary power fluctuations. It is advisable to confirm

a true FMEA fault condition by making sure the error flags

persist for a several seconds.

For more information see Section 2.16.

4.10 Dump Setups Block - 0x0d

This command causes the device to dump the entire internal

Setups block back to the host.

If the transfer is not paced faster than 100ms per byte the

transfer will be aborted and the device will time out. This can

happen if the host is also controlling DRDY.

During the transfer, sensing is halted. Sensing is resumed after

the command has finished.

An 8-bit CRC is appended to the response; this CRC is the

same as the Setups table CRC.

4.11 Eeprom CRC - 0x0e

This command returns the 8-bit CRC byte calculated from the

eeprom contents. The CRC sent back is the same CRC that is

appended to the end of the Setups block.

This command requires substantial amounts of time to process

and return a result; it is not recommended to use this command

except perhaps on startup or very infrequently.

No CRC is appended to the response.

4.12 Return Last Command - 0x0f

This command returns the last received command character, in

1’s complement (inverted). If the command is repeated twice or

more, it will return the inversion of 0x0f, 0xf0.

If a prior command was not valid or was corrupted, it will return

the bad command as well. This command also will reset the

communications error flag (Section 4.5).

No CRC is appended to the response.

4.13 Internal Code - 0x10

This command returns a 1-byte internal code.

A CRC byte is appended to the response; this CRC folds in the

command 0x10 itself initially.

4.14 Internal Code - 0x12

This command returns an internal code byte of the part for

factory diagnostic purposes. A response might take as long as

500ms.

No CRC is appended to the response.

13 QT60248-AS R4.02/0405

4.15 Data Set for One Key - 0x4k

Returns the data set for key k, where k = {0..23} encoded into

the low nibble of this command. This command returns 5 bytes,

in the sequence:

Signal (2 bytes)

Reference (2 bytes)

Normal Detect Integrator (1 byte)

Signal and Reference are returned LSByte first. No CRC is

appended.

Keys that are disabled report ‘0’ for both signal and reference.

4.16 Status for Key ‘k’ - 0x8k

Returns a bitfield for key ‘k’ where k is from {0..23}. The bitfield

indicates as follows:

1= cal on this key failed 5 times0

1= this key is in cal1

1= signal ref < LSL (low signal error)2

1= key is in detect3

1= key is enabled4

1= reserved5

1= reserved6

1= reserved7

DescriptionBIT

Bit 2 - LSL notes: See page 21.

A CRC byte is appended to the response; this CRC folds in the

command 0x8k itself initially.

Disabled Keys: A disabled key never reports as being in

detect, but always reports an LSL error (if LSL >0). An LSL error

flag generated for this reason is not reflected elsewhere, for

example via the 0x05 or 0x06 commands. An LSL error on an

enabled key is however reflected in the 0x05 and 0x06

commands.

A disabled key also reports back with bit 0 high (failed Cal). A

Cal error flag generated for this reason is not reflected

elsewhere, for example via the 0x05 or 0x06 commands. A Cal

error on an enabled key is however reflected in the 0x05 and

0x06 commands.

Just after reset or after a CAL command (commands 0x03 or

0xCk), a disabled key will report back as being in calibration for

only one matrix scan cycle, then will report as having failed cal.

See also Section 2.2.

4.17 Cal Key ‘k’ - 0xck

This command must be repeated 2x within 100ms or the

command will fail; the repeating command must be sequential

without any intervening command.

This command functions the same as 0x03 CAL command

except this command only affects one key ‘k’ where ‘k’ is from 0

to 23.

The chosen key ‘k’ is recalibrated in its native timeslot; normal

running of the part is not interrupted and all other keys operate

correctly throughout. This command is for use only during

normal operation to try to recover a single key that has failed or

is not calibrated correctly.

Returns the 1’s compliment of 0xck just before the key is

recalibrated.

4.18 Command Sequencing

To interface the device with a host, the flow diagram of Figure

4-1, page 15, is suggested. The actual settings of the Setups

block used should normally just be the default settings except

where changes are specifically required, such as for sensiti vity,

timing, or AKS changes.

The circles in this drawing are communications interchanges

between host and sensor. The rectangles are internal host

states or processing events. If any communications exchange

fails, either the device will fail to respond within the allotted time,

or the response CRC will be incorrect, or the response will be

out of context (the response is clearly not for the intended

command). In these cases the host should just repeat the

command.

The control flow will spend 99% of its time alternating between

the two states within the dashed rectangle. If a key is detected,

the control flow will enter ‘Key Detection Processing’.

Stuck Key Detection processing (0xCk) is optional, since the

device contains the max on-duration timeout function and can

therefore recalibrate the stuck key automatically. However, the

host can recalibrate stuck keys with greater flexibility if the

recalibration timeouts are set to infinite and the host recalibrates

them under specific conditions.

Error handling takes place whenever an error flag is detected,

or the device stops communicating (not shown). The error

handling procedure is up to the designer, however normally this

would entail shutting down the product if the error is serious

enough (for example, a key that will not calibrate, or a FMEA

class error).

An eeprom CRC error report is serious, and requires that the

host reload the Setups table into the device and thereafter issue

a reset command or hardware reset.

The ‘Last Command’ command can be used at any time to clear

comms error flags and to resynchronize failed communications,

for example due to timing errors etc.

14 QT60248-AS R4.02/0405

15 QT60248-AS R4.02/0405

Figure 4-1 Suggested Communications Flow

0x0E

Setups CRC

Check

0x04

Force Reset

0x06

Report 1st Key

0x07

Report all

detections

Only 1 Key

in Detect

0xck

Cal Key 'k'

~10ms Delay

Key Detection(s) Processing

No key,

no error

m2 Keys

Detected

resolvable

error

0x0F

Get

'Last command'

(clear error)

Comms

Error

Setups CRC failed 2x

Setups CRC

failed 1x

0x05

Get

General Status

calibration fail, or

FMEA fail, or

multiple errors

CRC is OK

Power On or Hardware Reset

Stuck Key

Detected

(optional)

0x0C

Get

FMEA Status

0x0B

Get

Errors for All

Keys

Error Handling

Error Flag

(takes

precedence)

FMEA

Error

Calibration

Error

Done

Keys OK

Note: CRC errors or incorrect

responses should cause

each transmission to retry

Internal Host

Processes

Comms with

0x0F

Get

'Last command' 0xF0

returned

0xF0 not

returned

0x01

Load Setups

Block

132nd return byte is CRC-8 of cmmd + return data

Yes

0..0xFF21

FMEA bitfield on X, Y linesFMEA status

0x0C

134th return byte is CRC-8 of cmmd + return data

Yes

0..0xFF

3 bytes

Error bit fieldsError flags for all

0x0B

134th return byte is CRC-8 of cmmd + return data

Yes

0..0xFF

3 bytes

Sends back all key detect status bits (bitfield)Report all keys

0x07

Bit 7: 1= indicates 2 or more touches if set.

Bit 6: 1= any of the following conditions prevail: calibrating, key(s)

failed cal 5 times, sync fail, comms error, FMEA failure.

Bit 5: Unused

Bits 4..0: indicates key number (0..23) of first key touched; reads

0x1F (31 decimal) if no touch.

2nd return byte is CRC-8 of cmmd + return data

Yes0..0xFF

21Get indication of first touched key + othersReport 1st key

0x06

Bit 7: reserved

Bit 6: 1= comms error: unrecognized command received

This bit can be reset by the 0x0F cmmd

Bit 5: 1= FMEA failure

Bit 4: 1= Reserved

Bit 3: 1= line sync failure

Bit 2: 1= cal failed 5 times on an enabled key, or, an enabled key has

a low reference (Ref < LSL)

Bit 1: 1= any key in calibration

Bit 0: 1= any key is in detect

2nd return byte is CRC-8 of cmmd + return data

Yes

0..0xFF21Get general part status.General status

0x05

Returns 1’s complement of command to acknowledge command prior

to reset. If 2 commands not received in 100ms, times out and no

response is issued.

-0xFB12

Force device to reset. Command must be

repeated 2x consecutively without any

intervening command in 100ms to execute

Force reset

0x04

Returns 1’s complement of command to acknowledge cmd once the

cal has been initiated.

If 2 commands not received in 100ms, times out and no response is

issued.

-0xFC12

Force device to recalibrate all keys; re-enters

RUN mode afterwards automatically; 0x03 must

be repeated 2x consecutively without any

intervening command in 100ms to execute

CAL all

0x03

First 0xFE issued when ready to get data, second 0xFE issued when

all loaded and burned; else timeout.

If 2 commands not received in 100ms, times out and no response is

issued. Part will timeout if each byte not received within 100ms of

previous byte.

If CRC failure, returns 0x00 instead of 0xFE

Data block length is 100 + 1 (added +1 byte is CRC-8). LSL should be

sent low byte first. A CRC of 0x00 is also acceptable in which

case the CRC is not checked.

The internal EEPROM will be programmed regardless of CRC health.

0xFE

+ 0xFE

0xFE

+ 0x00 (err)

+100

Enter Setups, stop sensing; followed by block

load of binary Setups of length ‘nn’. Command

must be repeated 2x consecutively without any

intervening command in 100ms to execute.

Sensing auto-restarts, however, the device

should be reset after the block load to ensure all

new setups will take effect.

Enter Setups

mode

0x01

Flushes pending data from QT; one required to extract each response

byte.

-0..0xFF11

Used to get data back in SPI modeNull command

0x00

Page

NotesCRCRtn range# Rtnd#/CmdDescriptionNameHex

Table 4.2 Command Summary

16 QT60248-AS R4.02/0405

Used in Run mode. Normal sensing of other keys not affected.

CAL of ‘k’ only takes place in the key’s normal timeslot.

Returns the ones compliment of the cmd char, once the cal is

scheduled.

~0xCk

Force calibration of key # k where k= 0..23.

Command must be repeated 2x consecutively

without any intervening command in 100ms to

execute

CAL key ‘k’

0xCk

Bits 7..5: reserved

Bit 4: 1= key is enabled

Bit 3: 1= key is in detect

Bit 2: 1= (Ref < LSL), even on a disabled key

Bit 1: 1= key is in calibration

Bit 0: 1= calibration of this key failed 5 times

Second return byte is CRC of cmmd + return data

Yes0..0xFF21Get status byte for key ‘k’ {0..23}Status for key ‘k’

0x8k

Diagnostic use only, not to be relied upon (no CRC). Signal and

ref are Tx as 2 bytes, LSB first.

0..0xFF

Each byte

Get signal, ref, Norm DI for key k {0..23}

Signal: 2 bytes; Ref: 2 bytes; Norm DI: 1

byte

Data for 1 key

0x4k

Returns 1’s compliment of last command even if bad. Resets the

communications error flag.

-0..0xFF11Returns last command received

Return last

cmmd

0x0F

CRC-8 only on Setups array section of eeprom

This CRC is the same as the CRC at the end of Setups block load.

Yes0..0xFF11Get eeprom CRCEeprom CRC

0x0E

100 block data bytes + 1 CRC byte returned.Yes

0..0xFF

Each byte

1001

Returns Setups block area followed by CRC.

Scanning is halted and then auto-restarted

after the cmd has completed.

Dump Setups

0x0D

Page

NotesCRCRtn range# Rtnd#/CmdDescriptionNameHex

17 QT60248-AS R4.02/0405

5 Setups

The devices calibrate and process all signals using a

number of algorithms specifically designed to provide for

high survivability in the face of adverse environmental

challenges. They provide a large number of processing

options which can be user-selected to implement very

flexible, robust keypanel solutions.

User-defined Setups are employed to alter these algorithms

to suit each application. These setups are loaded into the

device in a block load over the serial interface. The Setups

are stored in an onboard eeprom array. After a setups block

load, the device should be reset to allow the new Setups

parameters to take effect. This reset can be either a

hardware or software reset.

Refer to Table 5.1, page 22 for a table of all Setups.

Block length issues: The setups block is 100 bytes long to

accommodate 24 keys. This can be a burden on smaller host

controllers with limited memory. In larger quantities the

devices can be procured with the setups block

preprogrammed from Quantum. If the application only

requires a small number of keys (such as 16) then the

setups table can be compressed in the host by filling large

stretches of the Setups area with nulls.

Many setups employ lookup-table value translation. The

Setups Block Summary on page 23 shows all translation

values.

Default Values shown are factory defaults.

5.1 Negative Threshold - NTHR

The negative threshold value is established relative to a

key’s signal reference value. The threshold is used to

determine key touch when crossed by a negative-going

signal swing after having been filtered by the detection

integrator. Larger absolute values of threshold desensitize

keys since the signal must travel farther in order to cross the

threshold level. Conversely, lower thresholds make keys

more sensitive.

As Cx and Cs drift, the reference point drift-compensates for

these changes at a user-settable rate; the threshold level is

recomputed whenever the reference point moves, and thus it

also is drift compensated.

The amount of NTHR required depends on the amount of

signal swing that occurs when a key is touched. Thicker

panels or smaller key geometries reduce ‘key gain’, ie signal

swing from touch, thus requiring smaller NTHR values to

detect touch.

The negative threshold is programmed on a

per-key basis using the Setup process. See table,

page 23.

Negative hysteresis: NHYST is fixed at 12.5% of

the negative threshold value and cannot be

altered

Typical values: 3 to 8

(7 to 12 counts of threshold; 4 is internally

added to NTHR to generate the threshold).

Default value:

(10 counts of threshold)

5.2 Positive Threshold - PTHR

The positive threshold is used to provide a mechanism for

recalibration of the reference point when a key's signal

moves abruptly to the positive. This condition is not normal,

and usually occurs only after a recalibration when an object

is touching the key and is subsequently removed. The desire

is normally to recover from these events quickly.

Positive hysteresis: PHYST is fixed at 12.5% of the positive

threshold value and cannot be altered.

Positive threshold levels are all fixed at 6 counts of signal

and cannot be modified.

5.3 Drift Compensation - NDRIFT, PDRIFT

Signals can drift because of changes in Cx and Cs over time

and temperature. It is crucial that such drift be compensated,

else false detections and sensitivity shifts can occur.

Drift compensation (Figure 5-1) is performed by making the

reference level track the raw signal at a slow rate, but only

while there is no detection in effect. The rate of adjustment

must be performed slowly, otherwise legitimate detections

could be ignored. The devices drift compensate using a

slew-rate limited change to the reference level; the threshold

and hysteresis values are slaved to this reference.

When a finger is sensed, the signal falls since the human

body acts to absorb charge from the cross-coupling between

X and Y lines. An isolated, untouched foreign object (a coin,

or a water film) will cause the signal to rise very slightly due

to an enhancement of coupling. This is contrary to the way

most capacitive sensors operate.

Once a finger is sensed, the drift compensation mechanism

ceases since the signal is legitimately detecting an object.

Drift compensation only works when the signal in question

has not crossed the negative threshold level.

The drift compensation mechanism can be asymmetric; the

drift-compensation can be made to occur in one direction

faster than it does in the other simply by changing the

NDRIFT Setup parameter. This can be done on a per-key

basis.

The PDRIFT parameter is fixed at 0.4 seconds per count of

reference drift.

Specifically, drift compensation should be set to compensate

faster for increasing signals than for decreasing signals.

Decreasing signals should not be compensated quickly,

since an approaching finger could be compensated for

partially or entirely before even touching the touch pad.

18 QT60248-AS R4.02/0405

Figure 5-1 Thresholds and Drift Compensation

Threshold

Signal

Hysteresis

Reference

Output

However, an obstruction over the sense pad, for which the

sensor has already made full allowance for, could suddenly

be removed leaving the sensor with an artificially suppressed

reference level and thus become insensitive to touch. In this

latter case, the sensor should compensate for the object's

removal by raising the reference level relatively quickly.

Drift compensation and the detection time-outs work together

to provide for robust, adaptive sensing. The time-outs

provide abrupt changes in reference calibration depending

on the duration of the signal 'event'.

NDRIFT Typical values:

9 to 11

(2 to 3.3 seconds per count of drift compensation)

NDRIFT Default value:

(2.5s / count of drift compensation)

PDRIFT Fixed value:

0.4 secs

Note: This value cannot be altered and does not appear

in the Setups block.

5.4 Detect Integrators - NDIL, FDIL

NDIL is used to enable or disable keys and to provide signal

filtering. To enable a key, its NDIL parameter should be

non-zero (ie NDIL=0 disables a key). See Section 2.2.

To suppress false detections caused by spurious events like

electrical noise, the device incorporates a 'detection

integrator' or DI counter mechanism that acts to confirm a

detection by consensus (all detections in sequence must

agree). The DI mechanism counts sequential detections of a

key that appears to be touched, after each burst for the key.

For a key to be declared touched, the DI mechanism must

count to completion without even one detection failure.

The DI mechanism uses two counters. The first is the ‘fast

DI’ counter FDIL. When a key’s signal is first noted to be

below the negative threshold, the key enters ‘fast burst’

mode. In this mode the burst is rapidly repeated for up to the

specified limit count of the fast DI counter. Each key has its

own counter and its own specified fast-DI limit (FDIL), which

can range from 1 to 15. When fast-burst is entered the QT

device locks onto the key and repeats the acquire burst until

the fast-DI counter reaches FDIL, or, the detection fails

beforehand. After this the device resumes normal

keyscanning and goes on to the next key.

The ‘Normal DI’ counter counts the number of times the

fast-DI counter reached its FDIL value. The Normal DI

counter can only increment once per complete scan of all

keys. Only when the Normal DI counter reaches NDIL does

the key become formally ‘active’.

The net effect of this is that the sensor can rapidly lock onto

and confirm a detection with many confirmations, while still

scanning other keys. The ratio of ‘fast’ to ‘normal’ counts is

completely user-settable via the Setups process. The total

number of required confirmations is equal to FDIL times

NDIL.

If FDIL = 5 and NDIL = 2, the total detection confirmations

required is 10, even though the device only scanned through

all keys only twice.

The DI is extremely effective at reducing false detections at

the expense of slower reaction times. In some applications a

slow reaction time is desirable; the DI can be used to

intentionally slow down touch response in order to require

the user to touch longer to operate the key.

If FDIL = 1, the device functions conventionally; each

channel acquires only once in rotation, and the normal detect

integrator counter (NDIL) operates to confirm a detection.

Fast-DI is in essence not operational.

If FDIL m 2, then the fast-DI counter also operates in addition

to the NDIL counter.

If Signal [ NThr: The fast-DI counter is incremented towards

FDIL due to touch.

If Signal >NThr then the fast-DI counter is cleared due to

lack of touch.

Disabling a key: If NDIL =0, the key becomes disabled.

Keys disabled in this way are pared from the burst sequence

in order to improve sampling rates and thus response time.

See Section 2.2, page 3.

NDIL Typical values:

2, 3

NDIL Default value:

FDIL Typical values:

4 to 6

FDIL Default value:

5.5 Negative Recal Delay - NRD

If an object unintentionally contacts a key resulting in a

detection for a prolonged interval it is usually desirable to

recalibrate the key in order to restore its function, perhaps

after a time delay of some seconds.

The Negative Recal Delay timer monitors such detections; if

a detection event exceeds the timer's setting, the key will be

automatically recalibrated. After a recalibration has taken

place, the affected key will once again function normally

even if it is still being contacted by the foreign object. This

feature is set on a per-key basis using the NRD setup

parameter.

NRD can be disabled by setting it to zero (infinite timeout) in

which case the key will never auto-recalibrate during a

continuous detection (but the host could still command it).

NRD is set using one byte per key, which can range in value

from 0..254. NRD above 0 is expressed in 0.5s increments.

Thus if NRD =120, the timeout value will actually be 60

seconds. 255 is not a legal number to use.

NRD Typical values:

20 to 60 (10 to 30 seconds)

NRD Default value:

20 (10 seconds)

NRD Range:

0..254 (∞, 0.5 .. 127s)

5.6 Positive Recalibration Delay - PRD

A recalibration occurs automatically if the signal swings more

positive than the positive threshold level. This condition can

occur if there is positive drift but insufficient positive drift

compensation, or, if the reference moved negative due to a

NRD auto-recalibration, and thereafter the signal rapidly

returned to normal (positive excursion).

As an example of the latter, if a foreign object or a finger

contacts a key for period longer than the Negative Recal

Delay (NRD), the key is by recalibrated to a new lower

reference level. Then, when the condition causing the

negative swing ceases to exist (e.g. the object is removed)

the signal suddenly swings positive to its normal reference.

It is almost always desirable in these cases to cause the key

to recalibrate quickly so as to restore normal touch

operation. The time required to do this is governed by PRD.

In order for this to work, the signal must rise through the

positive threshold level PTHR continuously for the PRD

period.

19 QT60248-AS R4.02/0405

After the PRD interval has expired and the auto- recalibration

has taken place, the affected key will once again function

normally. PRD is fixed at 1 second for all keys, and cannot

be altered.

5.7 Burst Length - BL

The signal gain for each key is controlled by circuit

parameters as well as the burst length.

The burst length is simply the number of times the

charge-transfer (‘QT’) process is performed on a given key.

Each QT process is simply the pulsing of an X line once, with

a corresponding Y line enabled to capture the resulting

charge passed through the key’s capacitance Cx.

QT60xx8 devices use a fixed number of QT cycles which are

executed in burst mode. There can be up to 64 QT cycles in

a burst, in accordance with the list of permitted values shown

in Table 5.3.

Increasing burst length directly affects key sensitivity. This

occurs because the accumulation of charge in the charge

integrator is directly linked to the burst length. The burst

length of each key can be set individually, allowing for direct

digital control over the signal gains of each key individually.

Apparent touch sensitivity is also controlled by the Negative

Threshold level (NTHR). Burst length and NTHR interact;

normally burst lengths should be kept as short as possible to

limit RF emissions, but NTHR should be kept above 6 to

reduce false detections due to external noise. The detection

integrator mechanism also helps to prevent false detections.

BL Typical values:

2, 3 (48, 64 pulses / burst)

BL Default value:

2 (48 pulses / burst)

BL possible values:

16, 32, 48, 64

5.8 Adjacent Key Suppression - AKS

These devices incorporate adjacent key suppression (‘AKS’ -

patent pending) that can be selected on a per-key basis.

AKS permits the suppression of multiple key presses based

on relative signal strength. This feature assists in solving the

problem of surface moisture which can bridge a key touch to

an adjacent key, causing multiple key presses. This feature

is also useful for panels with tightly spaced keys, where a

fingertip might inadvertently activate an adjacent key.

AKS works for keys that are AKS-enabled anywhere in the

matrix and is not restricted to physically adjacent keys; the

device has no knowledge of which keys are actually

physically adjacent. When enabled for a key, adjacent key

suppression causes detections on that key to be suppressed

if any other AKS-enabled key in the panel has a more

negative signal deviation from its reference.

This feature does not account for varying key gains (burst

length) but ignores the actual negative detection threshold

setting for the key. If AKS-enabled keys in a panel have

different sizes, it may be necessary to reduce the gains of

larger keys relative to smaller ones to equalize the effects of

AKS. The signal threshold of the larger keys can be altered

to compensate for this without causing problems with key

suppression.

Adjacent key suppression works to augment the natural

moisture suppression of narrow gated transfer switches

creating a more robust sensing method.

AKS Default value:

0 (Off)

5.9 Oscilloscope Sync - SSYNC

Pin 11 (S_Sync) can output a positive pulse oscilloscope

sync that brackets the burst of a selected key. More than one

burst can output a sync pulse as determined by the Setups

parameter SSYNC for each key.

The SSYNC function does not become effective until the part

has been reset, or the desired key(s) are recalibrated.

This feature is invaluable for diagnostics; without it,

observing signals clearly on an oscilloscope for a particular

burst is very difficult.

This function is supported in Quantum’s QmBtn PC software.

SSYNC Default value:

0 (Off)

5.10 Mains Sync - MSYNC

The MSync feature uses the SYNC pin.

External fields can cause interference leading to false

detections or sensitivity shifts. Most fields come from AC

power sources. RFI noise sources are heavily suppressed

by the low impedance nature of the QT circuitry itself.

Noise such as from 50Hz or 60Hz fields becomes a problem

if it is uncorrelated with acquisition signal sampling;

uncorrelated noise can cause aliasing effects in the key

signals. To suppress this problem the SYNC input allows

bursts to synchronize to the noise source.

The noise sync operating mode is set by parameter MSYNC

in Setups.

The sync occurs only at the burst for the lowest numbered

enabled key in the matrix; the device waits for the sync

signal for up to 100ms after the end of a preceding full matrix

scan, then when a negative sync edge is received, the matrix

is scanned in its entirety again.

The sync signal drive should be a buffered logic signal, but

never a raw AC signal from the mains; slow or erratic edges

on MSYNC can cause the device to sync on the wrong edge,

or both edges. The device should only sync to the falling

edge.

Since Noise sync is highly effective and inexpensive to

implement, it is strongly advised to take advantage of it

anywhere there is a possibility of encountering low frequency

(i.e. 50/60Hz) electric fields. Quantum’s QmBtn software can

show such noise effects on signals, and will hence assist in

determining the need to make use of this feature.

If the sync feature is enabled but no sync signal exists, the

sensor will continue to operate but with a delay of 100ms

from the end of one scan to the start of the next, and hence

will have a slow response time. A failed Sync signal (one

exceeding a 100ms period) will cause an error flag (see

commands 0x05, 0x06).

MSYNC Default value:

0 (Off

)

MSYNC Possible range:

0, 1 (Off, On)

5.11 Burst Spacing - BS

The interval of time from the start of one burst to the start of

the next is known as the burst spacing. This is an alterable

parameter which affects all keys. The burst spacing can be

viewed as a scheduled timeslot in which a burst occurs. This

approach results in an orderly and predictable sequencing of

key scanning with predictable response times.

20 QT60248-AS R4.02/0405

Shorter spacings result in a faster response time to touch;

longer spacings permit higher burst lengths and longer

conversion times but slow down response time.

BS Default value:

1 (500µs)

BS Possible range:

1..11 (500µs .. 3ms)

5.12 Lower Signal Limit - LSL

This Setup determines the lowest acceptable value of signal

level for all keys. If any key’s reference level falls below this

value, the device declares an error condition in the status

bits.

Testing is required to ensure that there are adequate

margins in this determination. Key size, shape, panel

material, and burst length all factor into the detected signal

levels.

This parameter occupies 2 bytes of the setups table. The low

order byte should be sent first.

LSL Default value:

100

LSL Possible range:

0..2047

5.13 Host CRC - HCRC

The setups block terminates with a 8-bit CRC, HCRC, of the

entire block. The formulae for calculating this CRC is shown

in Section 7.

21 QT60248-AS R4.02/0405

Table 5.1 Setups Block

Setups data is sent from the host to the QT in a block of hex data. The block can only be loaded in Setups mode following two se quential 0x01 commands (page 12). All

devices this datasheet pertain to have the same block length. Refer also to Table 5.3, page 23 for further details, and all of Section 5.

101Block length

21--80..2551HCRCHost CRC byte1008

Lower limit of acceptable signal; below this value, device declares an error.

The low order byte should be sent first.

10024160..20482LSLLower signal Limit987

20Lower nibble = burst spacing1244BS = 0..111BSBurst spacing976

20Bit 6 = Mains sync, negative edge, 1 = enabled; default = 0 (off)0241MSYNC = 0, 11MSYNCMains Sync965

Bits 5, 4: = BL, via LUT, default = 48 (setting =2)

Bit 6 = AKS, 1 - enabled

Bit 7 = Scope sync, 1 = enabled

BL = 0, 1, 2, 3

AKS = 0, 1

SSYNC = 0, 1

AKS

SSYNC

Burst Length

AKS

Scope Sync

724

Range is in 0.5 sec increments; 0 = infinite; default = 10s (operand = 20)

Range is { infinite, 0.5...127s }; 255 is illegal to use

20180..25424NRDNeg recal delay483

Lower nibble = Normal DI Limit, values same as operand (0 = disables key)

Upper nibble = Fast DI Limit, values same as operand (0 does not work)

NDIL = 0..15

FDIL = 0..15

NDIL

FDIL

Normal DI Limit

Fast DI Limit

242

Lower nibble = Neg Threshold - take operand and add 4 to get value

Upper nibble = Neg Drift comp - Via LUT

NTHR = 0..15

NDRIFT = 0..15

NTHR

NDRIFT

Neg thresh

Neg Drift Comp

Page

Description

Default

Value

Key

Scope

BitsValid rangeBytesSymbolParameterByte

Item

CRC Note: A CRC calculator for Windows is available free of charge from Quantum Research on request.

Table 5.2 Key Mapping

Some commands return bitfields related to keys. For example, command 0x07 (report all keys) returns 3 bytes containing flag bits, one per key, to indicate which keys are reporting

touches. The following table shows the byte and bit order of the keys. The table contains the key number reported in each bit.

The key number is related to the X and Y scan lines which address each particular key. Each byte in the return stream represents one set of keys along a Y line, ie up to 8 keys.

Thus, key 0 is at location X0,Y0 and key 19 is at location X3,Y2. .

Note: Byte 0 is returned first.

22 QT60248-AS R4.02/0405

1617181920212223

89101112131415

01234567

Byte

(Y line)

01234567

Bit

(X line)

Table 5.3 Setups Block Summary

Typical values: For most touch applicatio

ns, use the values shown in the outlined cells. Bold text items indicate

default settings. The number to send to the QT is the number in

the leftmost column (0..15), not numbers from within the table. The QT uses lookup tables to translate the 0..15 to the parameters for each function.

NRD is an exception: It can range from 0..254 which is translated from 1= 0.5s to 254= 127s with zero = infinity.

15151019

14147.51814

13136

12124.51612

3,000µs11113.31511

2,750µs1010

- 2.5 -

2,500µs992139

2,250µs881.512

2,000µs771.2117

1,750µs661- 10 -6

1,500µs

- 5 -

50.89

1,250µs440.68

1,000µs64330.473

750µs

- 48 -

Default=

10s

- 2 -

0.36

- 500µs -

OnOnOn320.5 .. 127s110.25

unused- Off -- Off -- Off -160 (Infinite)unusedKey off0.140

GlobalGlobalPer keyPer keyPer keyPer keyPer keyPer keyPer keyPer key

BSMSYNCScope SyncAKS

pulses

NRD

secs

FDIL

countsNDIL counts

NDRIFT

secs

NTHR

counts

Parameter

Index Number

23 QT60248-AS R4.02/0405

6 Specifications

6.1 Absolute Maximum Electrical Specifications

Operating temp.................................................................... -40

C to +105

Storage temp......................................................................-55

C to +125

..................................................................................-0.5 to +5.5V

Max continuous pin current, any control or drive pin............................................. ±10mA

Short circuit duration to ground, any pin........................................................ infinite

Short circuit duration to V

, any pin........................................................... infinite

Voltage forced onto any pin.................................................. -0.6V to (Vdd + 0.6) Volts

Eeprom setups maximum writes.................................................. 100,000 write cycles

6.2 Recommended operating conditions

................................................................................ +3.0V to 5.25V

Supply ripple+noise................................................................... 5mV p-p max

Cx transverse load capacitance per key..................................................... 0 to 20pF

6.3 DC Specifications

Vdd = 5.0V, Cs = 4.7nF, Rs = 470K; Ta = recommended range, unless otherwise noted

k✡8030Internal /RST pullup resistorRrst

DRDY, /SS pinsk✡50 20Internal pullup resistorsRp

bits119Acquisition resolutionAr

µA±1Input leakage currentIil

1mA sourceVVdd-0.7High output voltageVoh

4mA sinkV0.6Low output voltageVol

V2.2High input logic levelVhl

V0.8Low input logic levelVil

V2.92.7 Vdd internal reset voltageVr

Excluding external componentsmA25Supply current, runningIddr

NotesUnitsMaxTypMinDescriptionParameter

6.4 Timing Specifications

Max guaranteed is a min of 1.5MHzMHz1.5SPI Clock rateFck

SPI parameter controlled by hostns667CLK periodS9

SPI parameter controlled by hostns333CLK high pulse widthS8

SPI parameter controlled by hostns333CLK low pulse widthS7

SPI parameter controlled by QTµs1DRDY low pulse widthS6

SPI parameter controlled by QTµs40Ç /SS to falling DRDYS5

SPI parameter controlled by QTns20Ç /SS to 3-state MISOS4

SPI parameter controlled by hostns25Last Ç CLK to Ç /SSS3

SPI parameter controlled by QTns20È CLK to valid MISOS2

SPI parameter controlled by hostns333È /SS to first È CLK edgeS1

%±8Burst modulation, percentFm

kHz226Burst center frequencyFc

Adjustable parameter via Setupsµs3,000500Burst spacingT

NotesUnitsMaxTypMinDescriptionParameter

24 QT60248-AS R4.02/0405

6.5 Mechanical Dimensions

6.6 Marking

25 QT60248-AS R4.02/0405

11109

32 31 30 28

25262729

12 14 16

15 17

SYMBOL

Millimeters Inches

Min Max Notes Min Max Notes

9.25 8.75 0.344 0.354

0.09 0.20 0.003 0.008

0.45

0.05

0.75

0.15

1.20

0.018

0.002

0.030

0.006

0.047

0.80

0.30

BSC0.80

0.45

0.031

0.012

BSC0.031

0.018

6.90 7.10 0.272 0.280

o07 07

SQSQ

Package Type: 32 Pin TQFP

YesQT60248-AG24QT60248-ASG-40

C to +105

YesQT60168-AG16QT60168-ASG-40

C to +105

Lead-FreeMarkingKeys

TQFP Part

NumberT

7 Appendix

7.1 8-Bit CRC Algorithm

// 8 bits crc calculation. Initial value is 0.

// polynomial = X

+ X

+ 1

// data is an 8 bit number; crc is a 8 bit number

unsigned char eight_bit_crc(unsigned char crc, unsigned char data)

{ unsigned char index; // shift counter

unsigned char fb;

index = 8; // initialise the shift counter

{ fb = (crc ^ data) & 0x01;

data >>= 1;

crc >>= 1;

If(fb)

{ crc ^= 0x8c;

}

} while(--index);

return crc;

}

A CRC calculator for Windows is available free of charge from Quantum Research.

26 QT60248-AS R4.02/0405

7.2 1-Sided Key Layout

This key design can be made on a 1-sided SMT PCB. A single 0-ohm jumper

allows the wiring to be done on a single side with full pass-through of X and Y

traces to allow matrix connections to be made across a large number of keys.

Key size, shape, and number of interleavings can be varied substantially from

this drawing. The below drawing shows 6 interleave white spaces; only a

double interleave is required in the case of smaller keys.

The PCB is bonded to a panel on its underside, and the fields fire through the

PCB, adhesive, and panel in that sequence. This results in a very low cost

design.

7.3 PCB Layout

Shown is an example PCB layout using inexpensive 1-sided CEM-1 or FR-1 PCB laminate. The key layouts follow the design

rules shown above. (PCB design shown uses a QT60326 chip but still represents a good example).

27 QT60248-AS R4.02/0405

0-ohm SMT Jumper

Patented and patents pending

Corporate Headquarters

1 Mitchell Point

Ensign Way, Hamble SO31 4RF

Great Britain

Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939

www.qprox.com

North America

651 Holiday Drive Bldg. 5 / 300

Pittsburgh, PA 15220 USA

Tel: 412-391-7367 Fax: 412-291-1015

This device covered under one or more of the following United States and international patents: 5,730,165, 6,288,707, 6,377,009, 6,452,514,

6,457,355, 6,466,036, 6,535,200. Numerous further patents are pending which may apply to this device or the applications thereof.

The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject

to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order

acknowledgement. QProx, QTouch, QMatrix, QLevel, QSlide, and QWheel are trademarks of QRG. QRG products are not suitable for

medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in

QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in

connection with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers

are entirely responsible for their products and applications which incorporate QRG's products.

Development Team: Dr. Tim Ingersoll, Samuel Brunet, Hal Philipp