ISSI IS61C1024 IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM (R) MAY 1999 FEATURES DESCRIPTION * High-speed access time: 12, 15, 20, 25 ns * Low active power: 600 mW (typical) * Low standby power: 500 W (typical) CMOS standby * Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 5V (10%) power supply * Low power version available: IS61C1024L * Commercial and industrial temperature ranges available The ISSI IS61C1024 and IS61C1024L are very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C1024 and IS61C1024L are available in 32-pin 300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I, 8 x 13.4) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 x 2048 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE1 CE2 OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1999, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 1 ISSI IS61C1024 IS61C1024L PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H) NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (R) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vcc Power GND Ground OPERATING RANGE Range Commercial Ambient Temperature 0C to +70C VCC 5V 10% -40C to +85C 5V 10% Industrial TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write 2 WE CE1 CE2 OE X X H H L H X L L L X L H H H X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1J 11/03/98 ISSI IS61C1024 IS61C1024L (R) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -55 to +125 -65 to +150 1.5 20 Unit V C C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 5 pF VOUT = 0V 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA 2.4 -- V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA -- 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.5 V -0.3 0.8 V (1) VIL Input LOW Voltage ILI Input Leakage GND VIN VCC Com. Ind. -2 -5 2 5 A ILO Output Leakage GND VOUT VCC Outputs Disabled Com. Ind. -2 -5 2 5 A Note: 1. VIL = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 3 ISSI IS61C1024 IS61C1024L (R) IS61C1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -12 ns Min. Max. -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Symbol Parameter Test Conditions ICC1 Vcc Operating Supply Current VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = 0 Ind. -- -- 85 110 -- -- 85 110 -- -- 85 110 -- -- 85 110 mA ICC2 Vcc Dynamic Operating Supply Current VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = fMAX Ind. -- -- 170 180 -- -- 160 170 -- -- 150 160 -- -- 140 150 mA ISB1 TTL Standby Current (TTL Inputs) VCC = VCC MAX., VIN = VIH or VIL CE1 VIH, f = 0 or CE2 VIL, f = 0 Com. Ind. -- -- 40 60 -- -- 40 60 -- -- 40 60 -- -- 40 60 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = VCC MAX., Com. Ind. -- -- 30 40 -- -- 30 40 -- -- 30 40 -- -- 30 40 mA CE1 VCC - 0.2V, CE2 0.2V VIN > VCC - 0.2V, or VIN 0.2V, f = 0 Unit Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IS61C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Symbol Parameter Test Conditions ICC1 Vcc Operating Supply Current VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = 0 Ind. -- -- 85 110 -- -- 85 110 -- -- 85 110 mA ICC2 Vcc Dynamic Operating Supply Current VCC = VCC MAX., CE = VIL Com. IOUT = 0 mA, f = fMAX Ind. -- -- 160 170 -- -- 150 160 -- -- 140 150 mA ISB1 TTL Standby Current (TTL Inputs) VCC = VCC MAX, VIN = VIH or VIL CE1 VIH, f = 0 or CE2 VIL, f = 0 Com. Ind. -- -- 40 60 -- -- 40 60 -- -- 40 60 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = VCC MAX., Com. Ind. -- -- 500 750 -- -- 500 750 -- -- 500 750 A CE1 VCC - 0.2V, CE2 0.2V VIN > VCC - 0.2V, or VIN 0.2V, f = 0 Unit Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1J 11/03/98 ISSI IS61C1024 IS61C1024L (R) READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -12(2) Min. Max. Parameter -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit tRC Read Cycle Time 12 -- 15 -- 20 -- 25 -- ns tAA Address Access Time -- 12 -- 15 -- 20 -- 25 ns tOHA Output Hold Time 3 -- 3 -- 3 -- 3 -- ns tACE1 CE1 Access Time -- 12 -- 15 -- 20 -- 25 ns tACE2 CE2 Access Time -- 12 -- 15 -- 20 -- 25 ns tDOE OE Access Time -- 6 -- 7 -- 9 -- 9 ns OE to Low-Z Output 0 -- 0 -- 0 -- 0 -- ns tHZOE(3) OE to High-Z Output 0 6 0 6 0 7 0 10 ns tLZCE1(3) CE1 to Low-Z Output 2 -- 2 -- 3 -- 3 -- ns tLZCE2 CE2 to Low-Z Output 2 -- 2 -- 3 -- 3 -- ns CE1 or CE2 to High-Z Output 0 7 0 8 0 9 0 10 ns tPU(4) CE1 or CE2 to Power-Up 0 -- 0 -- 0 -- 0 -- ns tPD(4) CE1 or CE2 to Power-Down -- 12 -- 12 -- 18 -- 20 ns tLZOE (3) tHZCE (3) (3) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. -12 ns device for IS61C1024 only. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 4. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 480 5V 5V OUTPUT OUTPUT 30 pF Including jig and scope 255 Figure 1 Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 5 pF Including jig and scope 255 Figure 2 5 ISSI IS61C1024 IS61C1024L (R) AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE1 CE2 t ACE1 t ACE2 t LZCE1 t LZCE2 DOUT HIGH-Z t HZCE1 t HZCE2 DATA VALID CE2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1J 11/03/98 ISSI IS61C1024 IS61C1024L (R) WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) Symbol Parameter -12 ns(3) Min. Max. -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit tWC Write Cycle Time 12 -- 15 -- 20 -- 25 -- ns tSCE1 CE1 to Write End 10 -- 12 -- 15 -- 20 -- ns tSCE2 CE2 to Write End 10 -- 12 -- 15 -- 20 -- ns tAW Address Setup Time to Write End 10 -- 12 -- 15 -- 20 -- ns tHA Address Hold from Write End 0 -- 0 -- 0 -- 0 -- ns tSA Address Setup Time 0 -- 0 -- 0 -- 0 -- ns tPWE(4) WE Pulse Width 10 -- 10 -- 12 -- 15 -- ns tSD Data Setup to Write End 7 -- 8 -- 10 -- 12 -- ns Data Hold from Write End 0 -- 0 -- 0 -- 0 -- ns WE LOW to High-Z Output -- 7 -- 7 -- 10 -- 12 ns tLZWE(5) WE HIGH to Low-Z Output 2 -- 2 -- 2 -- 2 -- ns tHD tHZWE (5) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. -12 ns device for IS61C1024 only. 4. Tested with OE HIGH. 5. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 7 ISSI IS61C1024 IS61C1024L (R) AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA t HA CE1 CE2 t AW t PWE1 t PWE2 WE t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE2_WR1.eps WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE1 LOW HIGH CE2 t AW t PWE1 WE t HZWE t SA DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1J 11/03/98 ISSI IS61C1024 IS61C1024L (R) WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE1 LOW t HA HIGH CE2 t AW t PWE2 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR3.eps Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 9 ISSI IS61C1024 IS61C1024L IS61C1024 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0C to +70C IS61C1024 STANDARD VERSION ORDERING INFORMATION Industrial Range: -40C to +85C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 12 12 12 12 IS61C1024-12J IS61C1024-12K IS61C1024-12H IS61C1024-12T 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 12 12 12 12 IS61C1024-12JI IS61C1024-12KI IS61C1024-12HI IS61C1024-12TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 15 15 15 15 IS61C1024-15J IS61C1024-15K IS61C1024-15H IS61C1024-15T 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 15 15 15 15 IS61C1024-15JI IS61C1024-15KI IS61C1024-15HI IS61C1024-15TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 20 20 20 20 IS61C1024-20J IS61C1024-20K IS61C1024-20H IS61C1024-20T 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 20 20 20 20 IS61C1024-20JI IS61C1024-20KI IS61C1024-20HI IS61C1024-20TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 25 25 25 25 IS61C1024-25J IS61C1024-25K IS61C1024-25H IS61C1024-25T 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 25 25 25 25 IS61C1024-25JI IS61C1024-25KI IS61C1024-25HI IS61C1024-25TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) IS61C1024L LOW POWER VERSION ORDERING INFORMATION Commercial Range: 0C to +70C IS61C1024L LOW POWER VERSION ORDERING INFORMATION Industrial Range: -40C to +85C Speed (ns) Speed (ns) 10 Order Part No. Package 15 IS61C1024L-15JI IS61C1024L-15KI IS61C1024L-12HI IS61C1024L-15TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 20 IS61C1024L-20JI IS61C1024L-20KI IS61C1024L-12HI IS61C1024L-20TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 25 IS61C1024L-25JI IS61C1024L-25KI IS61C1024L-12HI IS61C1024L-25TI 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) Order Part No. Package 15 IS61C1024L-15J IS61C1024L-15K IS61C1024L-15H IS61C1024L-15T 300-mil Plastic SOJ 400-mil Plastic SOJ sTSOP (Type I) TSOP (Type I) 20 IS61C1024L-20J IS61C1024L-20K IS61C1024L-20H IS61C1024L-20T 25 IS61C1024L-25J IS61C1024L-25K IS61C1024L-25H IS61C1024L-25T (R) Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1J 11/03/98 IS61C1024 IS61C1024L ISSI ISSI (R) (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. -- 1-800-379-4774 SR028-1K 05/12/99 11