IS42VM32200G
512K x32Bits x4Banks Low Power Synchronous DRAM
Description
These IS42VM32200G are Low Power 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and
output voltage levels are compatible with LVCMOS.
JEDEC standard 1.8V power supply.
• Auto refresh and self refresh.
• All pins are compatibl e with LVCMOS interface.
•4K refresh c
y
cle
/
64ms.
• All inputs and outputs referenced to the positiv e edge of the
system clock.
• Data mask function by DQM.
•
Internal 4 banks operation
Features
y/
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
•
Deep Power Down Mode
•
Internal
4
banks
operation
.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
•
Deep
Power
Down
Mode
.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, prod ucts or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
SS ff f f
1
www.issi.com - DRAM@issi.com
Rev. A | July 2010
Integrated
S
ilicon
S
olution, Inc. does not recommend the use o
f
any o
f
its products in li
f
e support applications where the
f
ailure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circ umstances
IS42VM32200G
Figure1: 90Ball FBGA Ball Assignment
1
2 3 456 7 8 9
DQ26 DQ24 DQ23 DQ21
DQ28 VDDQ VSSQ DQ19
VSSQ DQ27 DQ20 VDDQ
VSSQ DQ29 DQ18 VDDQ
A
B
C
D
VDD
VDDQ
DQ22
DQ17
VSS
VSSQ
DQ25
DQ30
1
2
3
4
5
6
7
8
9
VDDQ DQ31 DQ16 VSSQ
VSS DQM3 DQM2 VDD
A4 A5 A0 A1
A7 A8 BA1 NC
CLK CKE /CS /RAS
E
F
G
H
J
NC
A2
A10
NC
BA0
NC
A3
A6
NC
A9
DQM1 NC /WE DQM0
VDDQ DQ8 DQ7 VSSQ
VSSQ DQ10 DQ5 VDDQ
VSSQ DQ12 DQ3 VDDQ
D
Q
11 VDD
VSS
Q
D
Q
4
K
L
M
N
P
/CAS
VDD
DQ6
DQ1
VDDQ
NC
VSS
DQ9
DQ14
V
SSQ
[Top View]
Q
Q
Q
DQ13 DQ15 DQ0 DQ2
RVDD
SSQ
VSS
2
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table2: Pin Descriptions
Pin
Pin Name
Descriptions
Pin
Pin
Name
Descriptions
CLK System Clock The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CKE Clock Enable Controls internal clo ck signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/CS Chip Select Enable or disable all inputs except CLK, CKE and DQM.
BA0 BA1
BkAdd
Selects
ba
nk t
o
b
e
a
ctiv
a
te
d
du
rin
g
RAS
a
ctivit
y
.
BA0
~
BA1
B
an
k
Add
ress
ba o b a a d du g a y
Selects ba nk to be read/written during CAS activity.
A0~A10 Address Row Address : RA0~RA10
Column Address : CA0~CA7
Auto Precharge : A10
/RAS, /CAS, /WE Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
Ctl ttbff i d d d ki tdti
DQM0~DQM3 Data Input/Output Mask
C
on
t
ro
l
s ou
t
pu
t
b
u
ff
ers
i
n rea
d
mo
d
e an
d
mas
k
s
i
npu
t
d
a
t
a
i
n
write mode.
DQ0~DQ31 Data Input/Output Data input/output pin.
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection No connection.
3
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Figure2: Functional Block Diagram
BANK D
TCSR
CLOCK
GENERATOR
CLK
CKE
EXTENDED
MODE
REGISTER
BANK
D
ROW DECODER
BANK C
ROW DECODER
PASR
ROW
ADDRESS
BUFFER &
REFRESH
COUNTER
MODE
REGISTER
BANK B
ROW DECODER
BANK A
ROW DEC
O
ADDRESS
CONTROL
L
COMMAND D
E
COLUMN
ADDRESS
BUFFER &
COUNTER
/CS
/RAS
/
CAS
O
DER
SENSE AMPLIFIER
COLUMN DECODER
& LATCH CIRCUIT
L
OGIC
E
CODER
BURST
COUNTER
/
/WE
DATA CONTROL CIRCUIT
DQM LATCH CIRCUIT
INPUT & OUTPUT
DQ
INPUT
&
OUTPUT
BUFFER
4
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Figure3: Simplified State Diagram
SELF
REFRESH
EXTENDED
MODE
REGISTER
SET
IDLE CBR
REFRESH
POWER
DOWN
MODE
REGISTER
SET
ACT
REF
MRS
DEEP
POWER
DOWN
ROW
ACTIVE
DOWN
ACTIVE
POWER
DOWN
READ
WRITE
CKE ↓
CKE
PR
E
DOWN
CKE ↓
CKE READWRITE
READ AWRITE A
READ
SUSPEND
READ A
SUSPEND
WRITE
SUSPEND
WRITE A
SUSPEND
CKE ↓
CKE ↓
CKE
CKE ↓
READ
WRITE
E
SUSPEND
SUSPEND
CKE CKE
PRE-
CHARGE
POWER
ON PRECHARGE
5
www.issi.com - DRAM@issi.com
Rev. A | July 2010
Automatic Sequence
Manual Input
IS42VM32200G
A0A1A2A3A4A5A6A7A8A9A10
Figure4: Mode Register Definition
BA0
BA1
WB0CAS Latency BT Burst Length
Address Bus
01234561098711 Mode Register (Mx)
00
0
0
12
M9 Write Burst Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
M3 Burst Type
0Sequential
1Interleave
M6 M5 M4 CAS Latency
000 Reserved
001 -
010 2
011 3
100 Reserved
101 Reserved
1
1
0
Reserved
M2 M1 M0 Burst Length
M3 = 0 M3 = 1
000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserved Reserved
1
0
1
Reserved
Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
add ess
as
sho n
in
Table
3
1
1
0
Reserved
111 Reserved
1
0
1
Reserved
Reserved
1 1 0 Reserved Reserved
111Full PageReserved
Note: M12/ M1 1(BA1/BA0) must be set to “0/0” to select Mode Register (vs. the Extended Mode Register)
add
r
ess
,
as
sho
w
n
in
Table
3
.
Table 3: Burst Definition
Burst
Length
Starting Column
Address Order of Access Within a Burst
Sequential Interleaved
A2 A1 A0
200-1 0-1
11-0 1-0
Note :
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column within the
4
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
11 3-0-1-2 3-2-1-0
000
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
001
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0
1
0
2
-
3
-
4
-
5
-
6
-
7
-
0
-
1
2
-
3
-
0
-
1
-
6
-
7
-
4
-
5
block.
3. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A7 select the
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A7
8
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
011
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
100
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
101
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
110
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
111
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
n=A0
7
Cn, Cn+1. Cn+2,
selec
t
the startin
g
column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
6
www.issi.com - DRAM@issi.com
Rev. A | July 2010
Full
Page
n=A0
-
7
(Location 0-255) Cn+3, Cn+4…
…Cn-1, Cn... Not Supported
IS42VM32200G
Figure5: Extended Mode Register
A0A1A2A3A4A5A6A7A8A9A10
BA0
BA1
0PASR
Address Bus
Extended Mode Register (Ex)
01234561098711
0000 DS
1
12
0
0
E2 E1 E0 Self Refresh Coverage
0 0 0 All Banks
001Two Banks (BA1=0)
0 1 0 One Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
E6 E5 Driver Strength
00 Full Strength
0 1 1/2 Strength
1 0 1/4 Strength
11 Reserved
1 0 1 Half of One Bank (BA1=BA0=0, Row Address MSB=0)
1 1 0 Quarter of One Bank (BA1=BA0=0, Row Address 2 MSB=0)
1 1 1 Reserved
Note: E12/E11(BA 1/ BA0) must be set to “1/0” to sele ct Ex tend Mod e Re gister (vs. the base Mode Reg ister )
7
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
In general, this 64Mb SDRAM (512K x 32Bits x 4banks) is a multi-bank DRAM that operates at 1.8V and includes a synchronous
Functional Description
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as
2,048 rows by 256 columns by 32-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (BA0-BA1 select the bank, A0-A10 select the row). The address bits (BA0-BA1 select the bank, A0-A7 select the
column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Pi
t
l
ti
th
SDRAM
t
b
iitili d
Th
fll i
ti
id
dtild
if ti
i
di
P
r
i
or
t
onorma
l
opera
ti
on,
th
e
SDRAM
mus
t
b
e
i
n
iti
a
li
ze
d
.
Th
e
f
o
ll
ow
i
n
g
sec
ti
ons prov
id
e
d
e
t
a
il
e
d
i
n
f
orma
ti
on cover
i
n
g
d
ev
i
ce
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other
than
a
COMMAND
INHIBIT
or
NOP
CKE
must
be
held
high
during
the
entire
initialization
period
until
the
PRECHARGE
command
other
than
a
COMMAND
INHIBIT
or
NOP
.
CKE
must
be
held
high
during
the
entire
initialization
period
until
the
PRECHARGE
command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Onceintheidlestate,twoAUTOREFRESHcyclesmustbeperformed.AftertheAUTOREFRESHcyclesarecomplete,theSDRAMis
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying
any
operational
command
.
And
a
extended
mode
register
set
command
will
be
issued
to
program
specific
mode
of
self
applying
any
operational
command
.
And
a
extended
mode
register
set
command
will
be
issued
to
program
specific
mode
of
self
refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE
REGISTER
command
and
will
retain
the
stored
information
until
it
is
programmed
again
or
the
device
loses
power
MODE
REGISTER
command
and
will
retain
the
stored
information
until
it
is
programmed
again
or
the
device
loses
power
.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10-M11 should be set to zero. M12 should
be set to zero to prevent extended mode register.
Themoderegistermustbeloadedwhenallbanksareidle,andthecontroller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the BATRAM device. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command and retains the stored information until it is
programmed again or the device loses power.
TheExtendedModeRegistermustbeprogrammedwithM7throughM11setto“0”.TheExtendedModeRegistermustbeloadedwhen
all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation.
8
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst
length
determines
the
maximum
number
of
column
locations
that
can
be
accessed
for
a
given
READ
or
WRITE
command
Burst
length
determines
the
maximum
number
of
column
locations
that
can
be
accessed
for
a
given
READ
or
WRITE
command
.
Burst
lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when
the burs
t
len
g
th is se
t
to two
;
b
y
A2-A7 when the burs
t
len
g
th is se
t
to four
;
and b
y
A3-A7 when the burs
t
len
g
th is se
t
to ei
g
h
t
.
T
he
g
;
y
g
;
y
g
g
remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified ba nk of the device. This command is initia ted by activating CS,RAS and
deasserting CAS, WE at the positi ve edge of the clock. The value on the BA0-BA1 selects the bank, and the value on the A0-A10 selects
the row.
This row remains active for colum n access until a precharge command is issued to that bank. Read and write op erations can only be
initiated on this activated b ank after the mini m um tRCD time is passed from the activate command .
Read
The READ command is used to initiate the burst read of da ta. This command is initiated by activating CS, CAS, and deasserting WE, RAS at
the positive edge of the clock. BA0-BA1 input sele ct the bank, A0-A7 ad dress inputs select the starting column location. The value on input
A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the
end of the READ burst; if Auto Precharge is not sele ct ed, the row will remain activ e for subsequent acce s s es. The length of burst and the
CAS latenc y will be determined by the values programmed during the MR S command.
Write
The WRITE command is used to initiate the burst w rite of data. This command is initiated by activating CS, CAS, WE and deasserting RAS
at the positive edge of the clock BA0
-
BA1 input select the bank A0
-
A7 address inputs select the starting column location The
value on
at
the
positive
edge
of
the
clock
.
BA0
-
BA1
input
select
the
bank
,
A0
-
A7
address
inputs
select
the
starting
column
location
.
The
value
on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being acces sed wil l b e precharged at
the end of the WRI TE burst; if Auto Precharge is not selected, the row will remain active for subseque nt acce sse s.
9
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
d
h
l
b
h
lk
f
d
d
lk
d
d
h
l
outpu
t
d
ata.
Th
e
l
atency can
b
ese
t
to two or t
h
ree c
l
oc
k
s. I
f
aREADcomman
d
is re
g
istere
d
a
t
c
l
oc
k
e
dg
en,an
d
t
h
e
l
atency is
m
clocks, the data will be available by clock edge
n+
m. The DQs will start driving as a result of the clock edge one cycle earlier
(n + m
-
1), and provided that the relevant access times are met, the data will be valid by clock edge
n+
m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
CLK
COMMAND NOP NOP
T0 T1 T2 T3
READ
Figure6: CAS Latency
DQ Dout
tLZ tOH
tAC
CAS Latency=2
CLK
T0 T1 T2 T3 T4
CLK
COMMAND
DQ
NOP NOP
Dout
tLZ tOH
tAC
CAS Latency=3
NOPREAD
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
DON’T CARE
UNDEFINED
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
10
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table4: Command Truth Table
Function CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10 Note
Command Inhinit (NOP) H X H X X X X X
No Operation (NOP) H X L H H H X X
Mode Register Set H X L L L L X OP CODE 4
Extended Mode Reg ister Set H X L L L L X OP CODE 4
Active (select bank and
activate row) HXLLHHX Bank/Row
Read H X L H L H L/H Bank/Col L 5
Read with Autopr echarg e H X L H L H L/H Bank/Col H 5
Write H X L H L L L/H Bank/Col L 5
Write with Autoprecharge H X L H L L L/H Bank/Col H 5
Precharge All Banks H X L L H L X X H
Prechar
g
e Selected Bank H X L L H L X Bank L
g
Burst Stop H H L H H L X X
Auto Refresh H H L L L H X X 3
Self Refresh Entry H L L L L H X X 3
Self Refresh E xit L H HX X X XX2
LH H H
H
X
X
X
Precharge Power Down Entry H L
H
X
X
X
XX
LH H H
Precharge Down Exit L H HX X X XX
LH H H
Clock Suspend Entry H L HX X X XX
LV V V
Clock Suspend Exit L H X X X
Deep Power Down Entry H L L H H L X X 6
Deep Power Down Exit L H X X X
Note :
1. CKE n is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exitin
g
Self Refresh occurs by asynchro nous ly brin
g
in
g
CKE from low to hi
g
h and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP command s should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, interna l refresh counter contro ls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A10 define OP CODE written to the mode register, and BA1/BA0 must b e issued “0/0” in the mode register set, and “1/0”
in the extended mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” m eans the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
11
www.issi.com - DRAM@issi.com
Rev. A | July 2010
DQM Latency is 2 CLK.
6. Stand ard SDRAM parts assign this command sequenc e as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
IS42VM32200G
Table5: Function Truth Table
Command
Current
State
Command
Action Note
/CS /RAS /CAS /WE BA A0-A10 Description
L L L L OP CODE Mode Register Set Set the Mode Register 14
L L L H X X Auto or Self Refresh Start Auto or Self
Refresh 5
L L H L BA X Precharge No Operation
L
L
H
H
BA
RAdd
BkAi
Activate the Specified
Idle
L
L
H
H
BA
R
ow
Add
.
B
an
k
A
ct
i
vate
Activate
the
Specified
Bank and Row
L H L L BA Col Add./ A10 Write/WriteAP ILLEGAL 4
L H L H BA Col Add./ A10 Read/ReadAP ILLEGAL 4
L H H H X X No Operation No Operation 3
H X X X X X Device Desele ct No Operation or Power
Down 3
Row
Active
LLL L OP CODE Mode Re
g
ister Se
t
ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge Precharge 7
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add./A10 Write/Write AP Start Write : Optional
AP(A10=H) 6
Sta t Read Optional
L H L H BA Col Add./A10 Read/Read AP
Sta
r
t
Read
:
Optional
AP(A10=H) 6
L H H H X X No Operation No Operation
H X X X X X Device Desele ct No Operation
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
Termination Burst :
Read
LLHLBA X Prechar
g
e
Termination
Burst
:
Start the Precharge
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add./A10 Write/WriteAP Termination Burst :
Start Write(AP) 8,9
L H L H BA Col Add./A10 Read/Read AP Terimination Burst :
Start Read(AP) 8
L
H
H
H
X
X
No Operation
Continue the Burst
L
H
H
H
X
X
No
Operation
Continue
the
Burst
H X X X X X Device Desel ect Continue the Burst
12
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table5: Function Truth Table
Command
Current
State
Command
Action Note
/CS /RAS /CAS /WE BA A0-A10 Description
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
LL HLBA X Precharge Termination Burst :
Start the Precharge 10
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
Write
L
L
H
H
BA
Row
Add.
Bank
Activate
ILLEGAL
4
L H L L BA Col Ad d ./A10 Write/WriteAP Termination Burst :
Start Write(AP) 8
L H L H BA Col Add./A10 Read/ReadAP Terimination Burst :
Start READ(AP) 8,9
L H H H X X No Operation Continue the Burst
H X X X X X Device Desele ct Continue the Burst
Read
with
Auto
Precharge
LL LL OP CODE Mode Re
g
ister Se
t
ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 4,12
L L H H BA Row Add. Bank Activate ILLE GAL 4,12
L H L L BA Col Add ./A10 Write/WriteAP ILLEGAL 12
L H L H BA Col Add./A10 Read/ReadAP ILLEGAL 12
L H H H X X No Operation Continue the Burst
H X X X X X Device Desele ct Continue the Burst
Write
with
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
with
Auto
Precharge
L
L
H
H
BA
Row
Add.
Bank
Activate
ILLEGAL
4,12
L H L L BA Col Add./A10 Write/WriteAP ILLEGAL 12
L H L H BA Col Add./A10 Read/ReadAP ILLEGAL 12
L H H H X X No Operation Continue the Burst
H X X X X X Device Desele ct Continue the Burst
13
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table5: Function Truth Table
Current Command
Action
Note
State
Action
Note
/CS /RAS /CAS /WE BA A0-A10 Description
Pechaging
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
LL HLBA X Precharge No Operation : Bank(s)
Idle after tRP
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
P
r
echa
r
ging
L H L L BA Col Add./ A10 Write/WriteAP ILLEGAL 4,12
L H L H BA Col Add./ A10 Read/ReadAP ILLEGAL 4,12
L H H H X X No Operation No Operation : Bank(s)
Idle after tRP
H X X X X X Device Deselect No Operation : Bank(s)
Idle after tRP
L L L L OP CODE Mode Register Set ILLEGAL 13,14
Row
Activating
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 4,12
L L H H BA Row Add. Bank Activate ILLEGAL 4 ,11,12
L H L L BA Col Add./A10 Write/Write AP ILLE GAL 4,12
L H L H BA Col Add./A10 Read/Read AP ILLEGAL 4,12
No Operation : ROw
L H H H X X No Operation
No
Operation
:
ROw
Active after tRCD
H X X X X X Device Deselect No Operation : ROw
Active after tRCD
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 4,13
Write
Recovering
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add./A10 Write/WriteAP Start Write : Optional
AP(A10=H)
L H L H BA Col Add./A10 Read/Read AP Start Write : Op tional
AP(A10=H) 9
L H H H X X No Operation No Operation : Row
Active after tDPL
H X X X X X Device Deselect No Operation : Row
Active after tDPL
14
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table5: Function Truth Table
Current
Command
Current
State
A
ction Note
/CS/RAS/CAS/WEBA A0-A10 Description
Write
Recovering
with
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 4,13
L L H H BA Row Add . Bank Activate ILLEGAL 4,12
L
H
L
L
BA
Col Add / A10
Write/WriteAP
ILLEGAL
412
with
Auto
Precharge
L
H
L
L
BA
Col
Add
.
/
A10
Write/WriteAP
ILLEGAL
4
,
12
L H L H BA Col Add./ A10 Read/ReadAP ILLEGAL 4,9,12
L H H H X X No Operation No Operation :
Precharge after tDPL
H X X X X X Device Deselect No Operation :
Precharge after tDPL
L L L L OP CODE Mode Register Set ILLEGAL 13,14
Refreshing
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 13
L L H H BA Row Add. Bank Activate ILLEGAL 13
L H L L BA Col Add./A10 Write/Write AP ILLEGAL 1 3
L H L H BA Col Add./A10 Read/Read AP ILLEGAL 13
L
H
H
H
X
X
No Operation
No Operation : Idle
fC
L
H
H
H
X
X
No
Operation
a
f
ter tR
C
H X X X X X Device Deselect No Operation : Idle
after tRC
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge ILLEGAL 13
L
L
H
H
BA
Row Add
Bank Activate
ILLEGAL
13
Mode
Register
Accessing
L
L
H
H
BA
Row
Add
.
Bank
Activate
ILLEGAL
13
L H L L BA Col Add./A10 Write/WriteAP ILLEGAL 13
L H L H BA Col Add./A10 Read/Read AP ILLEGAL 13
L H H H X X No Operation No Operation : Idle
after 2 Clock Cycle
H X X X X X Device Deselect No Operation : Idle
after 2 Clock Cycle
15
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Note :
1HLiHihLLiL XD't BABkAdd APAtP h
1
.
H
:
L
o
gi
c
High
,
L
:
L
o
gi
c
L
ow,
X
:
D
on
't
care,
BA
:
B
an
k
Add
ress,
AP
:
A
u
t
o
P
rec
h
ar
g
e.
2. A ll entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in pow er down cycle
4. Illegal to bank in specified states. Functi on may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Re fresh m ode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not sati sfi ed .
8. Must satisfy burst interrupt condition.
9. Must satisfy bus content i on, bus turn around, and/or write recover y requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tR RD is not sati sf ied
12. Illegal for single ba nk, but legal for other banks in multi-bank device s.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same comma nd truth table except BA.
16
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table6: CKE Truth Table
Current
CKE Command
Ai
N
Current
State
A
ct
i
on
N
ote
Prev
Cycle Current
Cycle /CS/RAS/CAS/WEBA A0-A10
Self
Refresh
HXXXXXXXINVALID 2
LHHXXXXX
Exit Self Refresh with Device
Deselect 3
LHLHHHX
X Exit Self Refresh with No
Operation 3
Refresh
L H L H H L X X ILLEGAL 3
L H L H L X X X ILLEGAL 3
L H L L X X X X ILLEGAL 3
L L X X X X X X Maintain Self Refresh
HXXXXXXXINVALID 2
L
H
H X X X X X Power Down Mode Exit, All
Banks Idle
3
Power
Down
L
H
Banks
Idle
3
LH HHX X
LHL
L X X X X ILLEGAL
3
XLXX X
XXLX X
L L X X X X X X Maintain Power Down Mod e
HXXXXXXXINVALID 2
Deep
Power
Down
L H X X X X X X Deep Power Down Mod e Exit 6
L L X X X X X X Maintain Deep Power Down
Mode
H H H X X X Refer to the Idle State
section of the Current State
Truth Table
4
HHLHXX 4
HHLLHX 4
All
Banks
Idle
H H L L L H X X Auto Refresh
H H L L L L OP CODE Mode Register Set 5
H L H X X X Refer to the Idle State
section of the Current State
Truth Table
4
HLLHXX 4
HLLLHX 4
HLLLLHXXEntry Self Refresh 5
H L L L L L OP CODE Mode Register Set
L X X X X X X X Power Down 5
Any
State
other
than
listed
H H X X X X X X Refer to Operations of the
Current State Truth Table
H L X X X X X X Begin Clock Suspend next
cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend next
17
www.issi.com - DRAM@issi.com
Rev. A | July 2010
listed
above
L
H
X
X
X
X
X
X
Exit
Clock
Suspend
next
cycle
L L X X X X X X Maintain Clock Suspend
IS42VM32200G
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to hig h transitio n, the clo ck and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to hig h transitio n, the clo ck and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edg e of clock after CKE goes
high and is maintained for a minimum 100usec
high
and
is
maintained
for
a
minimum
100usec
.
18
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table7: Absolute Maximum Rating
Parameter Symbol Rating Unit
Ambient Temperature (Industria l) TA
-40 ~ 85 °C
Ambient Temperature (Commercia l) 0 ~ 70
Storage Temperature TSTG -55 ~ 150 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 2.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 2.6 V
Short Circuit Output Current
I
OS
50
mA
Short
Circuit
Output
Current
I
OS
50
mA
Power Dissipation PD1W
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8: Capacitance (TA=25 °C, f=1MHz, VDD=1.8V)
Parameter Pin Symbol Min Max Unit
Input Capacitance CLK CI1 24pF
A0~A10, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE, DQM0~DQM3 CI2 24pF
Data In
p
ut
/
Out
p
ut Ca
p
acitance D
Q
0~D
Q
31 C
IO
35
p
F
p/ p p
QQ
IO
p
Table9: DC Operating Condition (Voltage referenced to VSS=0V, TA= -40 ~ 85 °C)
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.70 1.8 1.95 V
VDDQ
170
18
195
V
1
VDDQ
1
.
70
1
.
8
1
.
95
V
1
Input High Voltage VIH 0.8 X VDDQ - VDDQ+0.3 V 2
Input Low Voltage VIL -0.3 0 0.3 V 3
Output High Voltage VOH 0.9 X VDDQ - - V IOH= -0.1mA
Output Low Voltage VOL --0.2VI
OL= +0.1mA
Input Leakage Current ILI -1 - 1 uA 4
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = VDDQ+1.5V AC. The overshoot voltage duration is ≤3ns.
3. VIL(mi n) = -1.0V AC. T he overshoot voltage duration is ≤3ns.
4. Any input 0V ≤VIN ≤VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
Output Leakage Current ILO -1.5 1.5 uA 5
19
www.issi.com - DRAM@issi.com
Rev. A | July 2010
5. DOUT is disabled, 0V ≤VOUT ≤VDDQ.
IS42VM32200G
Table10: AC Operating Condition (TA= -40 ~ 85 °C, VDD = 1.70V~1.95V, VSS=0V)
Pt
Sbl
T
Uit
P
arame
t
e
r
S
ym
b
o
l
T
yp
U
n
it
AC Input High/Low Level Voltage VIH / VIL 0.9 X VDDQ / 0.2 V
Input Timing Measur ement R eference Level Voltage VTRIP 0.5 x VDDQ V
Input Rise / Fall Time tR/ tF1 / 1 ns
Output Timing Measurement Reference Level Voltage VOUTREF 0.5 x VDDQ V
Output Load Capacitance for Access Time Measurement CL30 pF
Output
500Ω
VDDQ
Output
50Ω
VTT=0.5 x VDDQ
Z0
=
50
Ω
Output
500Ω30pF
Output
30pF
Z0 50
Ω
DC Output Load Circuit
AC Output Load Circuit
DC
Output
Load
Circuit
AC
Output
Load
Circuit
20
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table11: DC Characteristic (DC operating conditions unless otherwise noted)
Pt
S
TtCditi
Speed
Uit
Nt
P
arame
t
e
r
S
ym
T
es
t
C
on
diti
on
U
n
it
N
o
t
e
-75 -10
Operating Current ICC1 Burst Leng th=1, One Bank Active,
tRC ≥tRC(min) IOL = 0 mA 55 50 mA 1
Precharge Standby Current
in Power Down Mode ICC2P CKE ≤VIL(max), tCK = 10ns 0.3 mA
ICC2PS CKE & CLK ≤VIL(max), tCK = ∞0.3
ICC2N CKE ≥VIH(min), /CS ≥VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks
8
Prechar
g
e Standby Current
in Non Power Down Mode
Input
signals
are
changed
one
time
during
2
clks
.mA
ICC2NS CKE ≥VIH(min), CLK ≤VI L(max), tCK = ∞
Input signals are stable. 1
Active Standby Current
in Power Down Mode ICC3P CKE ≤VIL(max), tCK = 10ns 5mA
ICC3PS CKE & CLK ≤VIL(max), tCK = ∞1
Active Standby Current ICC3N CKE ≥VIH(min), /CS ≥VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks. 15
mA
in Non Power Down Mode
mA
ICC3NS CKE ≥VIH(min), CLK ≤VI L(max), tCK = ∞
Input signals are stable. 6
Burst Mode Operating Current ICC4 tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk 75 70 mA 1
Auto Refresh Current (4K Cycle) ICC5 tRC ≥tRFC(min), All Banks Active 75 70 mA 2
PASR TCSR
85°C350
Self
Refresh
Current ICC6 CKE ≤0.2V uA
4 banks 45°C180
2 Bank 85°C310
45°C160
1 Bank 85°C290
45°C150
Deep Power Down Mode Current
ICC7
30
uA
Note :
1. Measur ed with outputs open.
2. Refresh period is 64ms.
Deep
Power
Down
Mode
Current
ICC7
30
uA
21
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Table12: AC Characteristic (AC operation conditions unless otherwise noted)
-
75
-
10
Paramete
r
Sym
75
10
Unit Note
Min Max Min Max
CLK Cycle Time CL = 3 tCK3 7.5 1000 10 1000 1
CL = 2 tCK2 10 10
Access time from CLK (pos. edge) CL = 3 tAC3 6 8 2
CL = 2 tAC2 8 8
CLK High-Level Width tCH 2.5 2.5 3
CLK Low-Level Width tCL 2.5 2.5 3
ns
CKE Setup Time tCKS 2.0 2.0
CKE Hold Time tCKH 1.0 1.0
/CS, /RAS, /CAS, /WE, DQM Setup Time tCMS 2.0 2.0
/CS, /RAS, /CAS, /WE, DQM Hold Time tCMH 1.0 1.0
Address Setup Time tAS 2.0 2.0
Address Hold Time tAH 1.0 1.0
Data-In Setup Time tDS 2.0 2.0
Data
-
In Hold Time
tDH
10
10
Data
In
Hold
Time
tDH
1
.
0
1
.
0
Data-Out High-Impedance Time from
CLK (pos.edge) CL = 3 tHZ3 6 8 4
CL = 2 tHZ2 8 8
Data-Out Low-Impedance Time tLZ 1.0 1.0
Data-Out Hold Time (load ) tOH 2.5 2.5
Data-Out Hold Time (no load) tOHN 1.8 1.8
ACTIVE to PRECHARGE command tRAS 45 100K 40 100K
PRECHARGE command period tRP 22.5 24
bk bk d
ACTIVE
b
an
k
a to ACTIVE
b
an
k
a comman
d
tRC 67.5 64 5
ACTIVE bank a to ACTIVE bank b command tRRD 15 20
ACTIVE to READ or WRITE delay tRCD 22.5 30
READ/WRITE command to READ/WRITE command tCCD 1 1 CLK 6
WRITE command to input d a ta delay tDWD 0 0 6
Data-in to PRECHARGE command tDPL 15 20 ns 7
Data-in to ACTIVE com ma nd tDAL 37.5 40 7
DQM to data high-impedan ce during READs tDQZ 2 2 6
CLK
DQM to data mask during WRITEs tDQM 0 0 6
LOAD MODE REGISTER command to ACTIVE or
REFRESH command tMRD 2 2 8
Data-out to high-impedanc e from
PRECHARGE command CL = 3 tROH3 3 3 6
CL = 2 tROH2 2 2
Last data-in to burst STOP command tBDL 1 1 6
Last data-in to new RE AD/WR ITE command tCDL 1 1 6
CKE to clock disable or power-down entry mode tCKED 1 1
CLK
9
CLK
CKE to clock enable or power-down exit setup mode tPED 1 1 9
Refresh period (4,096 rows) tREF 64 64 ms
AUTO REFRESH period tRFC 67.5 70 ns 5
Exit SELF REFRESH to ACTIVE command tXSR 67.5 70 5
Transition time tT 0.5 1 .2 0 .5 1.2
22
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
A. Target values listed with alternative values in parentheses.
B
tRFC
t
b
l
th
l
t
tRC
1
CLK
B
.
tRFC
mus
t
b
e
l
ess
th
an or equa
l
t
o
tRC
+
1
CLK
tXSR must be less than or equal to tRC+1CLK
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
23
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Special Operation for Low Power Consumption
T
e
m
pe
r
atu
r
e
Co
m
pe
n
sated
Se
l
f
R
e
fr
es
h
epeatue
Co pe sated
Se
ees
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are All Banks;all four banks, Two Banks;bank a and b, One Bank;bank a, Half of
One Bank;1/2 of bank a, Quarter of One Bank;1/4 of bank a. WRITE and READ commands can still occur during standard operation, but
only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
whileCKEislow.ThismodeisexitedbyassertingCKEhigh.
24
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Figure7: Deep Power Down Mode Entry
CLK
CKE
/CS
/
RAS
Precharge if needed Deep Power Down Entry
tRP
/
/CAS
/WE
DON’T CARE
Figure8: Deep Power Down Mode Exit
CLK
CKE
/CS
/RAS
/CAS
/WE
100
µ
s
tRP
tRFC
100
µ
s
tRP
tRFC
Deep Power Down Exit
All Banks Precharge
Auto Refresh Mode Register Set
Extended Mode Reg ister Set
New Command
Auto Refresh
DON’T CARE
25
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
0
7
4
/2008
r
ence document : JEDEC MO-2
0
TROLLING DIMENSION : MM .
E
:
08/1
4
0.45
2. Refe
r
1. CON
NOT
E
O
utline
0.80
Package
O
D1
26
www.issi.com - DRAM@issi.com
Rev. A | July 2010
IS42VM32200G
Ordering Information – VDD = 1.8V
Id tilR (
40
o
Ct +85
o
C)
I
n
d
us
t
r
i
a
l
R
an
g
e:
(
-
40
o
C
t
o
+85
o
C)
Configuration Frequency
(MHz) Speed
(ns) Order Part No. Package
2Mx32 133 7.5 IS42VM32200G-75BLI 90-ball BGA, Lead-free
27
www.issi.com - DRAM@issi.com
Rev. A | July 2010