EV12DS400AZP Commercial and Industrial Grade Low power 12bit 4.5GSps Digital to Analog Converter with 4/2:1 Multiplexer Datasheet DS1130 MAIN FEATURES * 12bit resolution * 4.5 GSps guaranteed conversion rate * -3dB Analog output Bandwidth of 7 GHz * 4:1 or 2:1 integrated parallel MUX (selectable) * Selectable output modes: * * * * Return to Zero (RTZ), Non Return to Zero (NRZ), Narrow Return To Zero (NRTZ) and Radio Frequency (RF) Low latency time: 3 clock cycles 2.6 Watt Power Dissipation (in 4:1 MUX) 3 Wires Serial Interface Functions: - Selectable MUX ratio 4:1 (up to 4.5 GSps), 2:1 (up to 3.2 GSps) - Userfriendly functions, digitally controlled through a 3WSI serial interface: Gain Adjustment Output clock division selection (possibility to change the division ratio of the DSP clock) (OCDS) Reshaped Pulse Width (RPW) and Reshaped Pulse Begin (RPB) adjustments for performance optimization * * * * * * - Input data check bit for timing interface with FPGA check (IDC) - Timing violation flag (setup or hold) for FPGA communication monitoring (TVF) - Diode for die junction temperature monitoring LVDS differential data input and DSP clock output. Analog output differential swing: 1Vpp (100 differential impedance) Power on reset External SYNC that can be used for synchronization of multiple DACs Power supplies: 3.3 V (Digital), 3.3V & 5V (Analog) FpBGA package (15 x 15 mm body size, 1 mm pitch) PERFORMANCES Broadband: NPR at -14 dBFS Loading Factor (90% of full Nyquist zone), 1st Nyquist (NRTZ): NPR = 47.5 dB, 9.4 Bit Equivalent at Fs = 4.5 GSps 2nd Nyquist (NRTZ): NPR = 42 dB, 8.5 Bit Equivalent at Fs = 4.5 GSps Clock phase shift select for synchronization with DSP (PSS[2:0]) 3rd Nyquist (RF): NPR = 39 dB, 8 Bit Equivalent at Fs = 4.5 GSps Input Under Clocking Mode by 1/2/4 (IUCM) DOCSIS 3.0 Compatible Direct access available for bit OCDS and PSS Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with information contained herein. Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 SaintEgreve, France Holding Company: Teledyne e2v Semiconductors SAS Telephone: +33 (0)4 76 58 30 00 Contact Teledyne e2v by email: hotlinebdc@teledynee2v.com or visit www.teledynee2v.com for global sales and operations centres Teledyne e2v Semiconductors SAS 2017 1130E-BDC-07/17 EV12DS400AZP 1. BLOCK DIAGRAM Figure 11. Simplified block diagram Latches 24 A 24 24 B 24 4 data ports (12-bit differential) Latches MUX FPGA 1st M/S 24 24 C 24 24 D 24 2nd M/S MODE [1:0] DAC Core (NRZ, RTZ, NRTZ, RF) DSP DSPN 1 2 2 GA FPGA TIMING DSP CLOCK PHASE SHIFT CLOCK DIV/X CLOCK BUFFER 2 PSS[2:0] 2. OUT, OUTN DIODE Port Select TVF IDC_P IDC_N 2 OCDS SYNC, SYNCN CLK, CLKN 3WSI Reset_n 3 sclk, sdata, sld_n DESCRIPTION The EV12DS400A is a 12bit 4.5 GSps DAC with an integrated 4:1 or 2:1 multiplexer and 7 GHz output bandwidth, allowing easy interface with standard FPGAs thanks to user friendly features such as DSP clock, OCDS, PSS, TVF. It embeds 4 different output modes (NRZ, RTZ, NRTZ and RF) that allow performance optimizations depending on the Nyquist zone of interest. 2 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 3. 3.1 ELECTRICAL CHARACTERISTICS Absolute Maximum ratings Table 31. Absolute maximum ratings Value Unit Symbol min max VCCA5 analog supply voltage VCCA5 -0.6 6.0 V VCCA3 analog supply voltage VCCA3 -0.6 4.0 V VCCD digital supply voltage VCCD -0.6 4.0 V [P0..P11], [P0N..P11N], IDC_P, IDC_N, SYNC, SYNCN 0 VCCA3 V 2.0 Vpp 4.0 V 3 Vpp VCCD + 0.4 V 170 C Parameter Digital input (on each singleended input), IDC and SYNC signal Digital input maximum differential swing Port P = A, B, C, D Master clock input (on each single ended input) CLK, CLKN 1.0 Master clock maximum differential swing Control function inputs voltage Junction temperature Parameter PSS[0..2], OCDS, reset_n, sclk, sdata, sld_n TJ -0.4 Symbol Value Unit Electrostatic discharge human body model ESD HBM JESD22A114E Class 1C (1000V to < 2000V) Electrostatic discharge machine model ESD MM JESD22A115C Class M2 (100V to < 200V) V JEDEC 78B Class I & Class II Latch up Moisture sensitivity level MSL 3 Storage temperature range Tstg -65 to +150 C Notes: 1. Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. 2. All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by inappropriate handling or storage could range from performances degradation to complete failure. 3. Maximum ratings enable active inputs with DAC powered off. 4. Maximum ratings enable floating inputs with DAC powered on. 5. DSP clock and TVF output buffers must not be shorted to ground or positive power supply. 3 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 3.2 Recommended conditions of use Table 32. Recommended conditions of use Symbol Recommended Value Unit Note VCCA5 analog supply voltage VCCA5 5.0 V (1)(2) VCCA3 analog supply voltage VCCA3 3.3 V (1)(2) VCCD digital supply voltage VCCD 3.3 V (1)(2) 1.075 1.425 350 V V mVp CLK, CLKN 1.4 Vpp PCLK 4 dBm PSS[0..2], OCDS, reset_n, sclk, sdata, sld_n 0 VCCD V V RPB & RPW settings for enhanced dynamic performance 4.5 GSps in NRTZ mode RPB RPW RPB1 RPW1 - - (4) RPB settings for enhanced dynamic performance 4.5 GSps in RTZ mode RPB RPB1 - - (4) RPB & RPW settings for enhanced dynamic performance 4.5 GSps in RF mode RPB RPW RPB3 RPW0 - - (4) Parameter Digital input (on each single ended input), IDC and SYNC signal Port P = A, B, C, D VIL VIH Digital input differential swing Master Clock input differential mode swing Master Clock input power level (differential mode) Control function inputs VIL VIH [P0..P11], [P0N..P11N], IDC_P, IDC_N, SYNC, SYNCN (3) Notes: 1. See Section 8.8 on page 68 for power on requirement 2. No powerdown sequencing is required 3. Clock input power can be decreased when clock frequency is lower as long as it respects the specification. 4. A good compromise for RPB & RPW values is defined for a 4.5GHz clock frequency. This couple of values depends on the clock frequency. A good compromise for RPB & RPW values is defined for a 4.5GHz clock frequency. This couple of values depends on the clock frequency. These recommended RPB/RPW couples have been chosen to offer good performances over the Nyquist of use (1st and 2nd in NRTZ mode, 2nd and 3rd in RF mode) at Fclock = 4.5 GHz. For specific condition (for example looking at the SFDR at a particular output frequency), a RPB/RPW optimization can increase performances. 4 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 3.3 DC Electrical Characteristics Unless otherwise specified: VCCA5 = 5V, VCCA3 = 3.3V, VCCD = 3.3V, 4:1 MUX ratio, room temperature, typical swing on input data, typical Pclk, Master clock input jitter is below 100 fs rms integrated over 11 GHz bandwidth. Table 33. DC Electrical characteristics Parameter Symbol Min RESOLUTION Typ Max 12 Unit Notes Test level(1) bit POWER REQUIREMENTS Power Supply voltage Analog Analog Digital VCCA5 VCCA3 VCCD 4.75 3.15 3.15 5 3.3 3.3 5.25 3.45 3.45 V V V Power Supply current (4:1 MUX) Analog Analog Digital ICCA5 ICCA3 ICCD 85 170 360 100 205 425 115 240 490 mA mA mA Power Supply current (2:1 MUX) Analog Analog Digital ICCA5 ICCA3 ICCD 85 170 310 100 205 370 115 240 430 mA mA mA Power dissipation (4:1 MUX) PD4 2.2 2.6 3 Power dissipation (2:1 MUX) PD2 2 2.4 (2) 1 (8) 1 (8) 1 W (8) 1 2.8 W (8) 1 500 1.6 mVp V 1 1 2 pF 5 DIGITAL DATA INPUTS, SYNC and IDC INPUTS Logic compatibility Digital input voltages: Differential input voltage Common mode LVDS VID VICM 100 1 350 1.25 Input capacitance from each single input to ground 80 100 120 1 Input voltages (Differential operation swing) 0.6 1.4 2.4 Vpp 1 Power level (Differential operation) -4 4 +8.5 dBm Common mode 2.4 2.5 2.6 V 1 2 pF 5 120 1 450 1.375 mVp V Differential input resistance CLOCK INPUTS Input capacitance from each single input to ground (at die level) Differential Input resistance: 80 100 (3) 1 DSP CLOCK OUTPUT Logic compatibility Output voltages: Differential output voltage Common mode LVDS VOD VOCM 240 1.125 350 1.250 (10) 1 1 5 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 33. DC Electrical characteristics (Continued) Parameter Symbol Min Typ Max Unit 0.92 1 1.08 Vpp Notes Test level(1) ANALOG OUTPUT Fullscale Differential output voltage (100 differentially terminated) Fullscale output power (differential output on 100Ohm) +1 VCCA5-0.50 Singleended midscale output voltage (50 terminated) Output capacitance VCCA5-0.43 VCCA5-0.36 1.5 Nominal Output internal differential resistance 90 Output VSWR (using Teledyne e2v's evaluation board) 2.25 GHz 4.5 GHz 6 GHz 100 110 1 dBm (4) 1 V (5) 1 pF 5 1 1.2 1.4 1.7 -3dB Analog Output bandwidth 4 7 GHz 4 FUNCTIONS Digital functions: sdata, sld_n, sclk, reset_n, OCDS, PSS Logic 0 Logic 1 VIL VIH 1.6 VCCD sdata, sld_n, sclk, reset_n Low Level input current High Level input current IIL IIH -120 10 OCDS, PSS: Low Level input current High Level input current IIL IIH -150 50 VOL VOH 2.3 Digital output function TVF Logic 0 Logic 1 0 1 0.8 V V -55 80 -10 120 A A 1 -100 100 -50 150 A A 1 0.6 V V 500 500 A A 5 0.8 LSB 1 LSB 1 LSB 1 LSB 1 IOL IOH (8) 1 DC ACCURACY Differential NonLinearity DNL+ Differential NonLinearity DNL Integral NonLinearity INL+ Integral NonLinearity INL 0.4 0.8 -0.4 0.7 -2.5 2.5 -0.7 DC GAIN DAC output voltage (@default value) 0.92 DAC output voltage adjustment step -5 DAC output voltage after optimum 3WSI adjustment DAC output voltage sensitivity to supplies DAC output voltage drift over temperature 0.995 0.3 1 3.2 45 1.08 Vpp +5 mV 1.005 5 55 (6) 1 1 Vpp (6) 1 % (7) 1 mVpp (9) 4 Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 6 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 2. See Section 8.8 on page 68 for power up sequencing. 3. For use in higher Nyquist zone, it is recommended to use higher power clock within the limit. 4. In NRZ mode only. For the other reshaped modes, the output power will be lower by construction. Refer to Figure 52 and Figure 53. 5. These values are mainly for information as singleended operation is not recommended. 6. The DAC output voltage can be adjusted close to 1Vpp thanks to the GAIN control register in the 3WSI. 7. DAC output voltage sensitivity to supplies = DAC output voltage at Vmax DAC output at Vmin. Measurement done with DAC Gain Adjust at its default value (3WSI GA register default value = 0x200) Min and Max values are given versus supplies at room temperature 8. Tested with IOL & IOH=500A 9. DAC output voltage sensitivity to temperature = DAC output voltage at Tmax DAC output voltage at Tmin. Measurement done with DAC Gain Adjust at its default value (3WSI GA register default value = 0x200) Min and Max values are given versus temperature with typical supplies 10. It has been noted that at extreme low temperature and/or VCCD min, Common Mode and swing of the DSP clock signal are reduced. However it stays above the values generally specified for LVDS input swing and Common Mode and thus should not be an issue at the system level. 3.4 AC Electrical Characteristics Unless otherwise specified: VCCA5 = 5V, VCCA3 = 3.3V, VCCD = 3.3V, 4:1 MUX ratio, room temperature, typical swing on input data, typical Pclk, Master clock input jitter is below 100 fs rms integrated over 11GHz bandwidth. Important note on expected performances: Figures for performances in NRTZ and RF modes are given for recommended value of RPW (Reshaping Pulse Width). Tuning of RPW by customer is recommended. Increasing RPW improves signal purity (SFDR) at the expense of noise floor (SNR). Decreasing RPW improves noise floor (SNR) at the expense of signal purity (SFDR). Figures for performance in RTZ, NRTZ and RF modes are given for recommended value of RPB (Reshaping Pulse Begin) which are digitally programmable through the 3 Wires Serial Interface (3WSI). See Section 5.3 on page 25 for more information on RPW and RPB settings. Recommended values for RPB and RPW are given in Table 32. 7 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP . Table 34. AC Electrical Characteristics NRZ Mode (First Nyquist Zone) Parameter Symbol Min Typ Max Unit Notes Test level(1) Singletone Spurious Free Dynamic Range 4:1 MUX Fs = 4.5 GSps @ Fout = 45 MHz 0dBFS Fs = 4.5 GSps @ Fout = 2205 MHz 0dBFS |SFDR| Fs = 3.0 GSps @ Fout = 30 MHz 0dBFS Fs = 3.0 GSps @ Fout = 1470 MHz 0dBFS 2:1 MUX Fs = 3.2 GSps @ Fout = 32 MHz 0dBFS Fs = 3.2 GSps @ Fout = 1568 MHz 0dBFS 66 51 64 51 dBc 4 4 1 1 71 58 70 55 |SFDR| (2)(3) (2)(3) dBc 4 4 75 64 1 1 4:1 MUX Fs = 4.5 GSps @ Fout = 45 MHz 0dBFS Fs = 4.5 GSps @ Fout = 2205 MHz 0dBFS -66 -56 4 4 Fs = 3.0 GSps @ Fout = 30 MHz 0dBFS Fs = 3.0 GSps @ Fout = 1470 MHz 0dBFS -70 -61 2:1 MUX Fs = 3.2 GSps @ Fout = 32 MHz 0dBFS Fs = 3.2 GSps @ Fout = 1568 MHz 0dBFS -70 -60 Fs = 1.5 GSps @ Fout = 15 MHz 0dBFS Fs = 1.5 GSps @ Fout = 735 MHz 0dBFS -74 -66 Fs = 1.5 GSps @ Fout = 15 MHz 0dBFS Fs = 1.5 GSps @ Fout = 735 MHz 0dBFS 65 57 Highest spur level dBm 1 1 4 4 dBm 1 1 Signal independent Spur (clockrelated spur) with 4:1 MUX Fc/2 @4.5 GSps -90 dBm 4 Fc/4 @4.5 GSps -90 dBm 4 SelfNoise Density at code 0 or 4095 @4.5 GSps -160 dBm/Hz 4 Noise Power Ratio -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 43 dB Equivalent ENOB (Computed from NPR figure) ENOB 8.7 Bit 4 SNR 54 dB 4 Signal to Noise Ratio (Computed from NPR figure) (4)(5) 4 8 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 34. AC Electrical Characteristics NRZ Mode (First Nyquist Zone) (Continued) Parameter Noise Power Ratio -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width Equivalent ENOB (Computed from NPR figure) Signal to Noise Ratio (Computed from NPR figure) Max Unit Notes Test level(1) Symbol Min Typ NPR 43 46 dB 1 ENOB 8.7 9.2 Bit 1 SNR 54 57 dB 1 Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 2. Refer to Figure 725 for SFDR variation versus temperature. 3. Refer to Figure 724 for SFDR variation versus supplies. 4. Refer to Figure 743 for NPR variation versus temperature. 5. Refer to Figure 742 for NPR variation versus supplies. Table 35. AC Electrical Characteristics NRTZ Mode (First & Second Nyquist Zone) Parameter Symbol Min Typ Max Unit Notes Test level(1) Singletone Spurious Free Dynamic Range 4:1 MUX Fs = 4.5 GSps @ Fout = 45 MHz 0dBFS Fs = 4.5 GSps @ Fout = 2205 MHz 0dBFS Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS |SFDR| 62 60 55 Fs = 3.0 GSps @ Fout = 30 MHz 0dBFS Fs = 3.0 GSps @ Fout = 1470 MHz 0dBFS Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS 2:1 MUX Fs = 3.2 GSps @ Fout = 32 MHz 0dBFS Fs = 3.2 GSps @ Fout = 1568 MHz 0dBFS Fs = 3.2 GSps @ Fout = 3168 MHz 0dBFS Fs =1.5 GSps @ Fout = 15 MHz 0dBFS Fs =1.5 GSps @ Fout = 735 MHz 0dBFS Fs =1.5 GSps @ Fout = 1485 MHz 0dBFS 73 61 56 65 63 51 dBc 4 4 4 1 1 1 75 65 60 76 63 62 |SFDR| (2)(3) (2)(3) dBc 77 73 57 4 4 4 1 1 1 9 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 35. AC Electrical Characteristics NRTZ Mode (First & Second Nyquist Zone) (Continued) Parameter Symbol Min Typ Max Unit Notes Test level(1) Highest spur level 4:1 MUX Fs = 4.5 GSps @ Fout = 45 MHz 0dBFS Fs = 4.5 GSps @ Fout = 2205 MHz 0dBFS Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS -75 -66 -74 Fs = 3.0 GSps @ Fout = 30 MHz 0dBFS Fs = 3.0 GSps @ Fout = 1470 MHz 0dBFS Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS -76 -69 -76 1 1 1 2:1 MUX Fs = 3.2 GSps @ Fout = 32 MHz 0dBFS Fs = 3.2 GSps @ Fout = 1568 MHz 0dBFS Fs = 3.2 GSps @ Fout = 3168 MHz 0dBFS -77 -67 -80 4 4 4 Fs =1.5 GSps @ Fout = 15 MHz 0dBFS Fs =1.5 GSps @ Fout = 735 MHz 0dBFS Fs =1.5 GSps @ Fout = 1485 MHz 0dBFS -76 -76 -78 4 4 4 dBm dBm 1 1 1 Signal independent Spur (clockrelated spur) with 4:1 MUX Fc @4.5 GSps -46 dBm 4 Fc/2 @4.5 GSps < -93 dBm 4 Fc/4 @4.5 GSps < -93 dBm 4 SelfNoise Density at code 0 or 4095 @4.5 GSps -151 dBm/Hz 4 Noise Power Ratio (1st Nyquist) -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 47.5 dB Equivalent ENOB (Computed from NPR figure) ENOB 9.4 Bit 4 Signal to Noise Ratio (Computed from NPR figure) SNR 58.5 dB 4 Noise Power Ratio (1st Nyquist) -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width NPR 47 50 dB 1 ENOB 9.3 9.8 Bit 1 Signal to Noise Ratio (Computed from NPR figure) SNR 58 61 dB 1 Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 42 dB 4 Equivalent ENOB (Computed from NPR figure) (4)(5) 4 10 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 35. AC Electrical Characteristics NRTZ Mode (First & Second Nyquist Zone) (Continued) Parameter Symbol Equivalent ENOB (Computed from NPR figure) Min Typ Max Unit Notes Test level(1) ENOB 8.5 Bit 4 Signal to Noise Ratio (Computed from NPR figure) SNR 53 dB 4 Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width NPR 41 43.5 dB 1 ENOB 8.3 8.8 Bit 1 SNR 52 54.5 dB 1 Equivalent ENOB (Computed from NPR figure) Signal to Noise Ratio (Computed from NPR figure) Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 2. Refer to Figure 725 for SFDR variation versus temperature. 3. Refer to Figure 724 for SFDR variation versus supplies. 4. Refer to Figure 743 for NPR variation versus temperature. 5. Refer to Figure 742 for NPR variation versus supplies. Table 36. AC Electrical Characteristics RTZ Mode (Second Nyquist Zone) Parameter Symbol Min Typ 59 52 64 59 59 66 Max Test level(1) Unit Notes dBc (2)(3) 4 1 (2)(3) 4 1 Singletone Spurious Free Dynamic Range 4:1 MUX Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS |SFDR| 2:1 MUX Fs = 3.2 GSps @ Fout = 3168 MHz 0dBFS Fs =1.5 GSps @ Fout = 1485 MHz 0dBFS |SFDR| Highest spur level 4:1 MUX Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS -66 -74 dBm 4 1 2:1 MUX Fs = 3.2 GSps @ Fout = 3168 MHz 0dBFS Fs =1.5 GSps @ Fout = 1485 MHz 0dBFS -72 -75 dBm 4 1 -39 dBm 4 Fc/2 @4.5 GSps < -90 dBm 4 Fc/4 @4.5 GSps -86 dBm 4 SelfNoise Density at code 0 or 4095 @4.5 GSps -141 dBm/Hz 4 Signal independent Spur (clockrelated spur) with 4:1 MUX Fc @4.5 GSps 11 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 36. AC Electrical Characteristics RTZ Mode (Second Nyquist Zone) Parameter Symbol Min Typ Max Unit Notes (4)(5) Test level(1) Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 40 dB Equivalent ENOB (Computed from NPR figure) ENOB 8.2 Bit 4 Signal to Noise Ratio (Computed from NPR figure) SNR 51 dB 4 Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width NPR 43.5 46 dB 1 ENOB 8.8 9.2 Bit 1 SNR 54.5 57 dB 1 Equivalent ENOB (Computed from NPR figure) Signal to Noise Ratio (Computed from NPR figure) 4 Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 2. Refer to Figure 725 for SFDR variation versus temperature. 3. Refer to Figure 724 for SFDR variation versus supplies. 4. Refer to Figure 743 for NPR variation versus temperature. 5. Refer to Figure 742 for NPR variation versus supplies. Table 37. AC Electrical Characteristics RF Mode (Second and Third Nyquist Zones) Parameter Symbol Min Typ Max Unit Notes Test level(1) Singletone Spurious Free Dynamic Range 4:1 MUX Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS Fs = 4.5 GSps @ Fout = 6705 MHz 0dBFS |SFDR| Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS Fs = 3.0 GSps @ Fout = 4470 MHz 0dBFS 2:1 MUX Fs = 3.2 GSps @ Fout = 3168 MHz 0dBFS Fs = 3.2 GSps @ Fout = 4768 MHz 0dBFS 61 49 |SFDR| (2)(3) dBc 64 60 70 65 54 65 4 4 1 1 65 58 58 54 |SFDR| Fs = 1.5 GSps @ Fout = 1485 MHz 0dBFS Fs = 1.5 GSps @ Fout = 2235 MHz 0dBFS 4:1 MUX with IUCM2 Fs = 4.5 GSps @ Fout = 4455MHz 0dBFS 56 51 (2)(3) dBc (6) dBc (7) 4 4 1 1 1 12 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 37. AC Electrical Characteristics RF Mode (Second and Third Nyquist Zones) (Continued) Parameter Symbol Min Typ Max Unit Notes Test level(1) Highest spur level 4:1 MUX Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS Fs = 4.5 GSps @ Fout = 6705 MHz 0dBFS -65 -61 Fs = 3.0 GSps @ Fout = 2970 MHz 0dBFS Fs = 3.0 GSps @ Fout = 4470 MHz 0dBFS -69 -67 1 1 2:1 MUX Fs = 3.2 GSps @ Fout = 1568 MHz 0dBFS Fs = 3.2 GSps @ Fout = 4768 MHz 0dBFS -65 -66 4 4 Fs = 1.5 GSps @ Fout = 1485 MHz 0dBFS Fs = 1.5 GSps @ Fout = 2235 MHz 0dBFS -73 -75 4:1 MUX with IUCM2 Fs = 4.5 GSps @ Fout = 4455 MHz 0dBFS -70 dBm -42 dBm 4 Fc/2 @4.5 GSps < -93 dBm 4 Fc/4 @4.5 GSps < -93 dBm 4 SelfNoise Density at code 0 or 4095 @4.5 GSps -138 dBm/Hz 4 4 4 dBm dBm 1 1 (7) 1 Signal independent Spur (clockrelated spur) with 4:1 MUX Fc @4.5 GSps Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 39 dB Equivalent ENOB (Computed from NPR figure) ENOB 8.0 Bit 4 Signal to Noise Ratio (Computed from NPR figure) SNR 50 dB 4 Noise Power Ratio (2nd Nyquist) -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width NPR 42.5 45 dB 1 ENOB 8.6 9.0 Bit 1 Signal to Noise Ratio (Computed from NPR figure) SNR 53.5 56 dB 1 Noise Power Ratio (3rd Nyquist) -14 dBFS peak to rms loading factor Fs = 4.5 GSps 2 GHz broadband pattern, 25 MHz notch width NPR 39 dB 4 Equivalent ENOB (Computed from NPR figure) ENOB 8.0 Bit 4 Equivalent ENOB (Computed from NPR figure) (4)(5) 4 13 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 37. AC Electrical Characteristics RF Mode (Second and Third Nyquist Zones) (Continued) Parameter Symbol Signal to Noise Ratio (Computed from NPR figure) SNR Noise Power Ratio (3rd Nyquist) -14 dBFS peak to rms loading factor Fs = 3 GSps 1.33 GHz broadband pattern, 17 MHz notch width NPR Equivalent ENOB (Computed from NPR figure) Signal to Noise Ratio (Computed from NPR figure) Min Typ Max Unit Test level(1) Notes 50 dB 4 39 42 dB 1 ENOB 8.0 8.5 Bit 1 SNR 50 53 dB 1 Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 2. Refer to Figure 725 for SFDR variation versus temperature. 3. Refer to Figure 724 for SFDR variation versus supplies. 4. Refer to Figure 743 for NPR variation versus temperature. 5. Refer to Figure 742 for NPR variation versus supplies. 6. This measurement at Fs = 1.5 GSps is done with RPB1 and RPW1. 7. The corresponding spectrum shows an output frequency at 4455MHz within an 1125MHz wide Nyquist zone. 3.5 Timing Characteristics and Switching Performances Unless otherwise specified: VCCA5 = 5V, VCCA3 = 3.3V, VCCD = 3.3V, 4:1 MUX ratio, room temperature, typical swing on input data, typical Pclk, Master clock input jitter is below 100 fs rms integrated over 11 GHz bandwidth. Table 38. Timing characteristics and Switching Performances Parameter Symbol Value Unit Test Level(1) Note SWITCHING PERFORMANCE AND CHARACTERISTICS Maximum operating clock frequency 4.514 4:1 MUX mode GHz 4 4 2:1 MUX mode 3.2 GHz Minimum operating clock frequency 300 MHz Parameter Symbol Min Typ Max (2) 5 Unit Note Test Level(1) ps (3) 4 TIMING CHARACTERISTICS Input Data timing Input data setup and hold time tSH 360 Input data rate (4:1 MUX) 1125 Msps 4 Input data rate (2:1 MUX) 1600 Msps 4 Tclock 5 Data clock output timing (DSP, DSPN) DSP clock phase tuning steps PSS 0.5 14 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Parameter Symbol Min Typ Max Unit Note Test Level(1) Master clock to DSP timing Pipeline (4:1 MUX) 3 Pipeline (2:1 MUX) 3 Delay 4:1 MUX Delay 2:1 MUX 540 tPD 540 5 Tclock (4) 5 4 ps 4 SYNC to DSP, DSPN Sync falling edge to DSP rising edge Pipeline in 4:1 MUX 3 Tclock 5 Sync falling edge to DSP rising edge Pipeline in 2:1 MUX 3 Tclock 5 (5) Sync falling edge to DSP rising edge Delay with 2:1 MUX Delay with 4:1 MUX Sync rising edge to DSP falling edge 640 ps 4 640 ps 4 TCLK + 1/2 TDSP ps 5 3 Tclock 4 15 ps tSDSP tSDSPF SYNC timing Minimum Sync pulse width SYNC setup and hold time tSSH 4 (6) SYNC forbidden area lower bound t1 100 ps SYNC forbidden area upper bound t2 t1 - tSSH ps 4 Analog output rise time (2080%) tOR 30 ps 4 Analog output fall time (2080%) tOF 30 ps 4 4 Analog output timing Pipeline (4:1 MUX) 3 Pipeline (2:1 MUX) 3 Analog output delay tOD 560 Tclock (4) ps (4) 5 5 4 Notes: 1. See Section 3.6 on page 17 for explanation of test levels. 2. Minimum operating clock frequency can be DC. It depends on the clock input AC coupling capacitor used in the final application and limitation due to the environment as circuit itself displays no lower clock frequency limitation. 3. Set up and hold time were measured on Teledyne e2v evaluation board and as such include the impact from the FPGA (jit ter and skew) and PCB skew on the board. Refer to Figure 744 on Section 7.3. tSH variation over temperature range is around 20 ps. 4. See Figure 31 and Figure 32 below. 5. See Figure 33 below. 6. See Figure 34 below. 15 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 31. Timing Diagram for 4:1 MUX principle of operation OCDS1, IUCM1 External CLK Data input A xxx N N+4 N+8 N+12 Data input B xxx N+1 N+5 N+9 N+13 Data input C xxx N+2 N+6 N+10 N+14 Data input D xxx N+3 N+7 N+11 N+15 Pipeline + t PD DSP with PSS[000] DSP with PSS[001] Pipeline + t OD xxx OUT Figure 32. N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Timing Diagram for 2:1 MUX principle of operation OCDS1, IUCM1 External CLK Data input A xxx N N+2 N+4 N+6 N+8 N+10 N+12 N+14 Data input B xxx N+1 N+3 N+5 N+7 N+9 N+11 N+13 N+15 DSP with PSS[000] Pipeline + t PD DSP with PSS[001] Pipeline + t OD OUT Figure 33. xxx N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Timing relationship between SYNC and DSP Pipeline + tSDSP SYNC DSP tSDSPF 16 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 34. SYNC Timing Diagram Master Clk t1 t1 t2 SYNC NOK OK t2 NOK OK tSSH SYNC OK SYNC NOK SYNC NOK 3.6 Explanation of Test Levels Table 39. Test levels 1 100% production tested at +25C(1) 2 100% production tested at +25C(1), and sample tested at specified temperatures. 3 Sample tested only at specified temperatures 4 Parameter is guaranteed by characterization testing (thermal steadystate conditions at specified temperature). 5 Parameter value is only guaranteed by design Only MIN and MAX values are guaranteed. Note: 1. Unless otherwise specified. 3.7 Digital Input Coding Table Table 310. Coding Table (Theorical values) Digital output msb...........lsb Differential analog output 000000000000 -500 mV 010000000000 -250 mV 011000000000 -125 mV 011111111111 -0.122 mV 100000000000 0.122 mV 101000000000 +125 mV 110000000000 +250 mV 111111111111 +500 mV 17 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 4. DEFINITION OF TERMS Table 41. Definition of Terms Abbreviation Term Definition (SFDR) Spurious free dynamic range Ratio expressed in dBC of the signal power, set at Full Scale, to the power of the highest spurious spectral component over the Nyquist zone. The peak spurious component may or may not be a harmonic. (HSL) Highest Spur Level Power of the highest spurious spectral component expressed in dBm. Effective Number Of Bits ENOB is calculated from NPR measurement using the formula: ENOB = (NPR[dB] + |LF[dB]| 3 1.76) / 6.02 Where LF is the loading factor i.e. the ratio between the Gaussian noise standard deviation versus amplitude full scale of the NPR pattern. Signal to noise ratio SNR is calculated from NPR measurement using the formula: SNR [dB] = NPR[dB] + |LF[dB]| 3 Where LF is the loading factor i.e. the ratio between the Gaussian noise standard deviation versus amplitude full scale of the NPR pattern. Noise Power Ratio The NPR is measured to characterize the DAC performance in response to broad band signals. When applying a notchfiltered broadband whitenoise pattern at the input of the DAC under test, the Noise Power Ratio is defined as the ratio between the average noise measured on the shoulder of the notch and inside the notch, using the same integration bandwidth. (DNL) Differential non linearity The Differential Non Linearity for a given code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there is no missing point and that the transfer function is monotonic. (INL) Integral non linearity The Integral Non Linearity for a given code i is the difference between the measured voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. (VSWR) Voltage Standing Wave Ratio The VSWR corresponds to the insertion loss linked to the power reflection. For example a VSWR of 1.2 corresponds to a 20dB return loss (i.e. 99% power transmitted and 1% reflected). (IUCM) Input Under Clocking Mode The IUCM principle is to apply a selectable division ratio between the DAC clock section and the MUX clock section. (PSS) Phase Shift Select The Phase Shift Select function is used to tune the phase of the DSP clock. (OCDS) Output Clock Division Select It allows dividing the DSP clock frequency by the OCDS coded value factor. (NRZ) Non Return to Zero Non Return to Zero mode on analog output. (RF) Radio Frequency RF mode on analog output. (RTZ) Return To Zero Return to zero mode on analog output. (NRTZ) Narrow Return To Zero Narrow return to zero mode on analog output. (RPB) Reshaped Pulse Begin Function controlling when the transition of the DAC analog output occurs. (applicable in NRTZ, RTZ and RF mode) (RPW) Reshaped Pulse Width Function controlling the width of the reshaping of the DAC analog output. (applicable in NRTZ and RF mode) (ENOB) (SNR) (NPR) 18 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5. FUNCTIONAL DESCRIPTION Figure 51. DAC functional diagram V CCA5 A0...A11 2x12 A0N...A11N B0...B11 2x12 B0N...B11N C0...C11 2x12 C0N...C11N D0...D11 2x12 D0N...D11N 2 CLK, CLKN V CCD V CCA3 TVF 2 EV12DS400 IDC_P IDC_N 2 OUT, OUTN OCDS PSS 3 2 DSP_CK, DSP_CKN Reset_n sclk, sdata, sld_n SYNC 2 3 DIODE 2 DGND Table 51. AGND Functions description Name Function Name Function VCCD 3.3V digital power supply CLK Inphase master clock VCCA5 5V analog power supply CLKN Inverted phase master clock VCCA3 3.3V analog power supply DSP_CK Inphase output clock DGND Digital ground DSP_CKN Inverted phase output clock AGND Analog ground PSS[0..2] Phase shift select A[11...0] Inphase digital input port A Reset_n Reset of 3WSI registers A[11..0]N Inverted phase digital input port A sld_n 3WSI select B[11...0] Inphase digital input port B sclk, sdata 3WSI clock and data inputs B[11..0]N Inverted phase digital input port B TVF Setup/hold time violation flag C[11...0] Inphase digital input port C IDC_P, IDC_N Input data check C[11..0]N Inverted phase digital input port C OCDS Output Clock Division factor Selection D[11...0] Inphase digital input port D Diode Diode for temperature monitoring D[11..0]N Inverted phase digital input port D SYNC/ SYNCN Synchronization signal (active high) OUT Inphase analog output OUTN Inverted phase analog output 19 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 52. Function Description Controllability MUX MUX ratio selection (4:1 or 2:1) 3WSI MODE Output reshaping mode selection: NRZ, NRTZ, RTZ or RF 3WSI RPW Reshaping Pulse Width (applicable in NRTZ and RF mode) 3WSI RPB Reshaping Pulse Begin (applicable in NRTZ, RTZ and RF mode) 3WSI PSS Phase Shift Select: shift the DSP clock by steps of TCLK/2 for FPGA synchronisation 3WSI/external pins OCDS Output Clock Division Select: Ratio of division between DSP clock and master clock 3WSI/external pins IUCM Internal Under Clocking Mode ratio selection: Allow to work with data rate equal to FCLK divided by 1,2 or 4 with a DAC clocked at FCLK 3WSI GA DAC Gain Adjust 3WSI Note: 5.1 DAC overview functionality and controls 1. PSS and OCDS are controlled through the external pin if ECDC bit of 3WSI state register is set to level 1 (default value). See Section 5.13.3 on page 41 for more information. Multiplexer Two multiplexer ratios (N) are allowed: * N=4: 4:1 MUX, which allows operation up to 4.5 GSps; * N=2: 2:1 MUX, which allows operation up to 3.2 GSps. Label Value Description Default setting MUX 0 4:1 mode (N=4) 0 (4:1MUX mode) 1 2:1 mode (N=2) In 2:1 MUX ratio, the unused data ports (ports C and D) can be left open. 20 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.2 Mode Function The MODE function allows choosing between NRZ, NRTZ, RTZ and RF modes. Label MODE[1:0] Value Description 00 NRZ mode 01 Narrow RTZ (a.k.a. NRTZ) mode 10 RTZ Mode (50%) 11 RF mode Default setting 01 (NRTZ) Ideal equations describing maximum available output power versus analog output frequency in the four modes are given hereafter, with X being the normalised output frequency (i.e. Fout/FCLK, thus the edges of the Nyquist zones are at X = 0, 1/2, 1, 3/2, 2, ...). In fact, due to limited bandwidth, an extra term must be added to take into account a first order low pass filter with a 7 GHz cutoff frequency. In the following formula, Pout (X) is expressed in dBm NRZ mode: k sinc k X Pout(X) = 20 log 10 -----------------------------------------0.893 where sinc(x) = sin(x)/x, and k = 1 NRTZ mode: k sinc k X Pout(X) = 20 log10 --------------------------------------------0.893 where k = 1 RPW/TCLK and RPW is the width of reshaping pulse RTZ mode: k sinc k X Pout(X) = 20 log 10 --------------------------------------------0.893 where k is the duty cycle of the clock presented at the DAC input. Please note that due to phase mismatch in balun used to convert single ended clock to differential clock the first zero may move around the limit of the 4th and the 5th Nyquist zone. Ideally k=1/2. RF mode: kX kX k sinc ------------------- sin ------------------- 2 2 Pout(X) = 20 log 10 -----------------------------------------------------------------------------------0.893 where k = 1 RPW/TCLK and RPW is the width of reshaping pulse. As a consequence: * NRZ mode offers maximum output power for 1st Nyquist operation; * RTZ mode have a slow roll off for 2nd Nyquist operation; * RF mode offers maximum power over 2nd and 3rd Nyquist zones; 21 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP * NRTZ mode offers optimum power over the 1st and the first half of the 2nd Nyquist zones. It is the most relevant mode in terms of performance for operation over 1st and beginning of 2nd Nyquist zones. In the two following Figure 52 and Figure 53, the pink line is the ideal equation's result, and the green line includes a first order 7 GHz cutoff low pass filter to take into account the bandwidth effect due to die and package. Figure 52. Max available output power (Pout) at nominal gain vs output frequency (Fout) in the four output modes at 4.5 GSps, over eight Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz Figure 53. 7.0GHz 7.0GHz Max available output power (Pout) at nominal gain vs output frequency (Fout) in the four output modes at 3.2 GSps, over eight Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz 7.0GHz 7.0GHz 22 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.2.1 NRZ output mode This mode does not allow for operation in the 2nd Nyquist zone because of the sin(x)/x notch. The advantage is that it gives good results at the beginning of the 1st Nyquist zone (less attenuation than in RTZ mode); it also removes the parasitic spur at the clock frequency (in differential). This legacy mode provides the highest output power at the beginning of the 1st Nyquist zone Figure 54. NRZ timing diagram CLK Samples N N+1 N+2 N+3 TCLK tOD V N+1 N N+2 Analog output N+3 5.2.2 Narrow RTZ (NRTZ) output mode This mode has the following advantages: * Optimized power in the 1st Nyquist zone and beginning of the 2nd Nyquist zone; * Extended dynamic and linearity through elimination of noise on transition edges; * Tradeoff between NRZ and RTZ; * Possible operation in the 4th and 5th Nyquist zones. And weaknesses: * Notch in the 3rd Nyquist zone. In fact, notches are at N*(1/(TCLK RPW)), where TCLK is the external clock period and RPW is the reshaping pulse width; * By construction clock spur at FCLK. Figure 55. Narrow RTZ timing diagram CLK Samples N N+1 N+2 N+3 TCLK - RPW tOD + RPB V N+1 N Analog output RPW N+2 RPW RPW RPW N+3 The RPB and RPW settings are applicable in this mode; they are programmable through the 3 wire serial interface. For more information on RPB and RPW see Section 5.3 on page 25. 23 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.2.3 RTZ output Mode The advantage of the RTZ mode is that it enables the operation in the 2nd Nyquist zone but the drawback is that it attenuates more the signal in the first Nyquist zone. Advantages: * Extended roll off of sin(x)/x; * Extended dynamic and linearity through elimination of noise on transition edges; Weakness: * By construction strong clock spur at FCLK. Figure 56. RTZ timing diagram CLK Samples N N+1 N+2 N+3 1/2 TCLK tOD + RPB V N+1 Analog output N N+2 N+3 The RPB setting is applicable in this mode; it is programmable through the 3 wires serial interface. For more information on RPB see Section 5.3 on page 25. 5.2.4 RF output mode RF mode is optimal for operation at high output frequency, since the decay with frequency occurs at higher frequency than for RTZ. Unlike NRZ or RTZ modes, the RF mode presents notches at DC and 2N*(1/(TCLK - RPW), and minimum attenuation for Fout=1/(TCLK - RPW). Advantages: * Optimized for operations over the second half of the 2nd Nyquist zone or over the 3rd Nyquist zone; * Extended dynamic and linearity through elimination of noise on transition edges; * Possible operation proven in the first half of the 4th Nyquist zone. Weakness: * By construction clock spur at FCLK. * Next clock spur pushed to 2.FCLK. 24 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 57. RF timing diagram CLK Samples N N+1 N+2 N+3 tCLK - RPW tOD + RPB V N+1 (+) N+3 (-) N (+) N+2 (+) Analog output RPW N (-) RPW RPW N+1 (-) N+2 (-) RPW N+3 (+) RPB and RPW settings are applicable in this mode; they are programmable through the 3 wire serial interface. For more information on RPB and RPW see Section 5.3. 5.3 RPW and RPB Feature RPB (Reshaping Pulse Begin) and RPW (Reshaping Pulse Width) are new features of the EV12DS400A. They can be used to fine tune the performance of the different modes of the DAC. Their objective is to control the rejection of the signal transitions. These 2 settings are controlled via the 3WSI interface. See Section 5.13 on page 39 for more information on the 3WSI interface. The different values they can take are specified by mode in the following paragraphs. Note: In the following figures, the perturbation on the analog output in time domain has been exaggerated to facilitate the comprehension. NRZ Mode: See below the output of the DAC in NRZ mode in time domain: Figure 58. DAC output in NRZ and time domain As can be seen above, in NRZ mode, the transition contains a lot of perturbations that translates into harmonics in the spectrum. However the output power is maximum. RPB or RPW settings are not available in this mode. 25 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP RTZ Mode: In RTZ mode, the output is on 50% of the sampling period and off the remaining 50% of the sampling period. Per definition of the RTZ mode, its output power is half the one of the NRZ output power. In this mode, the EV12DS400A features the RPB function which controls when the transition between 50% on and 50% off occurs. Using this feature, the RTZ output linearity performance can be increased. See below the output of the DAC in RTZ mode and time domain, whether RPB is correctly configured or not (the NRZ output mode is traced to show the difference between NRZ and RTZ mode): Figure 59. DAC output in RTZ mode and time domain when RPB is optimum Figure 510. DAC output in RTZ mode and time domain when RPB is not optimum Tuning RPB as depicted in Figure 59 will improve the linearity of the output because the transition will be completely rejected. If RPB is not tuned to reject the transitions (see Figure 510), the output harmonics will be degraded (mainly H3). The RPW setting is not available in RTZ mode. See Section 5.13.3 on page 41 for the available values for RPB in RTZ mode. 26 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP NRTZ Mode: The NRTZ mode is a compromise between the NRZ and the RTZ modes. Its objective is to have the best possible linearity through the removal of the transitions while keeping a high output power. Thus, only the transitions should be cancelled. In this mode both RPB and RPW settings are available. The RPB setting controls the position where the signal is cancelled. The RPW setting controls the wideness of the cancelled signal. See below an example where RPB and RPW are optimum in NRTZ mode (the NRZ output mode is traced to show the difference between NRZ and NRTZ mode): Figure 511. DAC output in NRTZ mode and time domain when RPB/RPW are optimum In the case above, the output has a better linearity than in NRZ mode over the complete spectrum while suffering from a slight output power reduction. Figure 512. DAC output in NRTZ mode and time domain when RPB is not optimum 27 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 513. DAC output in NRTZ mode and time domain when RPW is not optimum In case RPB is not optimum (Figure 512), the harmonics will be degraded (mainly H3). In case RPW is smaller than the optimum (Figure 513), the linearity of the output will be degraded. In case RPW is larger than the optimum, the DAC will have high linearity performance but lower output power. The RPW setting impacts the frequency response of the mode. See below the Pout vs Fout figure in NRTZ mode with different RPW values: Figure 514. Pout vs Fout @ 4.5 GSps in NRTZ mode over 4 Nyquist zones with five RPW values 7.0GHz See Section 5.13.3 on page 41 for the available values for RPB and RPW in NRTZ mode. 28 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP RF Mode: The RF mode is used in higher Nyquist zones (2nd and 3rd). Its principle is that the output is at its value during half the sampling period and at its opposite value during the remaining half. To improve linearity of this mode both RPB and RPW settings are available. See below an example where RPB and RPW are optimum in RF mode (the NRZ output mode is traced to show the difference between NRZ and RF mode): Figure 515. DAC output in RF mode and time domain when RPB and RPW are optimum In case RPB is not optimum, the harmonics will be degraded (mainly H3). In case RPW is smaller than the optimum, the linearity of the output will be degraded. In case RPW is larger than the optimum, the DAC will have high linearity performance but lower output power. The RPW setting impacts the frequency response of the mode. See below the Pout vs Fout figure in RF mode with different RPW values: Figure 516. Pout vs Fout @ 4.5 GSps in RF mode over 4 Nyquist zones with five RPW values 7.0GHz See Section 5.13.3 on page 41 for the available values for RPB and RPW in RF mode. 29 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.4 Phase Shift Select function (PSS) It is possible to adjust the timing between the sampling clock and the output DSP clock. The DSP clock output phase can be tuned over a range of 3.5 input clock cycles (7 steps of half a clock cycle) in addition to the intrinsic propagation delay between the DSP clock (DSP, DSPN) and the sampling clock (CLK, CLKN). Three bits are provided for the phase shift function: PSS[2:0]. By setting these 3 bits to 0 or 1, one can add a delay on the DSP clock in order to properly synchronize the input data of the DAC and the sampling clock (the DSP clock should be applied to the FPGA and should be used to clock the DAC digital input data). These 3 bits are either driven directly through the pins PSS[2:0] or through the 3WSI depending on the ECDC bit in the state register of the 3WSI. Table 53. PSS coding table Label Value Description PSS[2:0] 000 No additional delay on DSP clock (Default value) 001 0.5 input clock cycle delay on DSP clock 010 1 input clock cycle delay on DSP clock 011 1.5 input clock cycle delay on DSP clock 100 2 input clock cycles delay on DSP clock 101 2.5 input clock cycles delay on DSP clock 110 3 input clock cycles delay on DSP clock 111 3.5 input clock cycles delay on DSP clock In order to determine how much delay needs to be added on the DSP clock to ensure the synchronization between the input data and the sampling clock within the DAC, the TVF bit should be monitored. Note: Figure 517. In 4:1 MUX mode the 8 settings are relevant, in 2:1 MUX only the four first settings are relevant; the four last settings will yield the same results. PSS timing diagram for 4:1 MUX, OCDS=0 External CLK Internal CLK/4 is used to clock the Data input A, B, C, D into MUXDAC Internal CLK/4 DSP clock is internal CLK/4 delay by MUXDAC (by step of 0,5 CLK via the PSS function) to be used as DDR clock for the FPGA DSP with PSS[000] t=0.5xTCLK DSP with PSS[001] DSP with PSS[010] DSP with PSS[011] DSP with PSS[110] DSP with PSS[111] 30 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 518. PSS timing diagram for 2:1 MUX, OCDS=0 External CLK Internal CLK/2 is used to clock the Data input A, B into DAC Internal CLK/2 DSP clock is internal CLK/2 delay by MUXDAC (by step of 0,5 CLK via the PSS function) to be used as DDR clock for the FPGA DSP with PSS[000] t=0.5xTCLK DSP with PSS[001] DSP with PSS[010] DSP with PSS[011] DSP with PSS[110] DSP with PSS[111] 5.5 Output Clock Division Select function (OCDS) It is possible to change the DSP clock internal division factor from 1 to 2 with respect to the sampling clock/(2*N*M) where N is the MUX ratio (2 or 4), and M is the IUCM ratio (1, 2 or 4). This is possible via the OCDS "Output Clock Division Select" bit through the 3WSI or the external pins if the ECDC bit is high. OCDS is used to obtain a synchronisation clock for the FPGA slow enough to allow the FPGA to operate with no further internal division of this clock, thus its internal phase is determined by the DSP clock phase. This is useful in a system with multiple DACs and multiple FPGAs to guarantee deterministic phase relationship more easily between the FPGAs after a synchronisation of all the DACs. Table 54. OCDS coding table Label Value Description Default setting OCDS 0 OCDS1: DSP clock = Sampling Clock/(2*N*M) 0 (OCDS1) 1 OCDS2: DSP clock = Sampling Clock/(2*N*M*2) Figure 519. OCDS timing diagram for 4:1 MUX and IUCM1 mode External CLK Internal CLK/4 is used to clock the Data input A, B, C, D into Internal CLK/4 DSP clock is internal CLK/4 divided by OCDS selection. This clock could be used as DDR clock for the DSP with OCDS=0 DSP with OCDS=1 Figure 520. OCDS timing diagram for 2:1 MUX and IUCM1 mode External CLK Internal CLK/2 is used to clock the Data input A, B into DAC Internal CLK/2 DSP clock is internal CLK/2 delay divided by OCDS selection. This clock could to be used as DDR clock for the FPGA DSP with OCDS=0 DSP with OCDS=1 31 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.6 Input Under Clocking Mode (IUCM) Three Input Under Clocking Modes are available for specific use where the input data are applied to the DAC at half the nominal rate (or a fourth of the nominal rate) with respect to the DAC sampling rate. These modes are available for both 4:1 MUX mode and 2:1 MUX mode. The principle is to apply a selectable division ratio (1, 2 or 4) between the DAC clock section and the MUX clock section. Thus there are 3 IUCM modes selectable through the 3WSI (see 3WSI description): * IUCM1: MUX is driven by the same clock than the DAC section (default mode). * IUCM2: MUX is driven by a divided by 2 clock coming from the DAC section * IUCM4: MUX is driven by a divided by 4 clock coming from the DAC section Detailed explanation is given hereafter for IUCM2 mode. IUCM4 mode is operating on the same principle but with a 4 division ratio. In IUCM1 mode the DAC expects data at half the nominal rate: if the DAC works at Fs sampling rate, then in 4:1 MUX mode, the input data rate is Fs/4 and the DSP clock is Fs/(2N*X), with N = MUX ratio (2 or 4) and X = OCDS ratio (1 or 2). When the IUCM2 mode is selected, the input data rate can be Fs/8 and the DSP clock frequency is Fs/(2N*X*2), with N = MUX ratio (2 or 4) and X = OCDS ratio (1 or 2). This means that in input under clocking mode, the DAC is capable to treat data at half the nominal rate. In this case, the DSP clock is also half its nominal speed. However, the sampling frequency is still Fs. Label IUCM<1:0> Logic Value Description Default setting 00 or 01 IUCM1: Input Under Clocking Mode inactive 10 IUCM2: clock division ratio between DAC core and MUX: 2 11 IUCM4: clock division ratio between DAC core and MUX: 4 00 (IUCM1) The IUCM2 mode affects spectral response of the different modes. The first effect is that Nyquist zone edges are no longer at n*Fclock/2 but at n*/Fclock/4 (this is the direct consequence of the division by 2 of the data rate). The second effect is the modification of the equations ruling the spectral responses in the different modes. Ideal equations describing maximum available Pout vs Fout in the four output modes when IUCM2 mode is selected are given hereafter, with X= normalised output frequency (i.e. Fout/Fclock, the edges of the Nyquist zones are then at X = 0, 1/4, 1/2, 3/4, 1, ...) In fact, due to limited bandwidth, an extra term must be added to take in account a first order low pass filter with an 7 GHz cutoff frequency. 32 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Assuming sinc(x)=sin(x)/x; NRZ mode: Pout(X) = 20*log10(|sinc(*X)*cos(*X)|/0.893) NRTZ mode: Pout(X) = 20*log10(|k*sinc(k**X)*cos(*X)|/0.893) Where k= 1 RPW/Tclock and RPW is width of reshaping pulse. RTZ mode: Pout(X) = 20*log10(|k*sinc(k**X)*cos(*X)|/0.893) Where k is the DAC input clock duty cycle. Please note that due to phase mismatch in the balun used to convert single ended clock into differential clock, the third zero may move around the limit of the 8th and the 9th Nyquist zones. Ideally k=1/2. RF mode: Pout(x) = 20*log10(|k*sinc(k**X/2)*sin(k**X/2)*cos(*X)|/0.893) where k = 1 RPW/Tclock and RPW is width of reshaping pulse. Figure 521. Max available Pout at nominal gain vs Fout in the four output modes at 4.5 GSps, combined with IUCM2, over eight Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz 7.0GHz 7.0GHz Figure 522. Max available Pout at nominal gain vs Fout in the four output modes at 3.2 GSps, combined with IUCM2, over eight Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz 7.0GHz 7.0GHz 33 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 523. Max available Pout at nominal gain vs Fout in the four output modes at 4.5 GSps, combined with IUCM4, over 16 Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz 7.0GHz 7.0GHz Figure 524. Max available Pout at nominal gain vs Fout in the four output modes at 3.2 GSps, combined with IUCM4, over 16 Nyquist zones, computed for different RPW steps 7.0GHz 7.0GHz 5.7 7.0GHz 7.0GHz Synchronization FPGADAC: IDC_P, IDC_N and TVF function * IDC_P, IDC_N: Input Data Check function (LVDS signal). * TVF: Timing Violation Flag. The IDC_P, IDC_N signal are LVDS signals. This signal should be toggling at each cycle synchronously with other data bits. This signal should be generated by the FPGA so that the DAC can check in realtime if the timings between the FPGA and the DAC are correct. The information on the synchronisation is then given by the TVF flag. IDC should be routed as the data signals (same layout rules and same length). It should be driven to an LVDS low or high level if not used. 34 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 525. IDC timing vs data input: Data Xi, XiN IDC_P, IDC_N Figure 526. FPGA to DAC synoptic IDC 24 Port A 24 Port B 24 Port C 24 Port D 2 OUT, OUTN 2 TVF DSP PSS 2 2 DIV CLK, CLKN 3 OCDS TVF is a 3.3V output signal that indicates if the DAC and the FPGA are synchronised. Table 55. TVF coding table Label Value Description TVF 0 SYNCHRO OK 1 Data setup or hold time violation detected Principle of Operation: The IDC signal is sampled in parallel by 2 clocks. One is delayed positively by half a clock period, the other one is delayed negatively by half a clock period. The result of the sampling of the IDC input by both these clocks is then compared. If both sampled outputs are equivalent, then TVF is at "0" to indicate that DAC and FPGA are synchronised. If not, TVF is set to "1" which means that the edge of the internal sampling clock is inside this window. In that case it is recommended to either: * Shift the DSP clock timing (possible by using the PSS function inside the DAC). * Shift the phase of the FPGA PLL (if this functionality is available in the FPGA) to change the timing of the digital data compared to the DAC clock. 35 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.8 DSP output clock The DSP output clock DSP, DSPN is an LVDS signal which is used to synchronize the FPGA generating the digital patterns with the DAC sampling clock. The DSP clock frequency is a fraction of the sampling clock frequency. The division factor depends on OCDS and IUCM settings. The DSP clock frequency is equal to (sampling frequency / [2N*X*M]) where N is the MUX ratio (2 or 4) and X is the output clock division factor (1 or 2), determined by the OCDS bit and M is the IUCM division ratio (1, 2 or 4) determined by the IUCM bit. For example, in a 4:1 MUX ratio application with a sampling clock at 4 GHz and OCDS set to "0" (i.e. Factor of 1) and in IUCM1, then the input data rate is 1000 MSps and the DSP clock frequency is 500 MHz. This DSP clock is used in the FPGA to control the digital data sequencing. Its phase can be adjusted thanks to the PSS[2:0] bits in order to ensure a proper synchronization between the data coming to the DAC and the sampling clock. The TVF bit should be used to check whether the timing of the interface between FPGA and DAC is cor rect. When the IDC input is provided, the TVF will indicate if there are setup or hold violation at the DAC inputs. If any violation is detected through TVF, the PSS setting should be increased by 4 in MUX4 and by 2 in MUX2. 5.9 OCDS, IUCM and MUX combinations summary The table here after gives the DSP clock division ratio with respect to the DAC input clock. DSPclk=FCLK/(2*N*M*X) DataRate=FCLK/(N*M) Where N: MUX Ratio (2 or 4), M: IUCM Ratio (1, 2 or 4), X: OCDS Ratio (1 or 2) Table 56. OCDS, MUX, IUCM and PSS combinations summary MUX Ratio 4:1 2:1 0 1 IUCM Ratio IUCM1 00 IUCM2 10 IUCM4 11 IUCM1 00 IUCM2 10 IUCM4 11 OCDS Ratio OCDS1: DSP Clock = FCLK/8 0 OCDS2: DSP Clock = FCLK/16 1 OCDS1: DSP Clock = FCLK/16 0 OCDS2: DSP Clock = FCLK/32 1 OCDS1: DSP Clock = FCLK/32 0 OCDS2: DSP Clock = FCLK/64 1 OCDS1: DSP Clock = FCLK/4 0 OCDS2: DSP Clock = FCLK/8 1 OCDS1: DSP Clock = FCLK/8 0 OCDS2: DSP Clock = FCLK/16 1 OCDS1: DSP Clock = FCLK/16 0 OCDS2: DSP Clock = FCLK/32 1 PSS Range / Steps Input Data Rate 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/4 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/8 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/16 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/2 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/4 0 to 7/(2*FCLK) 1/(2*FCLK) steps FCLK/8 Notes: 1. Behaviour according to MUX, OCDS, IUCM and PSS combination is independent of output mode. 2. In 2:1 MUX, only 4 steps of PSS are useful, the 4 other gives the same result. 36 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.10 Synchronisation function The timer of the DAC must be reset after the following changes of configuration: * At poweron; * Whenever one of the following parameter is modified: OCDS, MUX or IUCM; * Whenever the master clock is modified (amplitude, frequency...). There are two SYNC functions integrated in this DAC which reset its timer: * A power up reset, which is triggered by the power supplies if the dedicated power up sequence is applied VCCD > VCCA3 >VCCA5 (the clock must be supplied to the DAC prior to this power up sequence being generated); * An external SYNC, which is triggered by a pulse applied to the differential SYNC/SYNCN inputs. At poweron, there are 2 possibilities: * The powerup sequence of the DAC is VCCD, VCCA3 then VCCA5. In that case an internal power on reset is generated by the DAC. There is no need to send a SYNC pulse as long as OCDS, MUX or IUCM and the master clock are not modified (see Section 8.8 on page 68 for more information). * If the powerup sequence is different from the one above, a SYNC pulse must be sent to the DAC. The external SYNC is LVDS compatible. It is active high. After the application of the SYNC signal, the DSP clock from the DAC will stop and after a constant and known time (tDSP); the DSP clock will start up again. The external SYNC can also be used to synchronize multiple DACs. The pulse duration should be at least of 3 master clock cycles in OCDS1 and IUCM1. Depending on the settings of OCDS, IUCM and also on the MUX ratio the width of the SYNC pulse must be greater than a certain number of external clock pulses. It is also necessary that the sync pulse width shall be a whole number of clock cycles. 5.11 Gain Adjust function This function allows the adjustment of the internal gain of the DAC so that it can be tuned to the unity gain. The gain of the DAC can be adjusted by setting the GAIN register through the 3WSI. The gain can be adjusted by 1024 steps. GA min is given for GAIN = 0x000 and GA max for GAIN = 0x3FF. Default value is GA typ given for GAIN = 0x200. Note: The gain voltage step is indicated in Section 3.3 on page 5 Table 33. 37 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.12 Diode function A diode for die junction temperature monitoring, is available in this DAC. For the measurement of die junction temperature, a temperature sensor can be used. Figure 527. Temperature diode implementation Temperature sensor DAC Diode D+ DGND D- In characterization measurement a current of 1 mA is applied on the DIODE pin. The voltage across the DIODE pin and the DGND pin gives the junction temperature using the intrinsic diode characteristics below Figure 528. Diode Characteristics for Die Junction Temperature Monitoring 38 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.13 5.13.1 DAC 3WSI Description (DAC Controls) 3WSI timing description The 3WSI is a synchronous write only serial interface made of 4 signals: "reset_n": asynchronous 3WSI reset, active low "sclk": serial clock input "sld_n": serial load enable input "sdata": serial data input. The 3WSI gives a "write-only" access to up to 16 different internal registers of up to 12 bits each. The input format is fixed with 4 bits of register address followed by 12 bits of data. Address and data are sent MSB first. The write procedure is fully synchronous with the clock rising edge of "sclk" and described in the following chronogram. "sld_n" and "sdata" are sampled on each rising clock edge of "sclk" (clock cycle). "sld_n" must be set at "1" when no write procedure is done. A write starts on the first clock cycle when "sld_n" is at "0". "sld_n" must stay at "0" during the complete write procedure. In the first 4 clock cycles with "sld_n" at "0", 4 bits of register address from MSB (a[3]) to LSB (a[0]) are entered. In the next 12 clock cycles with "sld_n" at "0", 12 bits of data from MSB (d[11]) to LSB (d[0]) are entered. This gives 16 clock cycles with "sld_n" at "0" for a normal write procedure. A minimum of one clock cycle with "sld_n" returned at "1" is requested to end the write procedure, before the interface is ready for a new write procedure. Any clock cycle with "sld_n" at "1" before the write procedure is completed interrupts this procedure and no data transfer to internal registers is done. It is possible to have only one clock cycle with "sld_n" at "1" between two following write procedures. Additional clock cycles with "sld_n" at "0" after the parallel data have been transferred to the register do not affect the write procedure and are ignored. 12 bits of data must always be sent, even if the internal addressed register has less than 12 bits. Unused bits (usually MSB's) are ignored. Bit signification and bit position for the internal registers are detailed in the section "Registers". The "reset_n" pin combined with the "sld_n" pin can be used as a reset to program the chip to the "reset setting". "reset_n" high: no effect "reset_n" low and "sld_n" low: programming of registers to default values 39 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 529. 3WSI Timing Diagram reset_n 1 2 3 4 5 11 12 13 14 15 16 sclk sld_n sdata Internal Previous Register setting Value d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] d[11] Default setting New Setting Timings related to 3WSI are given in the table below Table 57. 3WSI Timings Name Parameter Tsclk Period of sclk Twsclk High or low time of sclk Tssld_n Min Typ Max Unit 1 s 0.5 s Setup time of sld_n before rising edge of sclk 4 s Thsld_n Hold time of sld_n after rising edge of sclk 2 s Tssdata Setup time of sdata before rising edge of sclk 4 ns Thsdata Hold time of sdata after rising edge of sclk 2 ns Twlreset Minimum low pulse width of reset_n 5 ns Tdreset Minimum delay between an edge of reset_n and the rising edge of sclk 5 s Note 40 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 5.13.2 3WSI: Address and Data Description This 3WSI is activated with the control bit sld_n going low (please refer to "write timing" in next section). The length of the word is 16 bits: 12 for the data and 4 for the address. The maximum serial logic clock frequency is 1 MHz. Table 58. Registers Mapping Address Label Description Default Setting 0000 State Register MUX ratio Selection Output MODE selection IUCM ratio selection External Control for DSP Clock Reshaping Pulse Width (RPW) adjust Reshaping Pulse Begin (RPB) adjust 0x922 0001 GA Register Gain Adjust register 0x200 0010 Not available 0011 Not available 0100 Not available 0101 5.13.3 Table 59. D11 DSP Register PSS, OCDS controls 0110 Not available 0111 Not available 1000 to 1111 Not available 0x080 State Register (address 0000) State register Mapping (Address 0000) D10 D9 RPW<2:0> D8 D7 RPB<2:0> D6 D5 ECDC D4 D3 IUCM<1:0> D2 D1 MODE<1:0> D0 MUX 41 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Default value: 0x922 Table 510. State register Coding (Address 0000) Label Coding MUX D0 MODE<1:0> D2,D1 IUCM<1:0> D4,D3 ECDC RPB<2:0> RPW<2:0> D5 D8, D7, D6 D11, D10, D9 Default Value Description 0 4:1 MUX mode 1 2:1 MUX mode 00 NRZ mode 01 Narrow RTZ (a.k.a. NRTZ) mode 10 RTZ Mode 11 RF mode 00 IUCM1 (MUX at DAC core speed) 01 IUCM1 (MUX at DAC core speed) 10 IUCM2 (MUX at DAC core speed/2) 11 IUCM4 (MUX at DAC core speed/4) 0 OCDS and PSS ruled by DSP register at address 0101 1 OCDS and PSS externally controlled 000 RPB2 = 38 ps 001 RPB2 = 38 ps 010 RPB0 = 12 ps 011 RPB1 = 25 ps 100 RPB2 = 38 ps 101 RPB3 = 51 ps 110 RPB4 = 64ps 111 RPB2 = 38 ps 000 RPW2 66 ps in NRTZ mode / 68 ps in RF mode 001 RPW2 66 ps in NRTZ mode / 68 ps in RF mode 010 RPW0 43 ps in NRTZ mode / 52 ps in RF mode 011 RPW1 49 ps in NRTZ mode / 60 ps in RF mode 100 RPW2 66 ps in NRTZ mode / 68 ps in RF mode 101 RPW3 78 ps in NRTZ mode / 86 ps in RF mode 110 RPW4 100 ps in NRTZ mode / 110 ps in RF mode 111 RPW2 66 ps in NRTZ mode / 68 ps in RF mode Notes 0 (1) 01 (1) 00 (1) 1 (1)(2) 100 (3) 100 (4) 42 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Notes: 1. Default mode is 4:1 MUX, NRTZ output mode, IUCM1, and PSS & OCDS externally controlled. Default mode is programmed by power up reset or low level pulse on reset_n pin while sld_n pin is low. 2. ECDC: when ECDC is High the timing of the DSP clock is controlled externally through pins PSS<2:0> and OCDS; when ECDC is low, this functionality is controlled through the 3WSI by the DSP register at address 0101. 3. RPB setting is applicable in NRTZ, RTZ and RF modes. RPB values are design values. 4. RPW setting is applicable in NRTZ and RF modes. RPW values are typical values measured on one part. 5.13.4 Table 511. D11 GA Register (address 0001) GA register Mapping (Address 0001) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 GA<9:0> Default value: 0x200 5.13.5 Table 512. D11 DSP Register (address 0101) DSP register Mapping (Address 0101) D10 D9 D8 D7 D6 D5 D4 <reserved> PSS<2:0> OCDS Default value: 0x080 (OCDS = 0, PSS = 000) Table 513. Registers 0000 to 0101 Summary Address Description Default register value Default parameter value Register value for max value Parameter max value Register value for min value Parameter min value Step 0000 RPB Adjust 0x922 RPB2 0x9A2 RPB4 0x8A2 RPB0 1bit 0000 RPW Adjust 0x922 RPW2 0xD22 RPW4 0x522 RPW0 1bit 0000 ECDC 0x922 ECDC1 0x922 ECDC1 0x902 ECDC0 N/A 0000 IUCM 0x922 IUCM1 0x93A IUCM4 0x922 IUCM1 N/A 0000 MODE 0x922 NRTZ 0x926 RF 0x920 NRZ N/A 0000 MUX 0x922 4:1 MUX 0x923 2:1 MUX 0x922 4:1 MUX N/A 0001 Gain Adjust 0x200 1 0x3FF 1.15 0x000 0.85 300ppm 0101 PSS 0x080 PSS0 0x09C PSS7 0x080 PSS0 N/A 0101 OCDS 0x080 OCDS1 0x081 OCDS2 0x080 OCDS1 N/A 43 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 6. PIN DESCRIPTION Figure 61. A Pinout view fpBGA196 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DGND B5 B6 B6N B9 B9N B11 C11 C9N C9 C6N C6 C5 DGND B3 B4 B5N B7 B8 B10 B11N C11N C10 C8 C7 C5N C4 C3 B B B1N B3N B4N B7N B8N B10N DGND DGND C10N C8N C7N C4N C3N C1N C C B1 B2 B2N DGND DGND VCCD VCCD VCCD VCCD DGND DGND C2N C2 C1 D D A10N B0 B0N DGND DGND VCCD VCCD VCCD VCCD DGND DGND C0N C0 D10N E E A10 A11 A11N VCCD VCCD AGND AGND AGND AGND VCCD VCCD D11N D11 D10 F G H F A8 A8N A9 A9N DGND AGND AGND AGND AGND DGND D9N D9 D8N D8 A6 A6N A7 A7N DGND AGND AGND AGND AGND DGND D7N D7 D6N D6 A3N A5 D5 D3N A5N VCCA3 VCCA3 AGND AGND AGND AGND VCCA3 VCCA3 D5N J G H J A3 A4 A4N DGND DGND AGND VCCA5 VCCA5 AGND DGND DGND D4N D4 D3 K K A1N A2 A2N DGND Diode VCCA5 VCCA5 VCCA5 VCCA5 DGND sldn D2N D2 D1N L L A1 A0N NC TVF reset_n VCCA5 VCCA5 AGND AGND sdata sclk PSS2 D0N D1 M M A0 DSPN IDC_P SYNCN CLKN AGND AGND AGND AGND AGND AGND iref_test OCDS D0 N N DGND DSP IDC_N SYNC CLK AGND AGND AGND OUT OUTN AGND PSS0 PSS1 DGND P P 1 Table 61. A 2 3 4 5 6 7 8 9 10 11 12 13 14 Pinout Table fpBGA196 Signal name Pin number Description Direction VCCA5 K7, K8, L6, L7, L8, L9, M6, M7 5.0V analog power supplies Referenced to AGND N/A VCCA3 J4, J5, J10, J11 3.3V analog power supply Referenced to AGND N/A VCCD D6, D7, D8, D9, E6, E7, E8, E9, F4, F5, F10, F11 3.3V digital power supply Referenced to DGND N/A Equivalent Simplified schematics Power supplies 44 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 61. Pinout Table fpBGA196 (Continued) Signal name Pin number Description Direction AGND F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9, K6, K9, M8, M9, N6, N7, N8, N9, N10, N11, P6, P7, P8, P11 Analog Ground N/A DGND A1, A14, C7, C8, D4, D5, D10, D11, E4, E5, E10, E11, G5, G10, H5, H10, K4, K5, K10, K11, L4, L10, P1, P14 Digital Ground N/A Equivalent Simplified schematics Clock signals CLKN CLK CLKN P5 N5 Master sampling clock input (differential) with internal common mode at 2.5V It should be driven in AC coupling. Equivalent internal differential 100 input resistor. VCCD 50 3.2K I 2.5V 50 CLK 10K AGND 3.75 pF AGND VCCD DSP DSPN P2 N2 Output clock (in-phase and inverted phase) if not used, should be 100 terminated DSPN O DSP 3.625mA DGND 45 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 61. Pinout Table fpBGA196 (Continued) Signal name Pin number Description Direction Equivalent Simplified schematics Analog output signal VCCA5 50 OUT OUTN P9 P10 In phase and inverted phase analog output signal (differential termination required) O OUT OUTN Current witches AGND Digital Input signals VCCD A0, A0N A1, A1N A2, A2N A3, A3N A4, A4N A5, A5N A6, A6N A7, A7N A8, A8N A9, A9N A10, A10N A11, A11N N1, M2 M1, L1 L2, L3 K1, J1 K2, K3 J2, J3 H1, H2 H3, H4 G1, G2 G3, G4 F1, E1 F2, F3 20.4 K IN Differential Digital input Port A Data A0, A0N is the LSB Data A11, A11N is the MSB 50 K V CC3= 3.3V I 1.25V AGND 3.75 pF 50 2K GND INN 12.4 K DGND B0, B0N B1, B1N B2, B2N B3, B3N B4, B4N B5, B5N B6, B6N B7, B7N B8, B8N B9, B9N B10, B10N B11, B11N E2, E3 D1, C1 D2, D3 B1, C2 B2, C3 A2, B3 A3, A4 B4, C4 B5, C5 A5, A6 B6, C6 A7, B7 Differential Digital input Port B Data B0, B0N is the LSB Data B11, B11N is the MSB I 46 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 61. Pinout Table fpBGA196 (Continued) Signal name Pin number Description C0, C0N C1, C1N C2, C2N C3, C3N C4, C4N C5, C5N C6, C6N C7, C7N C8, C8N C9, C9N C10, C10N C11, C11N E13, E12 D14, C14 D13, D12 B14, C13 B13, C12 A13, B12 A12, A11 B11, C11 B10, C10 A10, A9 B9, C9 A8, B8 Differential Digital input Port C Data C0, C0N is the LSB Data C11, C11N is the MSB Direction Equivalent Simplified schematics I VCCD D0, D0N D1, D1N D2, D2N D3, D3N D4, D4N D5, D5N D6, D6N D7, D7N D8, D8N D9, D9N D10, D10N D11, D11N N14, M13 M14, L14 L13, L12 K14, J14 K13, K12 J13, J12 H14, H13 H12, H11 G14, G13 G12, G11 F14, E14 F13, F12 20.4 K IN Differential Digital input Port D Data D0, D0N is the LSB Data D11, D11N is the MSB 50 K V CC3 = 3.3V I 1.25V AGND 3.75 pF 50 2K GND INN 12.4 K DGND Control signals VCCD 10.2 K SYNCN SYNC, SYNCN P4 N4 In phase and Inverted phase reset signal 50 K 1.25V VCC3 I AGND 50 2K 3.75 pF GND SYNC 6.2 K DGND 47 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 61. Pinout Table fpBGA196 (Continued) Signal name Pin number Description Direction Equivalent Simplified schematics VCCD 20.4 K IN IDC_P, IDC_N N3 P3 50 K Input data check 1.25V VCC3 = 3.3V I AGND 3.75 pF 50 2K GND INN 12.4 K DGND sdata M10 3WSI serial data input. sclk M11 3WSI clock. reset_n M5 Reset for the 3WSI registers I VCCD 8 K 8 K 28.14 K ~3.2V 14 K ~1.6V INP sld_n L11 3WSI serial load enable input. 20 K 320nA 32uA 320nA GND OCDS N13 Output Clock Division Select I Driven by resistor: 10 or 10 K Driven by voltage: <0.5 V or > 2 V VCC3 13 k P12 P13 M12 PSS0 PSS1 PSS2 8 k 8 k Phase Shift Select (PSS2 is the MSB) 20 k IN 8 k 200 Vp 33 k 4 k DGND 48 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table 61. Signal name Pinout Table fpBGA196 (Continued) Pin number Description Direction Equivalent Simplified schematics VCCD 10 K VCCD 1 K 100uA / 0A TVF M4 Setup/Hold time violation flag TVF O 0uA / 100A 500 10 K DGND Diode L5 Diode for die junction temperature monitoring I Iref test N12 Bandgap output for test purpose. To leave unconnected O NC M3 Not connected DGND 49 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7. 7.1 7.1.1 CHARACTERIZATION RESULTS Static performances INL/DNL Figure 71. 7.1.2 INL & DNL measurements at Fout = 100kHz, Fclock = 3GHz DC Gain Figure 72. Output Voltage variations versus Gain Adjust 50 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 73. 7.2 7.2.1 Output voltage variation vs Power supplies & temperature vs Gain Adjust AC performances Available Output Power vs Fout. NRZ mode offers max power for 1st Nyquist operation. NRTZ mode offers optimum power over full 1st and first half of 2nd Nyquist zones. RTZ mode offers slow roll off for 2nd Nyquist operation. RF mode offers maximum power over 2nd and 3rd Nyquist operation. 51 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 74. Pout vs Fout from 45MHz to 6705MHz in the 4 output modes at 4.5 GSps in MUX4:1 Pout = f(Fout) @4.5GSps - MUX4:1 0 Pout vs Fout from 32MHz to 4768MHz in the 4 output modes at 3.2 GSps in MUX2:1 Pout = f(Fout) @3.2GSps - MUX2:1 0 -5 -5 -10 -10 -15 -15 -20 NRZ -25 NRTZ RTZ -30 Pout (dBm) Pout (dBm) Figure 75. -20 NRZ -25 NRTZ RTZ -30 RF RF -35 -35 -40 -40 -45 -45 1st Nyquist 1st Nyquist 3rd Nyquist 2nd Nyquist -50 Figure 77. Pout=f(Fout) vs Fc (NRZ mode) - MUX4:1 Pout=f(Fout) vs Fc (NRTZ mode) - MUX4:1 -5 -10 -10 -15 -20 NRZ - 4.5GSps -25 NRZ - 4.1GSps Pout (dBm) -15 Pout (dBm) Pout vs Fout from 45MHz to 6705MHz and from 3.7 GSps to 4.5 GSps in NRTZ mode in MUX4:1 0 -5 -20 NRTZ - 4.5GSps -25 NRTZ - 4.1GSps NRTZ - 3.7GSps NRZ - 3.7GSps -30 -30 -35 -35 -40 -40 -45 7000 6500 6000 5500 5000 Pout vs Fout from 45MHz to 6705MHz and from 3.7 GSps to 4.5 GSps in RF mode in MUX4:1 Pout=f(Fout) vs Fc (RF mode) - MUX4:1 0 -5 -10 -10 -15 -15 -20 RTZ - 4.5GSps RTZ - 4.1GSps RTZ - 3.7GSps Pout (dBm) -5 -30 4500 Figure 79. Pout=f(Fout) vs Fc (RTZ mode) - MUX4:1 -25 4000 Pout vs Fout from 45MHz to 6705MHz and from 3.7 GSps to 4.5 GSps in RTZ mode in MUX4:1 0 3500 Fout (MHz) Fout (MHz) Figure 78. 3000 2500 2000 1500 1000 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 500 0 -45 Pout (dBm) 5000 4500 4000 3500 3000 Fout (MHz) Pout vs Fout from 45MHz to 6705MHz and from 3.7 GSps to 4.5 GSps in NRZ mode in MUX4:1 0 2500 2000 1500 1000 500 0 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Fout (MHz) Figure 76. 3rd Nyquist 2nd Nyquist -50 -20 RF - 4.5GSps -25 RF - 4.1GSps RF - 3.7GSps -30 -35 -35 -40 -40 -45 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Fout (MHz) -45 Fout (MHz) 52 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.2 Single Tone Measurements The following plots summarize characterization results in MUX4:1 mode, for an Fout sweep from 45 MHz to 6705 MHz (step 100 MHz). The following plots summarize characterization results in MUX2:1 mode, for an Fout sweep from 32 MHz to 4768 MHz (step 100 MHz). Figure 711. SFDR in the 4 output modes at 3.2 GSps in Figure 710. SFDR in the 4 output modes at 4.5 GSps in MUX4:1 80 SFDR @3.2GSps - MUX2:1 80 70 70 60 60 50 50 NRTZ 40 NRZ RTZ 30 SFDR (dBc) SFDR (dBc) MUX2:1 SFDR @4.5GSps - MUX4:1 NRTZ 40 NRZ RTZ 30 RF RF 20 20 10 10 1st Nyquist 1st Nyquist 3rd Nyquist 2nd Nyquist 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Fout (MHz) Fout (MHz) 7.2.3 3rd Nyquist 2nd Nyquist 0 0 Single tone measurements: typical spectra The following figures show typical SFDR spectra obtained for the four DAC modes on an EV12DS400A device. Conditions: typical power supplies, ambient temperature, MUX4:1 with Fs = 4.5 GSps or MUX2:1 with Fs= 3.2 GSps. 7.2.3.1 Figure 712. MUX 4:1 Typical SFDR spectrum in NRZ mode. Fout = 45MHz (1st Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 67dBc Figure 713. Typical SFDR spectrum in NRTZ mode. Fout = 45MHz (1st Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 73 dBc 53 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 714. Typical SFDR spectrum in NRTZ mode. Fout = 2205MHz (1st Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 60 dBc Figure 715. Typical SFDR spectrum in RTZ mode. Fout = 4455MHz (2nd Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 53 dBc Figure 716. Typical SFDR spectrum in RF mode. Fout = 4455MHz (2nd Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 58 dBc Figure 717. Typical SFDR spectrum in RF mode. Fout = 6705MHz (3rd Nyquist), MUX4:1, Fs = 4.5 GSps. SFDR = 52 dBc 54 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.3.2 MUX 2:1 Figure 718. Typical SFDR spectrum in NRZ mode. Fout = 32MHz (1st Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 70 dBc Figure 719. Typical SFDR spectrum in NRTZ mode. Fout = 32MHz (1st Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 76 dBc Figure 720. Typical SFDR spectrum in NRTZ mode. Fout = 1568MHz (1st Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 65 dBc Figure 721. Typical SFDR spectrum in RTZ mode. Fout = 3168MHz (2nd Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 59 dBc 55 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 722. 7.2.3.3 Typical SFDR spectrum in RF mode. Fout = 3168MHz (2nd Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 58 dBc Figure 723. Typical SFDR spectrum in RF mode. Fout = 4768MHz (3rd Nyquist), MUX2:1, Fs = 3.2 GSps. SFDR = 53 dBc Figure 725. SFDR vs Temperature MUX 2:1 @ 3.2 GSps MUX 4:1 @ 4.5 GSps SFDR vs Power supplies & Temperature Figure 724. SFDR vs Power supplies MUX 2:1 @ 3.2 GSps MUX 4:1 @ 4.5 GSps 56 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.4 Multi Tone Measurements 7.2.4.1 Dual Tones Figure 726. Observation of the 1st Nyquist Zone: NRTZ Mode. Fout1: 2000MHz, -8dBFS, Fout2: 2010MHz, -8dBFS Figure 727. Observation of the 2nd Nyquist Zone: RF Mode Figure 728. Observation of the 3rd Nyquist Zone: RF Mode 57 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.4.2 Multi tones A twenty two tones pattern (100 MHz to 2200MHz with a step of 100MHz) is applied to the DAC operating at 4.5 GSps and results are observed in the 1st, 2nd and 3rd Nyquist zones. Figure 729. Observation of the 1st and 2nd Nyquist Zones: NRTZ Mode 60dBc Dynamic Highest spur < 95dBm 48dBc Dynamic Highest spur < 97dBm Figure 730. Observation of the 2nd and 3rd Nyquist Zones: RF Mode 52dBc Dynamic Highest spur < 92dBm Highest spur < 95dBm 47dBc Dynamic 58 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.5 ACPR measurements Measured in NRTZ mode. Fc=4.5GHz. Channel width = 6 MHz Figure 731. 1 channel ACPR. Center frequency: 954MHz Figure 732. 1 channel ACPR versus channel center frequency (100MHz to 2000MHz) ACPR vs Frequency 1 channel 55.0 57.5 60.0 ACPR (dBc) 62.5 65.0 Lower Adj 67.5 Lower Alt1 Lower Alt2 70.0 Lower Alt3 72.5 Upper Adj 75.0 Upper Alt1 77.5 Upper Alt2 Upper Alt3 80.0 82.5 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 900 1000 800 700 600 500 400 300 200 0 100 85.0 Channel center frequency (MHz) Figure 733. 4 channels ACPR. 1st channel center frequency: 954MHz Figure 734. 4 channels ACPR versus 1st channel center frequency (100MHz to 2000MHz) 59 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 735. 8 channels ACPR. 1st channel center frequency: 954MHz Figure 736. 8 channels ACPR versus 1st channel center frequency (100MHz to 2000MHz) ACPR vs Frequency 8 Channels 55.0 57.5 60.0 ACPR (dBc) 62.5 65.0 Lower Adj 67.5 Lower Alt1 Lower Alt2 70.0 Lower Alt3 72.5 Upper Adj 75.0 Upper Alt1 77.5 Upper Alt2 Upper Alt3 80.0 82.5 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 900 1000 800 700 600 500 400 300 200 0 100 85.0 1st channel center frequency (MHz) 7.2.6 7.2.6.1 NPR performance NPR vs Loading Factor (LF) NPR pattern covers a 2GHz bandwidth (125MHz to 2125MHz) with a 25MHz notch width centered at 1100MHz. Figure 7-37 shows NPR evolution versus loading factor. Optimum NPR value is achieved for LF = -14dBFS. Figure 737. NPR versus loading factor @4.5 GSps 60 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.6.2 NPR vs Mode NPR measurements have been carried out at optimum loading factor (LF) for a 12 bit DAC, that is -14 dBFS, with the DAC operating at 4.5 GSps. SNR can be computed from NPR measurement with the formula: SNR[dB] = NPR[dB] + ILF[dB]I - 3. ENOB can be computed with the formula: ENOB = (SNR[dB] - 1.76) / 6.02. Figure 738. NPR in 1st Nyquist Zone, 125 MHz to 2125 MHz Noise Pattern with a 25 MHz Notch Centered on 1100 MHz, NRTZ mode Measured average NPR: 47.5 dB, therefore SNR = 58.5 dB and ENOB = 9.4bit NPR = 47.5dB Notch power = 88dBm Figure 739. NPR in 2nd Nyquist Zone, 2400 MHz to 4400 MHz Noise Pattern with a 25 MHz Notch Centered on 3400 MHz, NRTZ mode. Measured average NPR: 42.0 dB, therefore SNR = 50.0 dB and ENOB = 8.5bit NPR = 47.5dBc NPR = 42dB Notch power = 88dBm Notch power = 89dBm 61 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 740. NPR in 2nd Nyquist Zone, 2400 MHz to 4400 MHz Noise Pattern with a 25 MHz Notch Centered on 3400 MHz, RF mode. Measured average NPR: 39.0 dB, therefore SNR = 50.0 dB and ENOB = 8.0bit NPR = 39dB Notch power = 84dBm Figure 741. NPR in 3rd Nyquist Zone, 4600 MHz to 6600 MHz Noise Pattern with a 25 MHz Notch Centered on 5600 MHz, RF mode. Measured average NPR: 38.5 dB, therefore SNR = 49.5 dB and ENOB = 7.9bit NPR = 38.5dB Notch power = 86dBm 62 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7.2.6.3 NPR vs Power supplies & Temperature Figure 742. NPR vs power supply for the 4 output modes at room temperature. min: VCCA5: 4.75V // VCCA3 = VCCD = 3.15V; Typ: VCCA5: 5.00V // VCCA3 = VCCD = 3.30V; MAX: VCCA5: 5.25V // VCCA3 = VCCD = 3.45V 7.3 Figure 743. NPR versus temperature at 4.5 GSps in 4:1 MUX for the 4 output modes from Tc = -40C to Tc = 75C (Tj = -9C to 115C) Input Data Setup and Hold time vs Input Data Rate The figure below shows tSH variation versus input data rate. Figure 744. tSH vs input data rate 63 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 8. 8.1 APPLICATION INFORMATION Analog output (OUT/OUTN) The analog output should be used as a differential signal, as described in the figures below. If the application requires a single-ended analog output, then a balun is necessary to generate a single ended signal from the differential output of the DAC. Figure 81. Analog output differential termination MUXDAC Receiver VCCA5 50 100 nF OUT 50 lines OUTN 50 lines 100 nF 50 Current switches and sources AGND Figure 82. Note: AGND Analog output using a 1/sqrt(2) Balun The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the application. 64 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 8.2 Clock Input (CLK/CLKN) The DAC input clock (sampling clock) should be provided as a differential signal as described in the following figures: Figure 83. Clock input differential termination 100 Note: The buffer is internally pre-polarized to 2.5V (buffer between VCCA5 and AGND). Figure 84. Clock input differential with balun The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the application). 65 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 8.3 Digital Data, SYNC and IDC inputs LVDS buffers are used for the digital input data, the SYNC signal (active high) and the IDC signal. They are all internally terminated by 2 x 50 to ground via a 3.75 pF capacitor. Figure 85. Digital data, SYNC and IDC input differential termination DAC Data and Sync Input Buffer 50 line InN 50 1.25V LVDS Output Buffer 50 3.75 pF In 50 line DGND Notes: 1. In the case when only two ports are used (2:1 MUX ratio), then the unused data can be left floating (unconnected). 2. Data and IDC signals should be routed on board with the same layout rules and the same length than the data 3. In case the SYNC is not used, it is recommended to bias the SYNC to 1.1V and SYNCN to 1.4V. 8.4 DSP Clock The DSP, DSPN output clock signals are LVDS compatible. If DSP is not used, they have to be terminated via a differential 100 termination as described in the following figure: Figure 86. DSP output differential termination DAC Output DSP Z0 = 50 DSP Differential Output buffers 100 Termination To Load Z0 = 50 DSPN 66 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 8.5 Control signal settings The PSS and OCDS control signals use the same static input buffer. Logic `1' = 200 K to Ground, or tied to VCCD = 3.3V or left open Logic `0' = 10 to Ground or Grounded Figure 87. Control signal output differential termination Control Signal Pin 10 Control Signal Pin 200 K GND Not Connected Control Signal Pin GND Inactive High Level (`1') Active Low Level (`0') The control signals can be driven by an FPGA. Figure 88. Control signal settings with FPGA FPGA Control Signal Pin Logic "1" > VIH or VCCD = 3.3V Logic "0" < VIL or 0V 8.6 TVF Control signal The TVF control signal is a 3.3V CMOS output signal. This signal could be acquired by FPGA. Figure 89. Control signal settings with FPGA FPGA TVF Control Signal In order to modify the VOL/VOH value, pull up and pull down resistor or a potential divider could be used. 8.7 Power Supply Decoupling and Bypassing The DAC requires 3 distinct power supplies: VCCA5 = 5.0V (for the analog core) VCCA3 = 3.3V (for the analog part) VCCD = 3.3V (for the digital part) It is recommended to decouple all power supplies to ground as close as possible to the device balls with 100 pF in parallel to 10nF capacitors. The minimum number of decoupling pairs of capacitors can be calculated as the minimum number of groups of neighbouring pins. 4 pairs of 100pF in parallel to 10 nF capacitors are required for the decoupling of VCCA5. 4 pairs for the VCCA3 and 10 pairs are necessary for VCCD. 67 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Figure 810. Power Supplies Decoupling Scheme EV12DS400 VCCA5 B 100 pF X 4 (min) 10 nF AGND VCCD B B 100 pF 10 nF VCCA3 B X 10 (min) DGND B 100 pF X 4 (min) 10 nF AGND Each power supply has to be bypassed as close as possible to its source and accessed by 100 nF in parallel to 22 F capacitors (the optimum value depends on the regulators). 8.8 Power on/off requirement and power on reset function The DAC timing circuitry must be reset either by a power on reset (see below) or through the use of the SYNC input to set it to the right state. Refer to Section 5.10. At power-up a reset pulse is internally and automatically generated when the following sequence is satisfied: VCCD, VCCA3 then VCCA5. This pulse has two effects: * Resetting of the 3WSI interface registers to their default values. * Synchronizing the timing circuitry. To cancel the SYNC pulse at power-up, it is necessary to apply the sequence: VCCA5 then VCCA3 and VCCD. Any other sequence may not have a deterministic SYNC behaviour but can be used. There is no specific requirement to power down the device. 68 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 9. 9.1 PACKAGE DESCRIPTION fpBGA 196 Outline 69 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 9.2 Thermal Characteristics Assumptions: * Still air * Pure conduction * No radiation * Heating zone = 8.9% of die surface Rth Junction - bottom of Balls = 13C/W Rth Junction - board (JEDEC JESD-51-8) = 17.3C/W Rth Junction - top of case = 14C/W Assumptions: * Heating zone = 8.9% of die surface * Still air, JEDEC condition Rth Junction - ambient (JEDEC) = 32.0 C/W The hot spot point is 6C above the temperature given by the diode 10. ORDERING INFORMATION Table 101. Ordering Information Part Number Package Temperature Range Screening Level Comments EVX12DS400AZPY FpBGA196 RoHS Ambient General Sample Prototype EV12DS400ACZPY FpBGA196 RoHS 0C < Tc, Tj < 90C Commercial "C" Grade EV12DS400AVZPY FpBGA196 RoHS -40C < Tc, Tj < 110C Industrial "V" Grade EV12DS400AMZPY FpBGA196 RoHS -55C < Tc, Tj < 125C Military "M" Grade EV12DS400ACZP FpBGA196 0C < Tc, Tj < 90C Commercial "C" Grade EV12DS400AVZP FpBGA196 -40C < Tc, Tj < 110C Industrial "V"Grade EV12DS400AMZP FpBGA196 -55C < Tc, Tj < 125C Military "M" Grade Refer to datasheet 1163 EV12DS4xxAZPY-EB FpBGA196 RoHS Ambient Prototype Evaluation Board Refer to datasheet 1163 70 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 11. REVISION HISTORY This table provides revision history for this document. Table 111. Rev. No Revision History Date Substantive Change(s) July 2017 Update of Figure 8-1 on AOUT Section 5.8: Clarification about the usage of TVF Section 3.3, Section 3.4 and Section 3.5: Master clock input jitter is integrated over 11GHz bandwidth. Table 5-10: clarification about MSB/LSB labels Figure 8-3: differential sinewave source is 100 and not 50 March 2016 Update note 10 on Table 3-3 about DSP clock output swing and common mode Table 3-5 to Table 3-7: Remove lines about SFDR and NPR variations versus temperature and supplies and add reference to figures of Section 7. Table 3-8: add lines about pipeline delay on analog output Table 3-8: add note 3 about setup and hold time. Figure 5-17 and Figure 5-18: correct typo about DSP with PSS [111] Table 5-10: add RPB and RPW values + note about RPB and RPW settings Table 6-1: remove note about AGND and DGND planes. Table 6-1: add note about DSP clock that needs to be 100 terminated. Add Section 7.3 about tSH versus input data rate Section 8.4: DSP needs to be 100 terminated even if not used. Section 8.7: Remove note about AGND & DGND grand planes Update of Figure 7-25 about SFDR vs temperature Update of Figure 7-43 about NPR vs temperature November 2015 Final datasheet update: - Add note 10 about DSP clock swing in Table 3-3 - Add parameters t1 and t2 tin Table 3-8 - Add Figure 3-4 (SYNC timing diagram) - Update timing diagram vs output modes (Figure 5-4, Figure 5-5, Figure 5-6, Figure 5-7) - Add Section 7. Characterization results - Add Military grade version in Section 10. Ordering information 1130B September 2015 Table 3-3, Table 3-4, Table 3-5, Table 3-6, Table 3-7: Add min and max limits and update typical values Complete missing values of revision A Table 5-10 and Table 5-13: replace numerical values of RPB and RPW by RPB1, RPW1... 1130A May 2015 Initial Revision 1130E 1130D 1130C 71 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 72 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP Table of Contents MAIN FEATURES ...................................................................................... 1 PERFORMANCES ..................................................................................... 1 1 Block Diagram .......................................................................................... 2 2 Description ............................................................................................... 2 3 Electrical characteristics ........................................................................ 3 3.1 Absolute Maximum ratings ....................................................................................... 3 3.2 Recommended conditions of use ............................................................................. 4 3.3 DC Electrical Characteristics .................................................................................... 5 3.4 AC Electrical Characteristics .................................................................................... 7 3.5 Timing Characteristics and Switching Performances ............................................. 14 3.6 Explanation of Test Levels ..................................................................................... 17 3.7 Digital Input Coding Table ...................................................................................... 17 4 Definition of Terms ................................................................................ 18 5 Functional Description .......................................................................... 19 5.1 Multiplexer .............................................................................................................. 20 5.2 Mode Function ........................................................................................................ 21 5.3 RPW and RPB Feature .......................................................................................... 25 5.4 Phase Shift Select function (PSS) .......................................................................... 30 5.5 Output Clock Division Select function (OCDS) ....................................................... 31 5.6 Input Under Clocking Mode (IUCM) ....................................................................... 32 5.7 Synchronization FPGA-DAC: IDC_P, IDC_N and TVF function ............................ 34 5.8 DSP output clock .................................................................................................... 36 5.9 OCDS, IUCM and MUX combinations summary ....................................................36 5.10 Synchronisation function ...................................................................................... 37 5.11 Gain Adjust function ............................................................................................. 37 5.12 Diode function ...................................................................................................... 38 5.13 DAC 3WSI Description (DAC Controls) ................................................................ 39 6 Pin Description ...................................................................................... 44 i 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017 EV12DS400AZP 7 CHARACTERIZATION RESULTS .......................................................... 50 7.1 Static performances ............................................................................................... 50 7.2 AC performances ................................................................................................... 51 7.3 Input Data Set-up and Hold time vs Input Data Rate ............................................. 63 8 Application information ........................................................................ 64 8.1 Analog output (OUT/OUTN) ................................................................................... 64 8.2 Clock Input (CLK/CLKN) ........................................................................................ 65 8.3 Digital Data, SYNC and IDC inputs ........................................................................ 66 8.4 DSP Clock .............................................................................................................. 66 8.5 Control signal settings ............................................................................................ 67 8.6 TVF Control signal .................................................................................................. 67 8.7 Power Supply Decoupling and Bypassing .............................................................. 67 8.8 Power on/off requirement and power on reset function .......................................... 68 9 Package Description ............................................................................. 69 9.1 fpBGA 196 Outline ................................................................................................. 69 9.2 Thermal Characteristics ......................................................................................... 70 10 Ordering Information ............................................................................. 70 11 Revision History .................................................................................... 71 ii 1130E-BDC-07/17 Teledyne e2v Semiconductors SAS 2017