CY7C43684-12AC - Cypress Semiconductor

PRELIMINARY

256/512/1K/4K/16K x36 x2 Bidirectional

Synchronous FIFO w/ Bus Matching

CY7C43624

CY 7C43634/CY7C43644

CY7C43664/CY7C43684

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

October 6

1998

Features

• High-speed, low-power, bidirecti onal, first-in fi rst-out

(FIFO) memories w/ bus matching capabilities

• 256x36x2 (CY7C43624)

• 512x36x2 (CY7C43634)

• 1Kx36x2 (CY7C43644)

• 4Kx36x2 (CY7C43664)

• 16Kx36x2 (CY7C43684)

• 0.35-micr on CMOS for optimum speed/power

• High-speed 83-MHz operation (12 ns re ad/write cycle

times)

• Low power

—ICC= 100 mA

—ISB= 5 mA

• Fully asynchronous and simultaneous read and write

operati on permitted

• M ailbox bypass register f or each FIFO

• Parallel and Serial Pr ogrammabl e Almost- Full and Al-

most-Empty flags

• Retransmit function

• Standard or FWFT mode user sel ectable

• Partial Reset

• Big or little Endian format for word or byte bus sizes

• 128-pin TQFP packaging

• Pin-compatibl e, f eature enhanced, densi ty upgrade to

IDT723624/34/44 f amily

• Easil y expandable in widt h and depth

Logic Block Diagra m

Port-A

Control

Logic Port-B

Control

Logic

Mail 1

Input

Write

Pointer Read

Pointer

Status

Flag Logic

Programmable Flag

Offset Registers Timing

Mode

Status

Flag Logic

Write

Pointer Read

Pointer

256/512/1K

4K/16K x36

Dual Ported

Memory

256/512/1K

4K/16K x36

Dual Ported

Memory

Mail 2

Output

Input

FIFO1,

Mail 1

Reset

Logic

FIFO1,

Mail 1

Reset

Logic

CLKA

CSA

W/RA

ENA

MBA

RT2

MRS1

PRS1

FFA/IRA

AFA

SPM

FS0/SD

FS1/SEN

A0–35

EFA/ORA

AEA

MBF2

MRS2

PRS2

FFB/IRB

AFB

BE/FWFT

B0–35

CLKB

CSB

W/RB

ENB

MBB

RTI

SIZE

EFB/ORB

AEB

MBF1

Output

B us M at c hing

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

CY7C43624

CY7C43634

CY7C43644

CY7C43664

CY7C43684

TQFP

Top View

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

FS0/SD

MRS2

FS1/SEN

GND

MRS1

MBA

MBF2

AEA

AFA

VCC

PRS1

EFA/ORA

FFA/IRA

CSA

ENB

W/RB

CSB

GND

FFB/IRB

EFB/ORB

AFB

AEB

VCC

MBF1

MBB

102

101

100

B30

B26

B27

B28

B29

B31

GND

B32

B33

B34

B35

VCC

PRS2

CLKB

GND

SIZE

B16

B17

B18

B19

B20

B21

B22

B23

GND

B24

B25

RT1

GND

VCC

SPM

GND

VCC

GND

VCC

A29

GND

A30

A31

A32

A34

A35

GND

CLKA

ENA

W/RA

A12

A20

GND

A18

A19

A21

VCC

A22

GND

BE/FWFT

A23

A24

A25

A26

A27

A28

A33

B12

B10

B11

GND

B13

B14

B15

VCC

RT2

A10

A11

GND

A13

A14

A15

A16

A17

Pin Configuration

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Functional Description

The CY7C436X4 is a monolithic, high-speed, low-power,

CMOS Bidirectional Synchronous (clocked) FIFO memory

which supports cl ock frequencies up to 83 MHz and has read

access times as fast as 9 ns. Two independent

256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board

each c hip buf f er d ata in opp osite direc tions . FIFO dat a o n P ort

B can be input and output in 36-bi t, 18-bit, or 9-bit f ormats with

a choice of bi g- or li tt le-endia n configurations.

The CY7C436X4 is a synchronous (clocked) FIFO, meaning

each port employs a synch ronous interface. All dat a transfers

through a port are gated to the LOW-to-HIGH transition of a

port clock by enable signals. The clocks for each por t ar e in-

dependent of one another and can be asynchronous or coin-

cident. The enables for each port are arranged to provide a

simpl e bidirec tiona l interf ace bet ween micropr ocessors and/ or

buses with sync hronous control.

Commu nicati on betw een eac h port ma y b ypas s the FIF Os vi a

two mailbox registers. The mailbox registers’ width matches

the sel ected P ort B bu s width. Each mailbo x register has a flag

(MBF1 and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436X4: Master

Reset and P artial Reset. Mast er Reset in iti aliz es the read and

write point ers to the first location of the memory arr ay, config-

ures the FIFO for big- or little-endian byte arrangement and

selects serial fl ag programming, par allel flag programm ing, or

one of the three possible default flag offset settings, 8, 16, or

64. Each FIFO has its own independent Master Reset pin,

MRS1 and MRS2.

Par tial Reset also sets the read and wri te pointers to the first

location of the memory. Unlike Master Reset, an y settings ex-

ist ing pri or to P artial Reset (i.e ., prog ramming method and par-

tial flag default offsets) are retained. Partial Reset is useful

sinc e it permits f lushi ng of th e FIFO m emory witho ut chang in g

any configuration settings. Each FIFO has its own, indepen-

dent Partial Reset pin, PRS1 and PRS2.

The CY7C436X4 have two modes of operation: In the CY

Standard Mode, the first wor d written to an empty FIFO i s de-

posited into the memory array. A read operation is requi red to

access that word (along with all other words residing in mem-

ory). In the First Word Fall Through Mode

(FWFT), the first

long-word (36-bi t wi de) written to an empty FIFO appe ars au-

tomatically on the out puts, no re ad operation required (never-

theless, accessing subsequent words does necessitate a for-

mal read reques t). The st ate of the BE/FWFT pi n during FIFO

operation determines the mode in use.

Each FIFO has a combined Empty/Output Ready flag

(EFA/ORA and EFB/ORB) and a combined Full/Input Ready

flag (FFA/IRA and FFB/IRB). The EF and FF functions are

selected in the CY Standard m ode. EF indicates whether the

memory is full or not . The IR and OR funct ions are se lected in

the First Word Fall Through mode. IR in dicates whether or not

the FIFO has availa ble memory locat ions. OR shows whether

the FIFO has data available for reading or not. It marks the

presence of vali d data on the out puts.

Each FIFO has a programmab le Almost Emp ty f lag (AEA and

AEB) and a programmable Almost Full flag (AFA and AFB).

AEA and AEB indicate when a selected number of words writ-

ten to FIFO memory achieve a predet ermined “almost empty

state.” AFA and AFB indicate when a selected number of

words wri tten to t he memory ac hie v e a pr edet ermined “a lmost

fu ll st a te. ”

IRA, IRB , AF A, and AF B are synchronized to the port clock that

writes data into its array. ORA, O RB, AEA, and AEB are syn-

chronized to the port clock that reads data fr om it s array. Pro-

grammable offset for AEA, AEB, A FA, and AFB are loaded in

paral lel using Port A or i n serial v ia the SD input . Thr ee d ef ault

offset setti ngs are also provided. The AEA and AEB threshold

can be set at 8, 16, or 64 locations from the empty boundary

and AFA and AFB threshold can be set at 8 , 16, or 6 4 locati ons

from the full boundary. All these choices are made using the

FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider

data paths. If at any ti me, the FIFO is not actively performing

a function, the chip will autom atically power down. During the

power-down state, supply current consumption (ICC) is at a

minimum . In iti ating any oper ati on ( by act iv at ing cont rol inputs )

will immediately take the device out of the power-down state.

Retransmit feature is avail able on thes e devices.

The CY7C436X4 are characterized for operation from 0°C to

70°C. Input ESD protect ion is gr eater t han 2001V, and latch-up

is prevented by the use of guard rings.

Selec tio n Guid e

CY7C43624/34/44/64/84–12 CY7C43624/34/44/64/84−15

Maximum Frequency (MHz) 83 66.7

Maximum Access Time (ns) 910

Minimum Cycle Time (ns) 12 15

Minimum Data or Enable Set-Up (ns) 4 5

Minimum Data or Enable Hold (ns) 0 0

Maxim u m Flag Delay ( n s) 8 8

Active Power Supply

Current (ICC1) ( m A ) Commercial 100 100

Industrial 100 100

CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684

Density 256 x 36 x2 512 x 36 x2 1K x 36 x2 4K x 36 x2 16K x 36 x2

Package 128 TQ FP 128 TQFP 128 TQFP 128 TQFP 128 TQFP

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Pin Definitions

Signal Name Description I/O Function

A0–35 Po rt A Data I/O 36-bit bidirectional data port for side A.

AEA Port A Almost

Empty Flag O Programmab le almost- em pty flag synchronized t o CLKA. It is LOW wh en the num ber

of words in FIFO2 is less than or equal to the value in the almost-empty A offset register,

X2.

AEB Port B Almost

Empty Flag O Programmab le almost-em pty flag synchroniz ed to CLKB. It is LOW when the number

of words in FIFO1 is less than or equal to the value in the almost-empty B offset register,

X1.

AFA Port A Almost

Full Flag O Programmabl e almost-full flag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the almost-full A offset

regist er, Y1.

AFB Port B Almost

Full Flag O Programmab le al m ost-full f lag synchroniz ed to CLKB . It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the almost-full B offset

regist er, Y2.

B0–35 Po rt B Data I/O 36-bit bidirectional data port for side B.

BE/FWFT Big Endian/First

Word F all

Through Select

I This is a du al-purpose pin. During Maste r Reset, a HIGH on BE will se lect Bi g Endian

operat ion. In thi s case, depending on the bus size , the most sig nificant byte or wor d on

Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data

flo w). A LO W on BE will select Little Endian operati on. In t his case, the least s ignif icant

byte or word on Port A is r ead from Port B first (for A-to-B data flow) or wri tten to Port

B fir st (B-to -A da ta flo w). After M aster Reset, this pin se lects the t iming m ode. A HIG H

on FWFT selects CY Standard mode, a LO W selects First W ord Fall Through m ode.

Once the t iming m ode has been se lected, the le vel on FWFT must be st atic thr oughout

device operation.

BM Bus Match

Select (Port A) I A HIGH on this pin enab les ei ther b yte or wor d bus widt h on P ort B, depen ding on the

state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to

select the bus size and endian arrangement f or Port B. The le vel of BM must be static

throughout device operation.

CLKA Port A Cloc k I CLKA is a c ontinuous clock t hat synchr onizes al l data t ransf ers thro ugh Port A and can

be asynchronous or coincident to CLKB. FFA/IR A , E FA/ORA, AFA, and AEA are all

synchronized to the LOW-to-HIG H transition of CLKA.

CLKB Port B Cloc k I CLKB is a c ontinuous clock t hat synchr onizes al l data t ransf ers thro ugh Port B and can

be asynchronous or coincident to CLKA. FFB/I R B, EF B /ORB, AFB, and AEB are all

synchronized to the LOW-to-HIG H transition of CLKB.

CSA Port A Chip

Select ICSA must be LOW to enable a LOW-t o HIGH transiti on of CLKA to r ead or write on

Port A. The A0–35 outputs are in the high-impedance state when CSA is HI GH.

CSB Port B Chip

Select ICSB must be LOW to enable a LOW-t o HIGH transiti on of CLKB to r ead or write on

Port B. The B0–35 out puts are in the high- impedance state when CSB is HI G H.

EFA/ORA Por t A Empty/

Output Ready

Flag

O This i s a dual- functi on pin. In the CY Standard mode, the EF A functi on is selected. EFA

indicat es whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

functi on is selected. ORA indi cates the presence of valid data on A0–35 outputs, avail-

able for reading. FFA / ORA is synchronized to the LOW-to-HIGH transition of CLKA.

EFB/ ORB Por t B Empty/

Output Ready

Flag

O This is a dual-function pin. In the CY Standard mode, the EFB function is selected. EFB

indicat es whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB

functi on is selected. ORB indi cates the presence of valid data on B0–35 outputs, avail-

able for reading. FFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.

ENA P ort A Enab le I ENA must be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKA t o read or writ e data

on P ort A.

ENB P ort B Enab le I ENB must be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKB t o read or writ e data

on P ort B.

FFA/IRA Port A Full/Input

Ready Flag O This i s a dual-function pi n. In t he CY Standard mod e, the FF A functi on is selected. FF A

indicates whet her or not the FIFO1 memory is full . In the FWFT mode , the IRA funct ion

is selected. IRA indicates whether or not there is space available for writing to the FIFO1

memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

FFB/IRB Port B Full/Input

Ready Flag O This i s a dual- functi on pin. In the CY St andard mode, the FFB function is selected. FFB

indicates whet her or not the FIFO2 memory is full . In the FWFT mode , the IRB funct ion

is selected. IRB indicates whether or not there is space available for writing to the FIFO2

memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

FS1/SEN Flag Offset

Select 1/ Seri al

Enable

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program -

ming. During M aster Re set, FS1/ SEN and FS0/SD, together with SPM , sel ect the fl ag

offset programming method. Three offset register programming methods are available:

automatically lo ad one of three pr eset val ues (8, 16, or 64), parallel load from Port A,

and serial load. Whe n serial load is selected for flag offset register programming,

FS1/SEN is used as an enable synchronous to the LOW-to-H IGH transition of CLKA.

W hen FS 1/ S E N is LOW, a rising edge on CLKA load the bit present on FS0/SD into

the X and Y register s. The number of bit writes requ ired to prog ram the offse t regis ters

is 32 for the CY7C43624, 36 for the CY7C43634, 40 for the CY7C43644, 48 for the

CY7C43664, and 56 for the CY7C43684. The first bit writ e stores the Y-regi ster MSB

and the last bit writ e stores the X-regi ster LSB.

FS0/SD Flag Off set

Select 0/ Seri al

Data

M BA Port A M ail b ox

Select I A HIGH le vel on MBA chooses a mailbo x register for a Port A read or write operation.

When the A 0–35 outputs are active, a HIGH level on MBA selects data from th e Mail2

regist er for outpu t and a LOW level sel ects FIFO2 output register data for output.

M BB Port B M ail b ox

Select I A HIGH le vel on MBB chooses a mailbo x register for a Port B read or write operation.

When the B 0–35 outputs are active, a HIGH level on MBB selects data from th e Mail1

regist er for outpu t and a LOW level sel ects FIFO1 output register data for output.

MBF1 Mail 1 Register

Flag OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA tha t writes data to the Mail1

regist er. Writes to t he Ma il 1 register are i nhibited whil e M B F1 is LOW. MBF1 is set

HIGH by a LOW-to-HI GH tra nsiti on of CLKB when a Po rt B read is select ed and MBB

is HIGH. MBF1 is set HIGH foll owing eit her a Master or P artial Reset of FI FO 1.

MBF2 Mail 2 Register

Flag OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB tha t writes data to the Mail2

regist er. Writes to t he Ma il 2 register are i nhibited whil e M B F2 is LOW. MBF2 is set

HIGH by a LOW-to-HI GH tra nsiti on of CLKA when a Po rt A read is select ed and MBA

is HIGH. MBF2 is set HIGH foll owing eit her a Master or P artial Reset of FI FO 2.

MRS1 FIFO1 Master

Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects

the programming method (serial or parallel) and one of three programmable flag default

offset s f or FIFO1. I t also conf igur es P ort B fo r bus si z e and endi an arra ngement . F our

LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transi tions of CLKB must

occur whil e MRS1 is LOW.

MRS2 FIFO2 Master

Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the P ort A output register to all zeroes. A LOW pulse on MRS2 selects

one of thre e programma ble flag default off sets for FIFO2. F our LOW-to-HIGH trans i-

tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is

LOW.

PRS1 FIFO1 Partial

Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B outpu t register to al l zeroes . During Partial Reset, the

current ly select ed bus size, endian arrangement, program m ing method (seri al or par -

allel), and progr am m able flag settings are all re tai ned.

PRS2 FIFO2 Partial

Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the Port A outpu t register to al l zeroes . During Partial Reset, the

current ly select ed bus size, endian arrangement, program m ing method (seri al or par -

allel), and progr am m able flag settings are all re tai ned.

RT1 Retransmit

FIFO1 I A LO W strobe on this pin wi ll retransmi t data on FIFO1 from the location of the write

pointer at the last P artial or Master reset.

RT2 Retransmit

FIFO2 I A LO W strobe on this pin wi ll retransmi t data on FIFO2 from the location of the write

pointer at the last P artial or Master reset.

SIZE Bus Size Sel ect I A HIGH on this pin when BM is HIGH selects byte b us (9-bit) size on Port B. A LO W

on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and

BE to select the bus siz e and endian arran gem ent for Port B. The level of SIZE must

be static t hroughout device operation.

Pin Definitions (continued)

Signal Name Description I/O Function

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Maximum Ratings[1]

(Above which the useful l ife may be impa ired. F or user guide-

li nes, not tes ted.)

Storage Temper ature ... ....... ....... .. ........... .....–65°C to +150°C

Ambient Temper ature with

Power Applied...............................................–55°C to +125°C

Supply Volt age to Ground Potent ial...............–0. 5V to +7.0V

DC Voltag e Applied to Outputs

in High Z State[2]......................................–0.5V to VCC+0.5V

DC Input Voltage [2]...................................–0.5V to VCC+0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage..... ...... .. ........................... .. .>2001 V

(per MIL- STD-883, Method 3015 )

Latch-Up Current.... ... .............................................. >200 mA

SPM Serial

Programming I A LO W on this pin selects serial programming o f parti al fl ag offsets. A HIGH on thi s pin

selects parallel program ming or def ault offsets (8, 16, or 64).

W/RA Port A

Write/Read

Select

I A HIGH selects a write operatio n and a LOW sel ects a read operation on Port A f or a

LOW-to- HIGH transition of CLKA. The A 0–35 out put s are in t he HI GH im pedance sta te

when W/RA is H IGH .

W/RB Port B

Write/Read

Select

I A LO W selects a write operati on and a HIGH selects a read operation on Port B f or a

LO W -to- HIGH tr ansit ion of CL KB. T he B0–35 output s are i n the HIGH i mpeda nce sta te

when W/RB is LOW.

Pin Definitions (continued)

Signal Name Description I/O Function

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +7 0°C 5.0V ± 0.5V

Industrial –40°C to +85°C 5.0V ± 0. 5V

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY7C43624/34/44/64/84

UnitMin. Max.

VOH Output HIGH Voltage VCC = 4.5V,

IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = 4.5V,

IOL = 8.0 mA 0.4 V

VIH Input HI GH Voltage 2.0 VCC V

VIL Input LOW Voltage –0.5 0.8 V

IIX Input Leakage Current VCC = Max. –10 +10 mA

IOZL

IOZH Output OFF, High Z

Current VSS < VO< V CC –10 +10 mA

ICC1[3] Active Power Supply

Current Com’l 100 mA

Ind 100 mA

ISB[4] Average Standby

Current Com’l 5mA

Ind 5mA

Capacitance[5]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25×C, f = 1 MHz,

VCC = 5.0V 4pF

COUT Output Capacitance 8pF

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.

4. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

5. Tested initially and after any design or process changes that may affect these parameters.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

AC Test Loads a nd Waveforms

3.0V

OUTPUT

R2=680ΩCL=30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

OUTPUT 1.910V

Equivalent to: THÉ VENIN EQUIVALENT

410 Ω

ALL INPUT PULSES

1KΩ

Switching Charac teris t ics Ov er the Operating Range

Parameter Description

CY7C43624/34/44/64/84

–12 CY7C43624/34/44/64/84

–15

UnitMin. Max. Min. Max.

fSClock Frequency, CLKA or CLKB 83 67 MHz

tCLK Cl ock Cycle Ti me, CLKA or CLKB 12 15 ns

tCLKH Pulse Duration, CLKA or CLKB HIGH 5 6 ns

tCLKL Pulse Duration, CLKA or CLKB LOW 5 6 ns

tDS Set-Up Time, A0–35 b efore CLKA↑ and B0–35 be-

fore CLKB↑4 5 ns

tENS Set-Up Time, CSA, W/RA, ENA, and MBA before

CLKA↑; C S B, W/R B, ENB, and MBB bef ore

CLKB↑

4 5 ns

tRSTS Set-Up Time, MRS1, MRS 2 , PRS1, or PRS2

LOW before CLKA↑ or CLKB↑[6] 4 5 ns

tFSS Set-Up Time, FS0 and FS1 before MRS1 and

MRS2 HIGH 77.5 ns

tBES Set-Up Time, BE/FWFT bef ore MRS1 and MRS2

HIGH 77.5 ns

tSPMS Set-Up Time, SPM before MRS1 and MRS2

HIGH 77.5 ns

tSDS Set-Up Time , FS0/SD before CLKA↑4 5 ns

tSENS Set-Up Time, FS1/SEN before CLK A↑4 5 ns

tFWS Set-Up Time , BE/FWFT before CLKA↑0 0 ns

tDH Hold Time, A0–35 after CLKA ↑ and B0–35 after

CLKB↑0 0 ns

tENH Hold Time, CSA, W /RA, ENA, and MBA after

CLKA↑; CSB, W/RB, ENB, an d MBB after CLK B↑0 0 ns

tRSTH Hold Time, MRS1 , M RS2 , PRS1, or PRS2 LOW

after CLKA↑ or CLKB↑[6] 4 4 ns

tFSH Hold Ti m e, FS0 and FS1 after MRS1 and MRS2

HIGH 2 2 ns

tBEH Hold Time, BE/FWFT after MRS1 and MRS2

HIGH 2 2 ns

Note:

6. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH 2 2 ns

tSDH Hold Time, FS0/SD after CLKA↑0 0 ns

tSENH Hold Time, FS1/SEN after CLKA↑0 0 ns

tSPH Hold Time, FS1/SEN HIGH a fte r MRS 1 and

MRS2 HIGH 2 2 ns

tSKEW1[7] Skew Time between CLKA↑ and CLKB↑ for

EFA/ORA, EFB/ORB , FFA/IRA, and FFB /IRB 67.5 ns

tSKEW2[7] Skew Time between CLKA↑ and CLKB↑ f or AEA,

AEB, AFA, AFB 10 12 ns

tAAcces s Time, CLKA↑ to A0–35 and CLKB ↑ to

B0–35 1 9 3 10 ns

tWFF Prop agat ion De la y T ime, CLKA↑ to FF A/IRA and

CLKB↑ to FFB/IRB 1 8 2 8 ns

tREF Propagation Delay Time, CLKA↑ to EFA/ORA

and CLKB↑ to EFB/ORB 1 8 1 8 ns

tPAE Propagation Del ay Time, CLKA↑ to AEA and

CLKB↑ to AEB 1 8 1 8 ns

tPAF Propagati on Delay Time, CLKA↑ to AFA and

CLKB↑ to AFB 1 8 1 8 ns

tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW

or MBF2 HIGH and CLKB↑ to MBF2 LOW or

MBF1 HIGH

0 9 0 12 ns

tPMR Propagation Delay Time, CLKA↑ to B0–35[8] and

CLKB↑ to A0–35[9] 211 312 ns

tMDV Propagatio n Dela y Time, MBA to A0–35 V alid and

MBB to B0–35 V alid 210 311 ns

tRSF Prop agation Dela y Time , MRS1 or PRS1 LO W to

AEB LOW, A FA HIGH, and MBF1 HIG H and

MRS2 or PRS2 LOW to AEA LOW, AFB HI GH,

and MBF2 HIGH

112 115 ns

tEN Enab le Ti me , CSA or W/ RA LO W to A0–35 Act ive

and CSB LOW and W/RB HIGH to B0–35 Active 210 210 ns

tDIS Di sa ble T i m e, CS A or W /R A H IGH to A0–35 at

High Impedance and CSB HIGH or W/RB LOW

to B0–35 at High Impedance

1 7 1 8 ns

Notes:

7. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB

cycle.

8. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.

9. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.

Switching Charac teris t ics Ov er the Operating Range

Parameter Description

CY7C43624/34/44/64/84

–12 CY7C43624/34/44/64/84

–15

UnitMin. Max. Min. Max.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Switching Wavefor ms

Notes:

10. Master Reset is perf ormed in the same manner for FIFO2 to load X2 and Y2 with a preset value.

11. PRS1 must be HIGH during Master Reset.

FIFO1 Master Reset Loading X1 and Y1 with a Preset Valu e of Eight

CLKA

tRSF

tWFF

tFSS tFSH

tSPMS tSPMH

tBES tBEH

tRSTS

tFWS

CLKB

MRS1

BE/FWFT

SPM

FS1, FS0

FFA/IRA

EFB/ORB

AEB

AFA

MBF1

[10, 11]

tRSF

FWFT

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

12. Partial Reset is performed in the same manner for FIFO2.

13. MRS1 must be HIGH during Partial Reset.

14. CSA=LOW, W /RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

15. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the nex t cycle. If the time between the rising

edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.

Switching Wavefor ms (continued)

FIFO1 Partial Reset (CY Stan dard and FW FT Mo des)

tRSF

tRSTS tRSTH

CLKA

CLKB

PRS1

FFA/IRA

EFB/ORB

AEB

AFA

MBF1

[12, 13]

tWFF

tRSF

Parallel Program ming of t he Almost-Full Flag and Almost -Em pty Flag Off set Values afte r Reset

(CY Standard and FWFT Mo des)

tWFF

tFSS

tDS

tFSS tFSH

tFSH

tENS tENH

tDH

tSKEW1[15]

AFA Offset (Y1) AFB Offset (Y2) First Word to FIFO1

CLKA

MRS1

MRS2

SPM

FS1

FS0

FFA/IRA

ENA

A0 − 35

CLKB

FFB/IRB

[14]

AEB Offset (X1) AEA Offset (X2)

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

16. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.

17. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the nex t cycle. If the time between the rising

edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.

18. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).

19. Written to FIFO1.

Switching Wavefor ms (continued)

Serial Programming of the Almost -Full Flag and Almost-Empty Fla g

Offset Valu es (CY Standard and FWFT Modes)

tFSS tSPH tSENS tSENH tSENH

tSENS

tSDH

tSDS tSDH

tSDS

tSKEW1[17]

tWFF

AFA Offset (Y1) MSB

tFSS tFSH

tWFF

CLKA

MRS1

MRS2

SPM

FFA/IRA

FS1/SEN

CLKB

FFA/IRA

[14]

FS0/SD[18]

AEA Offset (X2) LSB

tCLKH tCLKL

tENS tENH

tDS tDH

tENS tENH tENS tENH

HIGH

W1[19] W2[19]

tCLK

CLKA

FFA/IRA

CSA

W/RA

MBA

ENA

A0–35

Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Note:

20. Written to FIFO2

Switching Wavefor ms (continued)

tCLKH tCLKL

tENS tENH

tDS tDH

tENS tENH tENS tENH

HIGH

W1[20] W2[20]

tCLK

Port B Long-Word Write Cycl e Timing for FIFO2 (CY Standard and FWFT Modes)

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0−35

tENS

tENS tENH

tDS tDH

tENS

tENH

HIGH

tENH

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0–17

P ort B Word Wr it e Cy cle Timing for FIFO2 (CY Stan dard and FWFT Modes)

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Note:

21. Read From FIFO1.

Switching Wavefor ms (continued)

Por t B Byte Write Cycle Tim ing for FIFO2 (CY St andard and FW FT Modes)

tENS

tENS tENH

tDS tDH

tENS

tENH

HIGH

tENH

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0–8

tCLKH tCLKL

tENS

tDIS

tENS tEN

tCLK

tDIS

tENH

tENS tENH

tEN

tMDV

W1[21] W2[21]

W3[21]

Previous Data

No Operation

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–35

(Standard Mode)

B0–35

(FWFT Mode)

P ort B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

22. Unused word B18–35 contains all zeroes for word-size reads.

23. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.

Switching Wavefor ms (continued)

tDIS

tENStENH

tEN

tMDV

tMDV tDIS

Pre vious Data

No Operation

HIGH

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–8

(Stan dard Mode)

B0–8

(FWFT Mode)

P ort B Word Read Cycle Timing f or FIFO1 (CY Sta ndard and FWFT Modes)[22]

tDIS

tENS tENH

tEN

tMDV

tMDV tDIS

Previous Data

No Operation

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–17

(Stan dard Mod e)

B0–17

(FWFT Mo de )

Port B By te Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[23]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Note:

24. Read From FIFO2.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENS

tDIS

tENS tENH

tCLK

tDIS

tENH

tENS tENH

tEN

tMDV

W1[24] W2[24]

W3[24]

Previous Data

No Operation

CLKA

EFA/ORA

CSA

W/RA

MBA

ENA

A0−35

(Stan dard Mode)

A0−35

(FWFT Mode)

Port A Rea d Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

25. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.

26. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and

load of the first word to the output register may occur one CLKB cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENS

tCLK

tEN

tENS

tEN

tDS

LOW

tDH

HIGH

FIFO1 Empt y

LOW

HIGH

LOW

Old Data in FIFO1 Output Register W1

tENS tENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW[26]

CLKA

CSA

W/RA

MBA

ENA

IRA

A0–35

CLKB

ORB

CSB

W/RB

MBB

ENB

B0–35

ORB Flag Timing and First Data Word Fall Through when FIFO 1 is Empty ( FWFT Mode) [25]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

27. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.

28. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENS

tENH

tENS

tENH

tDS

LOW

tDH

HIGH

FIFO1 Empty

LOW

HIGH

LOW

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW[28]

CLKA

CSA

W/RA

MBA

ENA

FFA

A0–35

CLKB

EFB

CSB

W/RB

MBB

ENB

B0–35

EFB Flag Timing and Fi rst Data Read Fa ll Through when FIFO1 is Empty (CY standard Mode) [27]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

29. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

30. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output

register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and

load of the first word to the output register may occur one CLKA cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENS

tENH

tENS

tENH

LOW

tDH

LOW

HIGH

FIFO2 Empt y

LOW

Old Data in FIFO2 Output Register W1

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[30]

tCLK

tDS

CLKB

CSB

W/RB

MBB

ENB

IRB

B0–35

CLKA

ORA

CSA

W/RA

MBA

ENA

A0–35

ORA Flag Timing and Fi rst Data Word Fal l Through when FIFO2 is Empty (FWFT Mode ) [29]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

31. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

32. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF A to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

Switching Wavefor ms (continued)

EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Stand ard Mode)

tCLKH tCLKL

tENS

tENH

tENS

tENH

tDS

LOW

tDH

LOW

HIGH

FIFO2 Empty

LOW

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[32]

CLKB

CSB

W/RB

MBB

ENB

FFB

B0–35

CLKA

EFA

CSA

W/RA

MBA

ENA

A0–35

[31]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

33. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

34. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle . If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO1 Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[34]

tDH

tDS

tENH

tENS

Pr evious W or d in FI FO1 Outp ut Reg ist er Next W ord From FIFO1

To FIFO1

CLKB

CSB

W/RB

MBB

ENB

ORB

B0–35

CLKA

IRA

CSA

W/RA

MBA

ENA

A0–35

IRA Flag Timing and Fi rst Available Writ e when FIFO1 is Full (FWFT Mo de)[33]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

35. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.

36. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF A to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO1 Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[36]

tDH

tDS

tENH

tENS

Previous Word in FIFO1 Output Register Next Word From FIFO1

CLKB

CSB

W/RB

MBB

ENB

ORB

B0–35

CLKA

IRA

CSA

W/RA

MBA

ENA

A0−35

FFA F lag Timing and Fir st Available Write when FIFO1 is Full (CY Standard Mode) [35]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

37. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.

38. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle . If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO2 Full

LOW

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[38]

tDH

tDS

tENH

tENS

Previous Word in FIFO2 Output Register Next Word From FIFO2

To FIFO2

LOW

CLKA

CSA

W/RA

MBA

ENA

ORA

A0–35

CLKB

IRB

CSB

W/RB

MBB

ENB

B0–35

IRB Flag Timi ng and Fir st Availab le Write when FIFO2 is Full (F WFT Mode) [37]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

39. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.

40. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.

Switching Wavefor ms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO2 Full

LOW

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[40]

tDH

tDS

tENH

tENS

Previous Word in FIFO12 Output Reg ister Next Word From FIFO2

To FIFO2

LOW

CLKA

CSA

W/RA

MBA

ENA

EFA

A0–35

CLKB

FFB

CSB

W/RB

MBB

ENB

B0–35

FFB Flag Timing and First Availabl e Write when FIFO2 is Full ( CY Standard Mode)[39]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

41. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LO W, W /RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

read from the FIFO.

42. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.

43. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

44. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LO W , MBA = LOW). Data in the FIFO2 output register has been

read from the FIFO.

45. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

46. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

Switching Wavefor ms (continued)

tPAE

tENH

tENS

tSKEW2[43]

tENS tENH

X1 Word in FIFO1 (X1+1)Words in FIFO1

CLKA

ENA

CLKB

AEB

ENB

Tim ing f or AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[41, 42]

tPAE

tENH

tENS

tSKEW2[46]

tENS tENH

X2 Word in FIFO2 (X2+1)Words in FIFO2

CLKB

ENB

CLKA

AEA

ENA

Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [44, 45]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Notes:

47. FIFO1 Write (CSA = LOW, W/ RA = HIGH, MBA = LOW), FIFO1 read (CSB = LO W, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

read from the FIFO.

48. D = Maximum FIFO Depth = 256 for the CY7C43624, 512 for the CY7C43634, 1K f or the CY7C43644, 4K for the CY7C43664, and 16K for the CY7C43684.

49. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

50. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF A to transition HIGH in the next CLKA cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

51. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LO W , MBA = LOW). Data in the FIFO2 output register has been

read from the FIFO.

52. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.

53. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.

Switching Wavefor ms (continued)

Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Mod es)

tPAF

tENH

tENS

tPAF

tENS tENH

[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1

tSKEW2[50]

CLKA

ENA

AFA

CLKB

ENB

[47, 48, 49]

tPAF

tENH

tENS

tPAF

tENS tENH

[D–(Y2+1)] Words in FIF O2 (D–Y2)Words in FIFO2

tSKEW2[53]

CLKB

ENB

AFB

CLKA

ENA

Timi ng for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)[48, 51 , 52 ]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Note:

54. If P ort B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are don’t care inputs). In this first case B0–17 will have valid

data (B18–35 will be indeterminate). If Port B is configured for byte size, data c an be written to the Mail1 Register using A0–8 (A9–35 are don’t care inputs). In

this second case, B0–8 will have v alid data (B9–35 will be indeterminate).

Switching Wavefor ms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)

CLKA

CSA

W/RA

MBA

ENA

A0–35

CLKB

MBF1

CSB

W/RB

MBB

ENB

Timing for Mail1 Register and M BF 1 Flag (CY Standard and FWFT Modes) [54]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Note:

55. If P ort B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid

data (A18–35 will be indeterminate). If Port B is configured for byte size, data c an be written to the Mail2 Register using B0–8 (B9–35 are don’t care inputs). In

this second case, A0–8 will have v alid data (A9–35 will be indeterminate).

Switching Wavefor ms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)

CLKB

CSB

W/RB

MBB

ENB

B0–35

CLKA

MBF2

CSA

W/RA

MBA

ENA

A0−35

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)[55]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Signal Description

Master Reset (MRS1, MR S 2 )

Each of the two FIFO memories of the CY7C436X4 undergoes

a complete reset by taking its associated Master Reset

(MRS1, MRS2) input LOW f or at least f our P ort A cloc k (CLKA)

and four Port B clock (CLKB) LOW-to-HIGH transitions. The

Mast er Reset i nputs can switch asynchronously to the clocks.

A Master Reset initializes the internal read and write pointers

and f orces the Full /Input Ready flag (FF A/IRA, FFB/IRB ) LOW,

the Empty /Output Ready flag (EFA/ORA, EFB/ORB) LOW , the

Almost Empty f lag (AEA, AEB) LO W, and the Al mo st Ful l fla g

(AFA, AFB) HIGH. A Master Rese t also f orces the Mail box flag

(MBF1, MBF2) of the parallel mailbox register HIGH. After a

Master Reset, the FIFO’s Full/Input Ready flag is set HIGH

aft er tw o cl ock cyc les t o begin normal oper at ion. A Master Re-

set m ust be p erf ormed on the FIFO after power up , b efore data

is written to its memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,

MRS2) input latches the value of t he Big Endi an (BE) input or

determining the order by which bytes are t ransfer red through

Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)

input latches the values of the Fl ag select (FS0, FS1) and Se-

rial Programming Mode (SPM) inpu ts for choosing the Alm ost

Full and Almost Empty offset programming method (see Al-

most Empty and Almost Full flag offset programming below).

Partia l Reset (PRS1, PRS2)

Each of the two FIFO memories of the CY7C436X4 undergoes

a limited reset by taking its associated Par tial Reset (PRS1,

PRS2) i nput LOW for at lea st four P ort A clo ck (CLKA) and four

P ort B cloc k (CLKB) L O W -to- HIGH tr ans itions . The P artial Re-

set inputs can switch asynchronously to the clocks. A Partial

Reset i nitiali zes the internal read an d write poi nters and f orces

the Full/Input Ready flag (FFA/IR A , F F B/IRB) LOW, the Emp-

ty/Output Ready fl ag (EFA/ORA, EFB/ORB) LOW, the Almost

Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA,

AFB) HIGH. A Partial Reset also forces the Mailbox flag

(MBF1, MBF2) of the parallel mailbox register HIGH. After a

Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH

after two clock cy cles to begin normal operation.

Whatever flag offsets, programming method (parallel or seri-

al), and timing mode (FWFT or CY Standard mode) are cur-

rently selected at the time a Partial Reset is initiated, those

settings will remain unchanged upon completion of the reset

operation. A Partial Reset may be useful in the case where

reprogramming a FIFO fol lowing a Master Reset would be in-

convenient.

Big Endian/ First Word Fall Through (BE/FWFT)

This is a dual-purpose pi n. At th e time of Master Reset, the BE

select functi on is active, per mitting a choice of big or little en-

dian byte arrangement for data written to or read from Port B.

This selection determines the order by which byt es (or words)

of data are tra nsferred throu gh this port. For the follo wing illus-

trations, assume that a byte (or wor d) bus size has been se-

lected for Port B. (Note that when Port B is configured for a

long wo rd size , t he Bi g Endian funct ion has no a pplic ation and

the BE input is a “don ’t care”.)

A HIGH on t he BE/FWFT i nput when the Master Reset (MRS1

and MRS2) inputs go from LO W to HIGH will sel ect a Big En-

dian arrangem ent. When data is moving in the direction from

Port A to Por t B, the most significant byte (word) of the long

word written to Port A wil l be read from Por t B first; the least

signi fican t by te (wor d) of the long wo rd writ ten to P ort A will be

read from Port B last. When data is moving in the direction

from Port B to P ort A, the byte (word) written to Po rt B first will

be read from Port A as the most significant byte (word) of the

long word; the byte (word) written to Port B last will be read

from Port A as the least significant byte (word) of the long

word.

A LO W on th e BE/FWFT input when t he Master Reset (MRS1

and MRS2) inputs go from LOW to HIGH will select a Little

Endian arrangement. When data is moving in the direction

from Port A to Por t B, the least significant byte (word) of the

long word written to Por t A will be read from Port B first; the

most significant byte (word) of the long word written to Por t A

will be r ead from Port B l ast. When dat a is movi ng in the di rec-

tion fro m P o rt B to Port A, the b yte ( word) written to Port B fi rst

Notes:

56. Retransmit is performed in the same manner for FIFO2.

57. Clocks are free running in this case.

58. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.

59. For the synchronous PAE and PAF flags (S MODE), a n appropriate clo ck c ycle is necess ary after tRTR to upda te the se fl ags.

Switching Wavefor ms (continued)

FIFO1 Retransmit Timing

ENB

RT1

tPRT tRTR

EFB/FFA

[56, 57, 58, 59]

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

will be read from port A as the least signif icant byte (word) of

the l ong word; the byte (wor d) writ ten to P ort B last will be read

from Port A as the most significant byte (word) of the long

word.

Af ter Mast er Res et, the FWFT selec t funct ion is acti ve , permit-

ting a choice between two possible timing modes: CY Stan-

dard mode or First Word F all Thr ough (FWFT ) mode. Once the

Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the

BE/FWFT input during the next LOW-to-HIGH transition of

CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-

dard mode. This mode uses the Empty Flag function (EFA,

EFB) t o indi ca te wheth er or not there are an y wor ds pres ent i n

the FIFO memory. It uses the Full Flag function (FFA, FFB) to

indicate w hether or not the FIFO memory has any free space

for writing. In CY Standard mode, every word read from the

FIFO, including the first, must be requested using a formal

read operation.

Once t he Master Reset (MRS1,MRS2) input is H IGH, a LOW

on th e BE/FWFT input during the next LOW-to-HIGH transition

of CLKA (for FIFO1) and CLKB (for FIFO2) wil l select FWFT

mode. This mode uses the Output Ready function (ORA,

ORB) to i ndicate whet her or not there is v alid data at th e data

outpu ts (A0–35 or B0–35) . It also uses th e Input Ready fu nct ion

(IRA, IRB) to indicate whether or not the FIFO memory has any

free space for writing. In the FWFT mode, the first word written

to an empty FIFO goes directly to data outputs, no read re-

quest necessary. Subsequent words must be accessed by

performing a formal read operation.

Following Master Reset , the level applied to the BE/FWFT in-

put to choose the desired timing mode must remain static

throughout th e FIFO operation.

Programming the Almost Empty and Almost Full Flags

Four registers in the CY7C436X4 are used to hold the offset

values for the Al m ost Empty and Almost Full flags . The Port B

Almost Empty flag (AEB) offset register is labeled X1 and the

Por t A Almost Empty flag (AEA) offset register is labeled X2.

The Por t A Almost Full flag (AFA) offset register is labeled Y1

and the Port B Almost Ful l flag (AFB) offset registe r i s labele d

Y2. The index of each register name corresponds with preset

values during the reset of a FIFO, programmed in parallel us-

ing the FIFO’s Port A data inputs, or programmed in serial

using the Serial Data (SD) input (see

Table 1

To load a FIFO’s Almost Emp ty flag and Al most Full flag of fset

registers with one of the three preset values l isted in

Table 1

the Serial Program Mode (SPM) and at least one of the

fl ag-sel ect input s must be HIGH during th e LOW -to-HI GH tran-

sit ion of its M aster Rese t i nput (MRS1 and MRS2). For exam-

ple, to load the preset val ue of 64 into X1 and Y1, SPM, FS0

and FS1 must be HIGH when FIFO1 reset (MRS1) returns

HIGH . Fl ag-offs et registers associ ated with FIFO 2 are loade d

with one of the preset values in the same way with Master

Reset (MRS2). When using one of the preset values for the

flag offsets, the FI FO’s can be reset simultaneously or at dif-

ferent times.

To program the X1, X2, Y1, and Y2 regi sters f rom Port A, pe r-

form a Master Reset on bo th FIFOs simul taneously with SPM

HIGH and FS0 and FS1 LOW during the LOW-to-HIGH tran-

sition of MRS1 and MRS2. After this reset is complete, the first

four writes to FIFO1 do not store data in RAM but load the

offset registers i n the order Y1, X1, Y2, X2. The Por t A data

inputs used by the offset registers are (A7–0), (A8–0), (A9–0),

(A11–0), or (A 13–0), for the CY7C436X4, respectively . The high-

est numbered input is used as the most significant bit of the

binary number in each case . Valid pr ogr ammi ng va lues for the

regis ters range from 1 to 252 for the CY7C43624; 1 to 508 f or

the CY7C43634; 1 to 1012 for the CY7C43644; 1 to 4092 for

the CY7C43664; 1 to 16380 for the CY7C43684. After all the

offset registers are programmed from Port A, the Port B Full/In-

put Ready (FFB/I RB) is set HIGH and both FIFOs begin nor-

mal operation.

To program t he X1, X2, Y1, a nd Y2 regist ers serially, i nitiate a

Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN

HIGH during the LOW -to-HIGH tra nsition of MRS1 an d MRS2.

After this reset is complete, the X and Y register values are

loaded bit-wise through the FS0/SD input on each

LOW-to-HIGH transition of CLKA that the FS1/SEN input is

LOW. Thirty-tw-, thirty-six, forty, forty-eight, or fifty-six bit

writes are needed to complete the programming for the

CY7C436X4, r especti vel y. The f our r egist ers are written in t he

order Y1, X1, Y2, and , finally, X2. The first-bit write stores the

most significant bit of the Y1 register and the last-bit write

stores the least signifi cant bit of the X2 register. Each r egister

value can be programmed from 1 to 252 (CY7C43624), 1 to

508 (CY7C43634), 1 to 1020 (CY7C43644), 1 to 4092

(CY7C43664), or 1 to 16380 (CY7C43684).

When the option to program the offset regist ers seri ally is cho-

sen, the Port A Full/I nput Ready (FFA/IRA) flag remains LOW

until all register bits are written. FFA/IRA is set HIGH by the

LO W-to-HIGH transiti on of CLKA afte r the last bit is loaded to

allow normal FIFO1 operation. The Port B Full/Input ready

(FFB/IRB) flag also remains LOW throughout the serial pro-

gramming process, unti l all register bits are writ ten. FFB/IRB

is set HIGH by the LOW-to-HIGH transition of CLKB after the

last bi t i s loaded to allow normal FIFO2 operati on.

SPM, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/ Read O peration

The state of the Port A data (A0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A0–35 lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A0–35 lines are active outputs

when both CSA and W/RA are LOW.

Data is loaded into FIFO1 from the A0–35 inputs on a

LO W-to-HIGH transition of CLKA when CSA is LOW, W/RA is

HIGH, ENA is HIGH, MBA is LOW , an d FF A/IRA is HI GH. Data

is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH

transition of CLKA when CSA is L OW, W /R A is L OW, E NA is

HIGH, MBA is LOW, and EFA/ORA is HIGH (see

Ta bl e 2

FIFO reads and write s on Port A are independent of any con-

current Port B operation.

The Port B control s ignals are identical to those o f Port A with

the exception that the Por t B Write/Read select (W /RB) is the

inverse of the Por t A Write/Read select (W/RA). The state of

the Por t B data (B0–35) lines is controlled by the Port B Chip

Select (CSB ) and P ort B Writ e/Read sel ect (W/RB). The B0–35

lines are in the high-impedance state when either CSB is

HIGH or W/RB is LOW. The B0–35 lines are active outputs

when CSB is LOW and W/RB is HIGH.

Data is loaded into FIFO2 from the B0–35 inputs on a

LO W-to-HIGH transition of CLKB when CSB is LOW, W/RB is

LO W, ENB is HIGH, MBB is LO W, and FF B/IRB is HI GH. Data

is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is

HIGH, MBB is LOW, and EFB/ORB is HIGH (see

Ta bl e 3

FIFO reads and writes on Port B are independent of any con-

current Port A operation.

The set-up and hol d time constr aints to the port cloc ks for the

port Chip Selects and Writ e/read sel ects are only for enabling

write and read operations and are not related to high-imped-

ance co ntrol of the data out puts. I f a port enab le is L OW durin g

a clock cycle, the port’s Chip Select and Write/Read select

ma y change states during the set- up and hold t ime window of

the cycle.

When operating the FIFO in FWFT Mode and the Output

Ready fl ag is LOW, the ne xt word writte n is automati call y sent

to the FIFO’s output regi ster b y the LO W -t o-H IGH tran siti on of

the port clock that sets the Output Ready flag HIGH, data re-

sidi ng in th e FIFO’s memory arra y is cl oc ke d t o the ou tput r eg-

ist er onl y when a read i s sel ect ed usin g the port’s Chip Sel ect,

Write/Read select, Enable, and Mailbox select.

When operat ing t he FI FO in CY Stan dard mode , regardl ess of

whether the Empty Flag is LOW or HI GH, data residing in the

FIFO’s memory array is clocked to the output register only

when a read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least

two fli p-fl op stage s. Th is i s done t o im prov e flag- signal rel iabil-

ity by reducing the probability of the metastable events when

CLKA and CLKB operate asynchronously to one another.

EFA/ORA, AEA, FF A/IRA, and AFA are synchronized t o CLKA.

EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to

CLKB.

Table 4

and

Table 5

show the relationship of each port

flag to FI FO 1 and FIFO2.

Empty/Output Ready Flags (EFA/ORA, EFB/ORB)

These are dual- purpose flags . I n the FWFT Mode, the Output

Ready (ORA, ORB) function is selected. When the Output

Ready flag is HIGH, new data is present in the FIFO output

regi ster . When the Output r eady flag i s LOW, the pr evious data

word is present in the FIFO output register and attempted

FIFO reads are ignored.

In th e CY Standard mode, the Empty Fl ag (EF A , EFB) function

is sel ected . When th e Empty Flag i s HIGH, dat a is availabl e in

the FIFO’s RAM memory for reading to the output register.

When Em pty Flag is LOW, the previous data word is present

in the FIFO output register and attempt ed FIFO reads are ig-

nored.

The Empty/ Output Ready flag of a FIFO is synchroniz ed to the

port clock that reads data from its array. For both the FWFT

and CY Standard modes, the FIF O read pointer is increment-

ed each tim e a new word is clocked to its output register. The

state machine that controls an Output Ready flag monitors a

write pointer and read poi nter comparator that in dicates whe n

the FIFO SRAM status is empty, em pty+1, or empty+ 2.

In FWFT mode, from the time a w ord is written to a FIFO, it ca n

be shifted to the FIFO output register in a minimum of three

cycles of the Output Ready flag synchronizing clock. There-

fore, an Output Ready flag is LOW if a word in memory is the

next data to be sent to the FIFO output register and three cy-

cles have not elapse d since the t ime the word was written . The

Output Ready flag of the FIFO remains LOW until the third

LO W-to-HI G H transition of the synchronizing clock occurs, si-

multa neously forcing th e Outpu t Ready fl ag HIGH and shi fti ng

the word to the FIFO output register.

In the CY Standard mode, from the time a word is writ ten to a

FIFO, the Empty Flag will indicate the presence of data avail-

able for reading in a minimum of two cyc les of th e Em pty Flag

synchronizing clock. Therefore, an Empty Flag is LOW if a

word in memory is the ne xt data to be se nt to the F IFO output

word was written. The Empty Flag of the FIFO remai ns LOW

until the second LOW-to-HIGH transition of the synchronizing

cloc k o ccurs , fo rcing the Empty Fl ag HIGH; onl y then ca n data

be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag

synchronizin g clock begins the firs t synchroni zation cycle of a

write if the clock transition occurs at time tSKEW1 or greater

after the wr ite. Otherwise, the subsequent clock cycle can be

the fi rst synchronization cycle.

Full/ Input Ready Flags (FFA/IRA, FFB/IRB)

This is a dual-purpose fl ag. In FWFT mode, the Input Ready

(IRA and I RB) function is selected. In CY St andard mode, t he

Full Flag (FFA and FFB) function is selected. For both timing

modes, when the Full/Input Ready flag is HIGH, a memory

locat ion is free in the SRAM to receive ne w data. No memory

locations are free when the Full/Input Ready flag is LOW and

attempted writes to the FIFO are ig nored.

The Full /Input Ready flag of a FIFO is sync hronized t o the port

cloc k that writes data to its ar ray. F or both FWFT and CY Stan -

dard modes, each time a word is written to a FIFO, its write

pointer is incremented. The state machine that controls a

Full/ Input Ready fl ag mo nitor s a write poi nt er and r ead poi nte r

comparator that indicates when the FIFO SRAM status is full ,

full–1, or full–2. From the time a word is read from a FIFO, its

previous memory location is ready to be written to in a mini-

mum of two cycles of the Full/Input Ready flag synchronizing

clock. Therefore, an Full/Input Ready flag is LOW if less than

two cycles of the Full/Input Ready flag synchronizing clock

have elapsed since the next memory write location has been

read. The second LOW-to-HIGH transition on the Full/Input

Ready flag synchronizing clock af ter the read sets t he Full/In-

put Ready flag HIGH.

A LOW-to-HIGH transition on a Full/Input Ready flag synchro-

nizing clock begins the first synchronization cycle of a read if

the clock transi tion occurs at time tSKEW1 or greater after the

read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

Almost Empty Flags (AEA, AEB )

The Almost Em pty flag of a FIFO is synchronized t o the port

clock that reads data from its array. The state machine that

controls an Almost Empty flag monitors a write pointer and

read pointer comparator that indicates when the FI FO SRAM

status is almost empty, almost empty+1, or almost empty+2.

The Almost Empty state is defined by the contents of register

X1 for AEB and register X2 f or AEA. These registers are l oad-

ed with preset values during a FIFO reset, programmed from

Port A, or programmed serially (see Almost Empty flag and

Almost Full flag offset pr ogram ming abo v e). An Almost Empty

flag is LOW when its FIFO contains X or less words and is

HIGH when its FIFO contains (X+1) or more words. A data

word present in the FIFO output register has been read from

memory.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Two LOW-to-HIGH transitions of the Almost Empty flag syn-

chronizing clock are required after a FIFO write for its Almost

Empty flag to reflect the new leve l of f il l. Therefore, the Alm ost

Full flag of a FIFO containing (X+1) or more words remains

LO W if tw o cycles of its synchroni zing clock have not el apsed

since the write that filled the memory to the (X+1) level. An

Almost Empty flag is set HIGH by the second LOW-to-HIGH

transition of its synchronizing clock after the FIFO write that

fills memory to the (X+1) level. A LOW -to-HIGH transition of an

Almost Empty flag synchronizing clock begins the first syn-

chr oni zation c ycl e if it occur s at time tSKEW2 o r gr eater after

the write that fills t he FIFO to (X+1) wo rds. Otherwise, the sub-

sequent synchronizing clock cycle may be the first synchroni-

zation cycle .

Almost Full Flags (AFA, AFB)

The Al most Full flag of a FIFO is synchroni zed to t he port cloc k

that writes data t o its array. Th e stat e machine tha t cont rols a n

Almost Full fl ag monitors a write poi nter and read point er com-

parator that indicates when the FIFO SRAM status is almost

full, a lmost full-1 , or al mo st f ull-2. The Almost Ful l state is de-

fi ned b y the con tents o f regi ster Y1 for AF A and r egist er Y2 f or

AFB. These registers are loaded with preset values during a

FIFO reset, programmed f rom Port A, or programmed serially

(see Almost Empty flag and Almost Full flag offset program-

ming above). An Almost Full flag is LOW when the number of

w ords in it s FIFO is gr eater t han or equa l to ( 256–Y) , (512– Y),

(1024–Y), (4096–Y), or (16384–Y) for the CY7C436X4 re-

spectively. An Almost Full flag is HIGH when the number of

words in its FIFO is less than or equal to [256–(Y+1)],

[512–(Y+1)], [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)],

for the CY7C436X4 respectively . Note that a data word present

in the FIFO output register has been read from memo ry.

Two LOW-to-HIGH transitions of the Almost Full fl ag synchro-

nizing clock are required after a FIFO read for its Almost Full

flag to reflect the new level of fill. Therefore, the Almost Full

flag of a FIFO containing [256/512/1024/4096/16384–(Y+1)]

or less words remains LOW if two cycles of its synchroni zing

cloc k have not el apsed sinc e the read that reduced the number

of words in memory to [256/512/1024/4096/16384–(Y+1)]. An

Almost Full f lag i s set HIGH b y the seco nd LO W -t o-HIGH t r an-

sit ion of its sy nchroni zing c loc k af ter t he FIF O rea d that re duc-

es the number of words in memory to

[256/512/1024/4096/16384–(Y+1)]. A LOW-to-HIGH transition

of an Almost Full fl ag synchroni zing clock begins the first syn-

chr oni zation c ycl e if it occur s at time tSKEW2 o r gr eater after

the read that reduces the number of words in memory to

[256/512/1024/4096/16384–(Y+1)]. Otherwise, the subse-

quent sy nchronizing clock cycle may be the first synchr oniza-

tion cycle.

Mailbox Registers

Each FI FO ha s a 36-bit byp ass regist er t o pas s com mand an d

control infor mation between Port A and Por t B without putting

it in queue. The Mailbox Select (MBA, MBB) inputs choose

between a mail register and a FIFO for a port data transfer

operation. The usable width of both the M ail 1 and M ail2 r egis-

ters matches the selected bus size for Port B.

A LOW-to-HIGH transition on CLKA writes A0–35 data to the

Mail 1 Regist er when a Port A write is sel ected b y CSA, W/RA,

and ENA with MBA HIGH. If the selected Port A bus size is

also 36 bits, then the usable width of the Mail1 Register em-

plo ys data li nes A0–35. If the se lecte d Po rt A bus siz e is 18 bits,

then th e usab le wi dth of t he Mail 1 Regist er emp lo ys dat a li nes

A0–17. (In this case, A18–35 are don ’t car e input s.) If t he sel ect-

ed Port A bus size is 9 bits, then the usabl e width of the Ma il 1

Regist er emplo ys dat a lines B0–8. (In this case, A9–35 are don’t

care inputs.)

A LOW-to-HIGH transition on CLKB writes B0–35 data to the

Mail2 Regi ster wh en a P ort B write is se lected by CSB , W/RB,

and ENB with MBB HIGH. If the selected Por t B bus size is

also 36 bits, then the usable width of the Mail2 Regi ster em-

plo ys data li nes B0–35. If th e selected P ort B bus siz e is 18 bits,

then th e usab le wi dth of the M ail 2 Regist er emp lo ys data l ines

B0–17. (In this case, B18–35 are don ’t car e input s.) If t he sel ect-

ed Port B bus size is 9 bits, then the usabl e width of the Ma il 2

Regist er emplo ys dat a lines B0–8. (In this case, B9–35 are don’t

care inputs.)

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. At tempted wri tes to a mail register are

ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox

Select input is LOW and from the mail register when the port

Mailbox Select input is HIGH.

The Mail1 Register Flag (MBF1) is set HIGH by a

LOW-to-HIGH transition on CLKB when a Port B read is se-

l ec ted by C S B, W/ RB, and ENB with MBB HIGH. For a 36-bit

bus size, 36 bits of mailbox data are placed on B0–35. For an

18-bit bus siz e, 18 bits of mailbo x data are pl aced on B0–17. (I n

this case , B18–35 are indeterminat e.) F or a 9-bit b us size , 9 bits

of mailbox data are placed on B0–8. (In this case, B9–35 are

indeterminate.)

The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH

transition on CLKA when a Port A read is selected by CSA,

W/RA, and ENA with MBA HIGH.

For a 36-bit bus size, 36 bits of mailbox data are placed on

A0–35. For an 18-bit bus size, 18 bits of mailbox data are placed

on A0–17. (In this case, A18–35 are indeterm inate.) For a 9-bit

bus size, 9 bits of mailbox data are placed on A0–8. (In this

case, A9–35 are indeter minate.)

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Sel ect featur e has no effect on the mailb ox data.

Bus Sizing

The Port B bus can be confi gured in a 36-bit long word, 18-bit

word, or 9-bit byte format for data read fr om FIFO1 or written

to FIFO2. The levels applied to the Port B Bus Size Select

(SIZE) and the Bus Match Select (BM) determine the Por t B

bus size. These le vels s hould be static thr oughout FIFO oper-

ation. Both bus size selections are implemented at the com-

pletion of Master Reset, by t he time the Full/ Input Ready flag

is set HIGH.

Two different methods for sequencing data transfer are avail-

able for Port B when the bus size selection is either byte-or

word-s ize . They are ref erred to as Big Endian (most si gnificant

byte first) and Little Endian (least significant byte first). The

level applied to the Big Endian Select (BE) input during the

LOW -to- H IGH tra nsition of M R S 1 and M RS2 select s th e endi-

an method that will be active during FIFO operation. BE is a

don’t care input when the bus size selected for Por t B is long

word. The endian m ethod i s implement ed at th e compl etion o f

Master Res et, by t he time th e Full/Input ready f lag is se t HIGH.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Only 36-bit long word data is written to or read from the two

FIFO memories on t he CY7C436X4. Bus-matchi ng operati ons

are done after data is read from the FIFO1 RAM and before

data i s written to FI FO2 RAM. Th ese b us- matchin g op erati ons

are not available when tr ansferring data vi a m ailbo x registers.

Furthermore, both t he word- and b yte- size bu s select ions l imit

the width of the data bus that can be used for mail register

oper ations . In this ca se, only tho se b yte lanes be longin g to th e

selected word- or byte-size bus can carr y mailbox data. The

remaining data outputs will be indeterminate. The remaining

data inputs will be don’t care inputs. For example, when a

word-size bus is selected, then mailbox data can be transmit-

ted only between A0–17 and B0–17. When a byte-size bus is

selected, then mailbox data can be transmitted only between

A0–8 and B0–8.

Bus-Matching FIFO1 Read s

Data is read from the FIFO1 RAM in 36-bit long word incre-

ments. If a long word bus si ze is implemented, the enti re long

w ord immediately shifts to the FIFO1 output r egister. If byte or

word size is implemented on Por t B, only the first one or two

bytes appear on th e selected portio n of the FI FO1 output r eg-

ist er, with the rest of the long word st ored in aux iliary regist ers.

In this case, subsequent FIFO1 reads output the rest of the

long word to the FIFO1 outpu t reg ister.

When r eading dat a from FIFO1 i n the by te or wor d f ormat, th e

unused B0–35 outputs are indeterminate.

Bus-Matching FIFO2 Writes

Data is written to the FIFO2 RAM in 36-bit long word incre-

ments. Data written to FIFO2 with a byte or word bus size

stores the initial bytes or words in auxiliary registers. The

CLKB rising edge that writes the fourth byte or the second

word of lon g word to FIFO2 also s tores th e entire long wor d in

FIFO2 RAM.

When reading data from FIFO2 in byte or word format, the

unused B 0–35 outputs are LOW.

Retransmit (RT1, RT 2 )

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the recei ver and ret ransmit ted if nec essary.

The retransmit feature is intended for use when a number of

writes equal to or less than the depth of the FIFO have oc-

curred and at l east one word has been read si nce the l ast rese t

cycle . A LO W pu lse o n RT 1, RT2 resets the internal read point-

er to the first physical location of the FIFO. CLKA and CLKB

ma y be free running b ut mu st be disab led duri ng and tRTR after

the retrans mit pulse. With every valid re ad cycle aft er retr ans-

mit, previ ously accessed data is read and the read pointer is

incremented until it is equal to the write pointer . Flags are gov-

er ned by the relative locations of the read and write point ers

and are updated during a retransmit cycle. Data writ ten to the

FIFO after activ ation of R T1, RT2 are trans mitte d also. The full

depth of t he FIFO can be repeatedl y retransmi tted.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

A35–27 B

A26–18

A17–9 D

A8–0

B35–27 B

B26–18 C

B17–9 D

B8–0

B35–27 A

B17–9 B

B8–0

B17–9 D

B8–0

B17–9 D

B8–0

B17–9 B

B8–0

B35–27

B26–18

B17–9

(a) LO NG WORD SIZE

(b) WORD SIZE – BIG ENDIAN

(d) BYTE SI ZE – BIG ENDIAN

BE BM SIZE

XLX

BE BM SIZE

HHL

BE BM SIZE

LHL

BE BM SIZE

HHH

Writ e to FI FO

Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

1st: Read from

FIFO

2nd: Read from

FIFO

3rd: Read from

FIFO

4th: Read from

FIFO

BYTE ORDER ON

PORT A:

B8–0

B35–27

B26–18

B17–9

( e) BYT E SIZE – LITT L E EN DIAN

BE BM SIZE

LHH

1st: Read from

FIFO

2nd: Read from

FIFO

3rd: Read from

FIFO

4th: Read from

FIFO

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Table 1. Flag Programming

SPM FS1/SEN FS0/SD MRS1 MRS2 X1 and Y1 Registers[60] X2 and Y2 Registers[61]

HHH↑X64 X

HHHX↑X64

HHL↑X16 X

HHLX↑X16

HLH

↑X8 X

HLHX

↑X8

HLL↑↑

P arallel programming via Port A Paral lel programming via Port A

LHL↑↑Seria l programming via SD Serial programming via SD

LHH

↑↑ Reserved Reserved

LLH

↑↑ Reserved Reserved

LLL

↑↑ Reserved Reserved

Table 2. Port A Enabl e Function

CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function

H X X X X In hig h-i m pedance state None

L H L X X I n high-impedan ce state None

LHHL↑In high-im pedance state FIFO1 writ e

LHHH↑In hig h-impedance state Mail1 write

L L L L X Active, FIFO2 output register None

LLHL↑Active, FIFO2 output register FIFO2 read

L L L H X Active, Mail2 regi ster None

LLHH

↑Acti ve, Mail2 register Mail2 read (set MBF2 HIGH)

Table 3. Port B Enabl e Function

CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function

H X X X X In hig h-impedance state None

L L L X X In high-impeda nce state None

LLHL↑In high-impedance state FIFO2 write

LLHH

↑In high-impeda nce state Mail2 write

L H L L X Active, FIFO1 output re gist er None

LHHL↑Ac t ive, FIFO1 o utp ut r e gister FIFO1 re ad

L H L H X Active, Mail1 register None

LHHH↑Active, Mail1 register Mail1 read (set MBF1 HIGH)

Notes:

60. X1 register holds the offset for AEB; Y1 register holds the offset f or AFA.

61. X2 register holds the offset for AEA; Y2 register holds the offset f or AFB.

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory[62,63,64,65] Synchronized to

CLKA Synchronized to

CLKB

CY7C43624 CY7C43634 CY7C 43644 CY7C43664 CY7C43684 EFB/ORB AEB AFA FFA/IRA

0 0 0 0 0 L L H H

1 TO X1 1 TO X1 1 TO X1 1 TO X1 1 T O X1 H L H H

(X1+1) to

[256–(Y1+1)] (X1+1) to

[512–(Y1+1)] (X1+1) to

[1024–(Y1+1)] (X1+ 1) to

[4096–(Y1+1)] (X1+1) to

[16384–(Y1+1)

]

H H H H

(256–Y1) to

255 (512–Y1) to

511 (1024–Y1) to

1023 (4096–Y1) to

4095 (16384–Y1) to

16383 H H L H

256 512 1024 4096 16384 H H L L

Table 5. FIFO2 Flag Operation (CY Standard and FWFT Modes)

Number of Words in FIFO Memory[63,64,66,67] Synchronized to

CLKA Synchronized to

CLKB

CY7C43624 CY7C43634 CY7C43644 CY 7C43664 CY7C43684 EFB/ORB AEB AFA FFA/IRA

0 0 0 0 0 L L H H

1 TO X2 1 TO X2 1 TO X2 1 TO X2 1 TO X2 H L H H

(X2+1) to

[256–(Y2+1)] (X2+1) to

[512–(Y2+1)] (X2+1) to

[1024–(Y2+1

)]

(X2+1) to

[4096–(Y2+1

)]

(X2+1) to

[16384–(Y2+

)1]

HHHH

(256–Y2) to

255 (512–Y2) to

511 (1024–Y2) to

1023 (40 96–Y2) to

4095 ( 16384–Y2)

to 16383 HHL H

256 512 1024 4096 16384 H H L L

Table 6. Data Size for Long-Word Writ es to FIFO2

Size Mode [68] Data Written to FIFO2 Data Read From FIFO2

BM SIZE BE B35–27 B26–18 B17–9 B8–0 A35–27 A26–18 A17–9 A8–0

LXXABCDABCD

Table 7. Data Size for Word Writes to FIFO2

Size Mode[68] Wri te No. Data Writt en to FI FO 2 Data Read From FIFO2

BM SIZE BE B17–9 B8–0 A35–27 A26–18 A17–9 A8–0

HLH1ABABCD

2CD

HLL1CDABCD

2AB

Notes:

62. X1 is the almost-empty offset for F IFO1 used by AEB . Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset

or port A programming.

63. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

64. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to

the output register (no read operation necessary), it is not included in the FIFO memory count.

65. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode

66. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset

or port A programming.

67. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.quested to the output register (no

read operation necessary), it is not included in the FIFO memory count.

68. BE is selected at Master Reset; BM and SIZE must be static throughout device operation

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Table 8. Data Size for Byte Writes to FIFO2

Size Mode [68] Write No. Da ta W ri tt en to

FIFO2 Data Read From FIFO2

BM SIZE BE B8–0 A35–27 A26–18 A17–9 A8–0

HHH1 A ABCD

HHL1 D ABCD

Table 9. Data Size for FIFO Long- Word Reads from FIFO1

Size Mode[68] Data Written to FIFO1 Data Read From FIFO1

BM SIZE BE A35–27 A26–18 A17–9 A8–0 B35–27 B26–18 B17–9 B8–0

LXXABCDABCD

Table 10. Data Size for Wor d Reads form FIFO1

Size Mode[68] Data Writt en to FIFO1 Read No. Data Read Fr om

FIFO1

BM SIZE BE A35–27 A26–18 A17–9 A8–0 B17–9 B8–0

HLHABCD1AB

2CD

HLLABCD1CD

2AB

Table 11. Data Siz e for Byt e Reads from FIFO1

Size Mode[68] Data Written to FIFO1 Read No. Data Read From

FIFO1

BM SIZE BE A35–27 A26–18 A17–9 A8–0 B8–0

HHHABCD1 A

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CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

Ordering Information

256 x36 x2 Bidirectional Synchronous FI FO w/ bus matching

Speed

(ns) O rd ering C ode Package

Name Package

Type Operating

Range

12 CY7C43624–12AC A128 128-Lead Thin Quad Flat Package Commercial

12 CY7C43624–12AI A128 128-Lead Thin Quad Flat Package Industrial

15 CY7C43624–15A C A128 128-Lead Thin Quad Flat Package Commercial

512 x36 x2 Bidi rectional Synchronous FIFO w/ b us ma tching

Speed

( ns ) Orde ring C o de Package

Name Package

Type Operating

Range

12 CY7C43634–12A C A128 128-Lead Thin Quad Flat Package Com me rci al

12 CY7C43634–12AI A128 128-Lead Thin Quad Flat Package Industrial

15 CY7C43634–15A C A128 128-Lead Thin Quad Flat Package Com me rci al

1K x36 x2 Bidir ectional Sync hronous FIFO w/ bus matching

Speed

( ns ) Orde ring C o de Package

Name Package

Type Operating

Range

12 CY7C43644–12A C A128 128-Lead Thin Quad Flat Package Com me rci al

12 CY7C43644–12AI A128 128-Lead Thin Quad Flat Package Industrial

15 CY7C43644–15A C A128 128-Lead Thin Quad Flat Package Com me rci al

4K x36 x2 Bidir ectional Sync hronous FIFO w/ bus matching

Speed

( ns ) Orde ring C o de Package

Name Package

Type Operating

Range

12 CY7C43664–12A C A128 128-Lead Thin Quad Flat Package Com me rci al

12 CY7C43664–12AI A128 128-Lead Thin Quad Flat Package Industrial

15 CY7C43664–15A C A128 128-Lead Thin Quad Flat Package Com me rci al

16K x36 x2 Bidirectional Synchronous FIFO w/ bus matching

Speed

( ns ) Orde ring C o de Package

Name Package

Type Operating

Range

12 CY7C43684–12A C A128 128-Lead Thin Quad Flat Package Com me rci al

12 CY7C43684–12AI A128 128-Lead Thin Quad Flat Package Industrial

15 CY7C43684–15A C A128 128-Lead Thin Quad Flat Package Com me rci al

Document #: 38–00700

CY7C43624

CY7C43634/CY7C43644

CY7C43664/CY7C43684

PRELIMINARY

of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag r am

128-Pin Thin Plas ti c Qua d Flat pack (14 x 20 x 1.4 mm) A128

51-85101