RT8299ZQW - Richtek - Product.Network

RT8299

DS8299-01 May 2012 www.richtek.com

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

3A, 24V, 500kHz Synchronous Step-Down Converter

General Description

The RT8299 is a high efficiency , monolithic synchronous

step-down DC/DC converter with internal power MOSFETs.

It achieves 3A of continuous output current over a wide

input supply range from 3V to 24V with excellent load and

line regulation. Current mode operation provides fast

transient response and eases loop stabilization. Cycle-

by-cycle current limit provides protection against shorted

outputs and soft-start eliminates input current surge during

start-up. Thermal shutdown provides reliable, fault tolera nt

operation. The low current shutdown mode provides output

disconnection, enabling easy power management in battery

powered systems.

Applications

zIndustrial a nd Commercial Low Power Syste ms

zComputer Peripherals

zLCD Monitors and TVs

zGreen Electronics/Applia nces

zPoint of Load Regulation for High Performance DSPs,

FPGAs, a nd ASICs

Pin Configurations

(TOP VIEW)

SOP-8 (Exposed Pad)

Features

z3V to 24V Input Voltage Range

z3A Output Current

zInternal N-MOSFET s

zCurrent Mode Control

zFixed Frequency Operation : 500kHz

zOutput Adjustable from 0.8V to 15V

zUp to 95% Efficiency

zStable with Low ESR Ceramic Output Capacitors

zCycle-by-Cycle Over Current Protection

zInput Under Voltage Lockout

zOutput Under Voltage Protection

zThermal Shutdown Protection

zSOP-8 (Exposed Pad) a nd 10-Lea d WDFN Pa ckage s

zRoHS Compliant and Halogen Free

BOOT

VIN

GND

VCC

PGOOD

GND

PGOOD

BOOT

VCC

GND

VIN

EN 9

GND

WDFN-10L 3x3

RT8299 Package Type

SP : SOP-8 (Exposed Pad-Option 1)

QW: WDFN-10L 3x3 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

Z : ECO (Ecological Element with

Halogen Free and Pb free)

RT8299

2DS8299-01 May 2012www.richtek.com

Typical Application Circuit

RT8299ZQW 56 : Product Number

YMDNN : Date Code

56 YM

DNN

RT8299

VIN

CIN

VIN

PGODD

BOOT

CBOOT L1 VOUT

COUT

Chip Enable

VCC

GND

RTR1

Power Good

CVCC

10µF x 2

VOUT (V) R1 (kΩ) R2 (kΩ) RT (k Ω) L (μH) COUT (μF)

1.2 15 30 50 2 22 x 2

2.5 25.5 12 40 3.6 22 x 2

3.3 16 5.1 30 4.7 22 x 2

5 27 5.1 18 6.8 22 x 2

Table 1. Recommended Component Selection

Marking Information

RT8299

GSPYMDNN

RT8299ZSP RT8299ZSP : Product Number

YMDNN : Date Code

RT8299GSP RT8299GSP : Product Number

YMDNN : Date Code

RT8299GQW 56= : Product Number

YMDNN : Date Code

RT8299

ZSPYMDNN

56=YM

DNN

RT8299

DS8299-01 May 2012 www.richtek.com

Function Block Diagram

Functional Pin Description

Pi n No.

SOP-8

( Exposed Pad) WDFN -1 0L 3x3 Pi n Name Pin Funct ion

1 5 BOOT

Bo otstrap fo r Hi gh Si de Gate D ri ver. Connect a 0. 1μF or greater

cer ami c capacitor from B O O T to SW pi n.

2 6, 7 VIN

Supply Input Voltage. Must bypass wit h a suitably large ceram ic

capacitor.

3 8, 9 SW Swi tch N ode. Connect to external LC filt er.

4, 9

( Exp osed Pad) 10, 11

(E xposed Pad) GND Gr ound. The exposed pad mu st be sol der ed t o a l arge P CB and

connect ed to GN D for maximum power dissipation.

5 1 FB

Fee dbac k In put . This pin is conn ected to the co nver t er output. I t

is used t o regulate the out put o f the convert er t o a de s ired value

via an inter nal re s ist ive volt age divi der. F or a n adjustable output ,

an external resistive voltage di vider is connect ed to t his pin.

6 3 EN

Enable Input. A logic high enables the converter; a logic low

forces the RT8299 into shutdown mode, reducing the supply

curre nt to less than 3μA . Atta ch this pin t o VIN wit h a 100kΩ pul l

up r esistor for aut oma ti c sta rtup.

7 2 PGOOD Power G ood Output. The output of this pin is open drain.

8 4 VCC Bias Supply.

Driver

Current Sense

Amplifier

PWM

Comparator

Oscillator

500kHz

Ramp

Generator

Regulator

-Error

Amplifier SW

BOOT

VIN

GND

VCC

1pF

30pF

300k OC Limit

Clamp

Reference

PGOOD

Generator

PGOOD

5k Comparator

RT8299

4DS8299-01 May 2012www.richtek.com

Electrical Characteristics

(VIN = 12V, TA = 25°C, unless otherwise specified)

Absolute Maximum Ratings (Note 1)

zSupply Input Voltage, VIN ----------------------------------------------------------------------------------- −0.3 to 26V

zSwitching Voltage, SW ------------------------------------------------------------------------------------- −0.3 to (VIN + 0.3V)

zBoot Voltage, BOOT----------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)

zAll Other Pins ------------------------------------------------------------------------------------------------- −0.3 to 6V

zPower Dissipation, PD @ TA = 25°C

SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------- 1.333W

WDFN-10L 3x3 ------------------------------------------------------------------------------------------------ 1.429W

zPa ckage Thermal Re sistance (Note 2)

SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------- 75°C/W

SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------- 15°C/W

WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------ 70°C/W

WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------ 8.2°C/W

zLead T emperature (Soldering, 10 sec.)------------------------------------------------------------------ 260°C

z Junction Temperature --------------------------------------------------------------------------------------- 150°C

zStorage T emperature Range ------------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------- 2kV

MM (Machine Model) ---------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

zSupply Voltage, VIN ------------------------------------------------------------------------------------------- 3V to 24V

zJunction T emperature Range-------------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range-------------------------------------------------------------------------------- −40°C to 85°C

Parameter Symbol Test Conditions Min Typ Max Unit

Sh utdown C ur rent I SHDN V

EN = 0V -- -- 3 μA

Supply Current VEN = 3 V , VFB = 1V -- 1 -- mA

Upper Sw itch On R esistance -- 100 -- mΩ

Lower Switch On Resistance -- 100 -- mΩ

Sw i tch Leakage VEN = 0 V , VSW = 0V o r 12V -- 0 10 μA

Curren t Limit ILIM V

BOOT − VSW = 4. 8V -- 5.5 -- A

Oscill at or Fr equency fOSC V

FB = 0.75V 425 500 575 kHz

Sh or t Ci rcu it F requency VFB = 0V -- 150 -- kHz

M a x imum Du ty Cycl e DMAX V

FB = 0.8V -- 93 -- %

M inimu m On- Ti me t ON -- 100 -- ns

Feedback Vol t age V FB 4.5V ≤ VIN ≤ 24V 788 800 812 mV

Logic-High VIH 2 -- 5.5

EN Input

Thres hol d Vol tag e Logic-Low VIL -- -- 0.4

Under Voltage Lock out Threshold VUVLO V

IN Rising -- 2. 8 - - V

Under Vol tage Lock out Threshold

Hysteresis ΔVUVLO -- 300 -- mV

RT8299

DS8299-01 May 2012 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

VOUT Rising, with Respect to VFB -- 90 --

P ower Good Threshold VOUT Falling, with Respect to VFB -- 70 -- %

VCC Regulator -- 5 -- V

VCC Load Regulation ICC = 5mA -- 5 -- %

Soft-S tart Period tSS -- 2 -- ms

Th erma l Shu tdown TSD -- 150 -- °C

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

RT8299

6DS8299-01 May 2012www.richtek.com

Typical Operating Characteristics

Reference Voltage vs. Temperature

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

Refer ence Voltage (V)

VIN = 12V, VOUT = 3.3V

Frequency vs. Input Voltage

470

480

490

500

510

520

530

540

550

560

570

3 5 7 9 11 13 15 17 19 21 23

In put Volt age (V)

Fr equency (kHz) 1

VOUT = 1.2V, IOUT = 0.5A

Efficiency vs. Output Current

100

00.511.522.53

Ou tput Current (A)

Effici ency (%)

VIN = 5V, VOUT = 3.3V

VIN = 12V, VOUT = 3.3V

VIN = 23V, VOUT = 3.3V

VIN = 5V, VOUT = 1.2V

VIN = 3V, VOUT = 1.2V

VIN = 12V, VOUT = 1.2V

Reference Voltage vs. Input Voltage

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

4 6 8 10 12 14 16 18 20 22 24

In put Voltage (V )

Reference Voltage ( V )

VOUT = 3.3V, IOUT = 0A

Output Voltage vs. Output Current

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3

Ou tput Current (A)

Output Voltage ( V )

VIN = 3V

VIN = 5VV

VIN = 4.5V

VIN = 12V

VOUT = 1.2V

Output Voltage vs . Output Current

3.320

3.325

3.330

3.335

3.340

3.345

3.350

3.355

3.360

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3

Output Current (A)

Output Vol tage (V)

VIN = 5V

VIN = 12V

VIN = 23V

VOUT = 3.3V

RT8299

DS8299-01 May 2012 www.richtek.com

Switching

Time (1μs/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 1.5A

(2A/Div)

VOUT

(5mV/Div)

VSW

(10V/Div)

Switching

Time (1μs/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 3A

(2A/Div)

VOUT

(5mV/Div)

VSW

(10V/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 1.5A to 3A

Load Transient Response

Time (100μs/Div)

VOUT

(100mV/Div)

IOUT

(2A/Div)

Current Limit vs. Temperature

-50 -25 0 25 50 75 100 125

Temperature (°C)

Current Lim it (A)

VOUT = 1.2V

VIN = 12V

VIN = 5VV

VIN = 3V

Load Transient Response

Time (100μs/Div)

VOUT

(100mV/Div)

IOUT

(2A/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 0A to 3A

Frequency vs . Te mpe rature

470

480

490

500

510

520

530

540

550

560

570

-50 -25 0 25 50 75 100 125

Temperature (°C)

Fr equency (kHz) 1

VIN = 23V

VIN = 12VV

VIN = 5V

VIN = 3V VOUT = 1.2V, IOUT = 0.5A

RT8299

8DS8299-01 May 2012www.richtek.com

Power Off from VIN

Time (2.5ms/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 3A

(2A/Div)

VOUT

(1V/Div)

VIN

(10V/Div)

Power Off from EN

Time (2.5ms/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 3A

(2A/Div)

VOUT

(1V/Div)

VEN

(5V/Div)

Power On from EN

Time (2.5ms/Div)

VIN = 12V, VOUT = 1.2V, IOUT = 3A

(2A/Div)

VOUT

(1V/Div)

VEN

(5V/Div)

Power On from VIN

Time (2.5ms/Div)

VIN = 12V, VOUT =1.2V, IOUT = 3A

(2A/Div)

VOUT

(1V/Div)

VIN

(10V/Div)

RT8299

DS8299-01 May 2012 www.richtek.com

Application Information

The RT8299 is a synchronous high voltage buck converter

that can support the input voltage range from 3V to 24V

a nd the output current ca n be up to 3A.

Output Voltage Setting

The resistive divider allows the FB pin to sense the output

voltage a s shown in Figure 1.

Figure 1. Output Voltage Setting

The output voltage is set by a n external resistive voltage

divider a ccording to the following equation :

⎛⎞

⎜⎟

⎝⎠

OUT FB R1

V = V1

where VFB is the feedback reference voltage (0.8V typ.).

External Bootstrap Diode

Connect a 100nF low ESR ceramic capacitor between

the BOOT pin and SW pin. This capacitor provides the

gate driver voltage for the high side MOSFET.

It is recommended to add an external bootstrap diode

between an external 5V and BOOT pin for efficiency

improvement when input voltage is lower than 5.5V or duty

ratio is higher than 65% .The bootstrap diode can be a

low cost one such as IN4148 or BA T54. The external 5V

ca n be a 5V fixed input from system or a 5V output of the

RT8299. Note that the external boot voltage must be lower

tha n 5.5V

Chip Enable Operation

The EN pin is the chip enable input. Pulling the EN pin

low (<0.4V) will shutdown the device. During shutdown

mode, the RT8299 quiescent current drops to lower than

3μA. Driving the EN pin high (>2V, < 5.5V) will turn on the

device again. For external timing control (e.g.RC), the EN

pin can also be externally pulled high by adding a REN*

resistor a nd CEN* capa citor from the VIN pin (see Figure

5).

An external MOSFET can be added to implement digital

control on the EN pin when no system voltage above 2.5V

is available, as shown in Figure 3. In this case, a 100kΩ

pull-up resistor, REN, is connected between VIN and the

EN pin. MOSFET Q1 will be under logic control to pull

down the EN pin.

Figure 3. Enable Control Circuit for Logic Control with

Low V oltage

To prevent enabling circuit when VIN is smaller than the

VOUT target value, a resistive voltage divider can be placed

between the input voltage a nd ground and connected to

the EN pin to adjust IC lockout threshold, as shown in

Figure 4. For exa mple, if an 8V output voltage is regulated

from a 12V input voltage, the resistor REN2 can be selected

to set input lockout threshold larger than 8V.

RT8299

GND

VOUT

BOOT

RT8299 100nF

Figure 2. External Bootstra p Diode

VIN

GND

BOOT

SW L

VOUT

Chip Enable

VIN RT8299

VCC

CPGOOD

CBOOT

COUT

CIN

REN

100k

VCC

100k

Figure 4. The Resistors can be Selected to Set IC

Lockout Threshold

VIN

GND

BOOT

SW L

VOUT

RT8299

VCC

PGOOD

CBOOT

COUT

CIN

REN

100k

VCC

100k

REN2

10µF

VIN

12V

RT8299

10 DS8299-01 May 2012www.richtek.com

OUT OUT

LIN

I = 1

fL V

⎡⎤⎡ ⎤

Δ×−

⎢⎥⎢ ⎥

⎣⎦⎣ ⎦

Under Voltage Protection

Hiccup Mode

For the RT8299, it provides Hiccup Mode U nder Voltage

Protection (UVP). When the FB voltage drops below half

of the feedback reference voltage, VFB, the UVP function

will be triggered and the RT8299 will shut down for a period

of time a nd then recover automatically . The Hiccup Mode

UVP ca n reduce input current in short-circuit conditions.

Inductor Selection

The inductor value and operating frequency determine the

ripple current according to a specific input and output

voltage. The ripple current ΔIL increases with higher VIN

and decrea ses with higher inductance.

Having a lower ripple current reduces not only the ESR

losses in the output ca pacitors but also the output voltage

ripple. High frequency with small ripple current can achieve

highest efficiency operation. However , it requires a large

inductor to a chieve this goal.

For the ripple current selection, the value of ΔIL = 0.24(IMAX)

will be a reasonable starting point. The largest ripple

current occurs at the highest VIN. To guarantee that the

ripple current stays below the specified maximum, the

inductor value should be chosen according to the following

equation :

OUT IN

RMS OUT(MAX) IN OUT

I = I 1

−

CIN and COUT Selection

The input capacitance, CIN, is needed to filter the

tra pezoidal current at the source of the high side MOSFET .

To prevent large ripple current, a low ESR input ca pa citor

sized for the maximum RMS current should be used. The

RMS current is given by :

OUT OUT

L(MAX) IN(MAX)

L = 1

fI V

⎡⎤⎡ ⎤

×−

⎢⎥⎢ ⎥

×Δ

⎣⎦⎣ ⎦

The inductor's current rating (caused a 40°C temperature

rising from 25°C ambient) should be greater than the

maximum load current and its saturation current should

be greater than the short circuit peak current limit. Plea se

see Table 2 f or the inductor selection reference.

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT / 2. This simple worst case condition is

commonly used for design because even significant

deviations do not offer much relief.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design.

For the input capacitor, two 10μF low ESR ceramic

ca pa citors are recommended.

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

Loop stability can be checked by viewing the load transient

response as described in a later section.

The output ripple, ΔVOUT , is determined by :

OUT L OUT

VIESR

8fC

⎡⎤

Δ≤Δ +

⎢⎥

⎣⎦

The output ripple will be highest at the maximum input

voltage since ΔIL increases with input voltage. Multiple

capa citors pla ced in parallel may be needed to meet the

ESR and RMS current handling requirement. Dry tantalum,

special polymer, aluminum electrolytic and ceramic

capacitors are all available in surface mount packages.

Special polymer capacitors offer very low ESR value.

However, it provides lower ca pacitance density than other

types. Although Tantalum capacitors have the highest

ca p a cita nce density, it is importa nt to only use types that

pass the surge test for use in switching power supplies.

Aluminum electrolytic ca pacitors have significantly higher

ESR. However, it can be used in cost-sensitive a pplications

Table 2. Suggested Inductors for Typical

Application Circuit

Compo nent

Supplier Series Dimension s

(mm)

TDK VLF10045 10 x 9.7 x 4.5

TDK SLF 12565 12.5 x 12.5 x 6.5

TAIYO

YUDEN NR 8040 8 x 8 x 4

RT8299

DS8299-01 May 2012 www.richtek.com

for ripple current rating and long term reliability

considerations. Ceramic capacitors have excellent low

ESR characteristics but can have a high voltage coefficient

and audible piezoelectric effe cts. The high Q of ceramic

ca pacitors with trace inductance can also lead to significant

ringing.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller ca se sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However , care must

be taken when these capacitors are used at input and

output. When a ceramic capacitor is used at the input

a nd the power is supplied by a wall ada pter through long

wires, a load ste p at the output ca n induce ringing at the

input, VIN. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

cause a voltage spike at VIN large enough to da mage the

part.

Checking Tra n sient Re spon se

The regulator loop response can be checked by looking

at the load tra nsient response. Switching regulators ta ke

several cycles to respond to a step in load current. When

Figure 5. Reference Circuit with Snubber and Enable Timing Control

VIN

GND

BOOT

SW L

VOUT

10µF x 2

VIN RT8299

VCC

PGOOD

CBOOT

COUT

CIN

RBOOT*

RS*

CS*

REN*

CEN*

* : Optional

VCC

100k

a load step occurs, VOUT immediately shifts by a n amount

equal to ΔILOAD (ESR) also begins to charge or discharge

COUT generating a feedba ck error signal f or the regulator

to return VOUT to its steady-state value. During this

recovery time, VOUT can be monitored for overshoot or

ringing that would indicate a stability problem.

EMI Consideration

Since para sitic inductance a nd capacitance effects in PCB

circuitry would cause a spike voltage on SW pin when

high side MOSFET is turned-on/off, this spike voltage on

SW may impact on EMI performance in the system. In

order to enhance EMI performance, there are two methods

to suppress the spike voltage. One is to place an R-C

snubber between SW and GND a nd ma ke them a s close

a s possible to the SW pin (see Figure 5). Another method

is adding a resistor RBOOT* in series with the bootstrap

ca pacitor, CBOOT. But this method will decrea se the driving

capability to the high side MOSFET. It is strongly

recommended to reserve the R-C snubber during PCB

layout for EMI improvement. Moreover , reducing the SW

trace area and keeping the main power in a small loop will

be helpful on EMI perf orma nce. For detailed PCB layout

guide, plea se refer to the section of Layout Consideration.

RT8299

12 DS8299-01 May 2012www.richtek.com

Figure 6. Derating Curve of Maximum Power Dissipation

Layout Consideration

Follow the PCB layout guidelines for optimal performance

of the RT8299.

` Keep the tra c es of the main current paths as short a nd

wide as possible.

` Put the input ca pa citor as close a s possible to the device

pins (VIN and GND).

` SW node is with high frequency voltage swing and should

be kept at small area. Keep analog components away

from the SW node to prevent stray ca pacitive noise pick-

up.

` Connect feedback network behind the output capa citors.

Keep the loop area small. Place the feedback

components near the RT8299.

` An example of PCB layout guide is shown in Figure 6 for

reference.

Thermal Considerations

For continuous operation, do not exceed the maximum

operation junction temperature 125°C. The maximum

power dissipation depends on the thermal resistance of

IC pa ckage, PCB layout, the rate of surroundings airflow

and temperature difference between junction to a mbient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX) − TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature , TA is the a mbient temperature and the θJA is

the junction to ambient thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

a mbient thermal resistance, θJA, is layout dependent. For

SOP-8 (Exposed Pad) package, the thermal resistance,

θJA, is 75°C/W on a standard JEDEC 51-7 four-layer

thermal test board. For WDFN-10L 3x3 packageS, the

thermal resistance, θJA, is 70°C/W on a standard JEDEC

51-7 four-layer thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by the following

formulas :

PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for

SOP-8 (Exposed Pad) pa ckage

PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for

W DF N-10L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. The derating curve in Figure 6 allow the

designer to see the ef fe ct of rising ambient temperature

on the maximum power dissipation.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

0255075100125

Ambient Tem perature (°C)

Maxi mum Power Di ssipati on (W) 1

Four-Layer PCB

SOP-8 (Exposed Pad)

WDFN-10L 3x3

RT8299

DS8299-01 May 2012 www.richtek.com

Figure 7. PCB Layout Guide

VIN

VOUT

GND

CIN

GND

VOUT

COUT

Input capacitor must

be placed as close

to the IC as possible.

SW should be connected to inductor by

wide and short trace. Keep s ens itive

components away from this trace.

The feedback components

must be connect ed as close

to the device as possible.

BOOT

VIN

GND

VCC

PGOOD

GND

CVCC

RS*

CS*

GND

VIN

REN

RPG VCC

The CVCC component must be connec ted

as close to the dev ice as possible.

The REN component

must be connect ed t o

VIN.

RT8299

14 DS8299-01 May 2012www.richtek.com

Outline Dimension

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dime nsions In M illimeters Dimensions In In ches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2 Y 3.000 3.500 0.118 0.138

RT8299

DS8299-01 May 2012 www.richtek.com

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Dim ensions In M illimet ers Dimensio ns In Inches

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 2.300 2.650 0.091 0.104

E 2.950 3.050 0.116 0.120

E2 1.500 1.750 0.059 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 10L DFN 3x3 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options

SEE DETAIL A