0.8V Reference Ultra Low Dropout (0.2V@1.5A) Linear Regulator
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw1
•Ultra Low Dropout
- 0.2V(typical) at 1.5A Output Current
•Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
•0.8V Reference Voltage
•High Output Accuracy
- ±1.5% over Line, Load, and Temperature
•Fast Transient Response
•Adjustable Output Voltage by External Resistors
•Power-On-Reset Monitoring on both VCNTL and
VIN Pins
•Internal Soft-Start
•Current-Limit Protection
•Under-Voltage Protection
•Thermal Shutdown with Hysteresis
•Power-OK Output with a Delay Time
•Shutdown for Standby or Suspend Mode
•Simple SOP-8P Package with Exposed Pad
•Lead Free and Green Devices Available
(RoHS Compliant)
Features
The APL5915 is a 1.5A ultra low dropout linear regulator.
This product is specifically designed to provide well sup-
ply volatage for motherboards NB and VGA card
applications. The IC needs two supply voltages, a control
voltage for the circuitry and a main supply voltage for
power conversion, to reduce power dissipation and pro-
vide extremely low dropout.
The APL5915 integrates many functions into a single
package. A Power-On-Reset (POR) circuit monitors both
supply voltages to prevent wrong operations. Thermal
shutdown and current limit functions protect the device
against thermal and current over-loads. POK indicates
the output status with time delay which is set internally. It
can control other converter for power sequence. The
APL5915 is enabled by other power system. Pulling and
holding the EN pin below 0.3V to shuts off the output.
The APL5915 is available in SOP-8P package which fea-
tures small size as SOP-8 and an Exposed Pad to reduce
the junction-to-case resistance, being applicable in 1~2W
applications.
Applications
Pin Configuration
General Description
•Note Book PC Applications
•Motherboard Applications
•VGA Card Applications
1
2
3
4
8
7
6
5
EN
POK
VCNTL
VIN
GND
FB
VOUT
VOUT
VIN
SOP-8P
(Top View)
= Exposed Pad
(connected to VIN plane for better heat dissipation)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw2
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handing Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APL5915
Handling Code
Temperature Range
Package Code
APL5915
XXXXX
APL5915 KA:XXXXX - Date Code
Assembly Material
Symbol Parameter Rating Unit
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 3.9 V
VI/O EN and FB to GND -0.3 ~ VCNTL+0.3 V
VPOK POK to GND -0.3 ~ 7 V
PD Power Dissipation 2.8 W
TJ Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Absolute Maximum Ratings
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Thermal Resistance in Free Air (Note 2)
SOP-8P
44 oC/W
θJC Junction-to-Case Thermal Resistance (Note 3)
SOP-8P
19 oC/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
1
2
3
4
8
7
6
5
VIN
Measured Point
PCB Copper
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw3
Recommended Operating Conditions
Symbol Parameter Range Unit
VCNTL VCNTL Supply Voltage 3.1 ~ 6 V
VIN VIN Supply Voltage 1.1 ~ 3.5 V
VOUT Output Voltage V
CNTL=3.3±5%
V
CNTL=5.0±5%
0.8 ~ 1.2
0.8 ~ VIN-0.2 V
IOUT VOUT Output Current 0 ~ 1.5 A
TJ Junction Temperature -40 ~ 125 oC
Electrical Characteristics
APL5915
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
SUPPLY CURRENT
ICNTL VCNTL Supply Current
EN = VCNTL, VFB is well regulated 0.4 1 2 mA
ISD VCNTL Shutdown Current EN = GND - 180 380 µA
POWER-ON-RESET
VCNTL POR Threshold VCNTL Rising 2.7 2.9 3.1 V
VCNTL POR Hysteresis - 0.4 - V
VIN POR Threshold VIN Rising 0.8 0.9 1.0 V
VIN POR Hysteresis - 0.5 - V
OUTPUT VOLTAGE
VREF Reference Voltage FB =VOUT - 0.8 - V
Output Voltage Accuracy IOUT=0A ~1.5A, TJ= -40~125oC -1.5 - +1.5 %
Line Regulation VCNTL=3.3 ~ 5.5V -0.13
- 0.13 %/V
Load Regulation IOUT=0A ~1.5A - 0.06 0.15 %
DROPOUT VOLTAGE
VOUT = 1.2V - 0.12 0.18
IOUT = 1.5A,
VCNTL=5V,
TJ= 25oC VOUT = 2.5V - 0.17 0.23 V
VOUT = 1.2V - - 0.25
Dropout Voltage IOUT = 1.5A,
VCNTL=5V,
TJ= -40~125oC VOUT = 2.5V - - 0.3 V
PROTECTION
VCNTL=5V, TJ= 25oC 2.1 2.8 3.5 A
ILIM Current Limit VCNTL=5V, TJ= -40 ~ 125oC 1.8 - - A
TSD Thermal Shutdown Temperature TJ Rising - 150 - oC
Thermal Shutdown Hysteresis - 50 - oC
Under-Voltage Threshold VFB Falling - 0.4 - V
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = -40
to 85°C, unless otherwise specified. Typical values refer to TA = 25°C.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APL5915
Symbol
Parameter Test Conditions Min. Typ. Max.
Unit
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN Rising 0.3 0.4 0.5 V
EN Hysteresis - 30 - mV
EN Pin Pull-Up Current EN=GND - 10 - µA
TSS Soft-Start Interval - 2 - ms
POWER OK AND DELAY
VPOK POK Threshold Voltage for Power
OK VFB Rising 90% 92% 94% VREF
VPNOK POK Threshold Voltage for Power
Not OK VFB Falling 79% 81% 83% VREF
POK Low Voltage POK sinks 5mA - 0.25 0.4 V
TDELAY POK Delay Time 1 3 10 ms
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = -40
to 85°C, unless otherwise specified. Typical values refer to TA = 25°C.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw5
Typical Operating Characteristics
VCNTL Supply Current vs. Junction
Temperature
VCNTL Supply Current, ICNTL (mA)
Junction Temperature (°C)
Current-Limit vs. Junction Temperature
Current-limit, ILIM (A)
Reference Voltage vs. Junction
Temperature
Reference Voltage, VREF (mV)
POK Delay Time vs. Junction Temperature
POK Delay Time (ms)
-50 -25 0 25 50 75 100 125
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VCNTL=5V
VCNTL=3.3V
2.4
2.5
2.6
2.7
2.8
2.9
-50 -25 025 50 75 100 125
VCNTL=5V
VCNTL=3.3V
Junction Temperature (°C)
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
-50 -25 0 25 50 75 100 125
Junction Temperature (°C)-50 -25 0 25 50 75 100 125
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
VCNTL=5V
VCNTL=3.3V
Junction Temperature (°C)
Frequency (Hz)
VCNTL PSRR (dB)
VCNTL PSRR vs. Frequency
VIN PSRR (dB)
VIN PSRR vs. Frequency
Frequency (Hz)
100 1000 10000 100000 1000000
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
VIN=1.6V
VIN=1.8V
VCNTL=5V
VIN PK-PK=200mV
IOUT=1A
VOUT=1.2V
COUT=22µFVIN=1.5V
-80
-70
-60
-50
-40
-30
-20
-10
0
100 1000 10000 100000 1000000
VCNTL=5V
VCNTLPK-PK=200mV
VIN=1.5V
IOUT=1A
VOUT=1.2V
COUT=22µF
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
VIN Dropout Voltage vs. Output Current
VIN Dropout Voltage (mV)
Output Current, lOUT (A)
VIN Dropout Voltage vs. Output Current
VIN Dropout Voltage (mV)
0
50
100
150
200
250
300
00.5 11.5
VCNTL=5V
VOUT=2.5V TJ=25oC
TJ=75oC
TJ=125oCTJ=0oC
TJ=-25oC
00.5 11.5
VCNTL=5V
VOUT=1.8V
0
50
100
150
200
TJ=25oC
TJ=75oC
TJ=125oCTJ=0oC
TJ=-25oC
Output Current, lOUT (A)
VIN Dropout Voltage vs. Output Current
VIN Dropout Voltage (mV)
00.5 11.5
VCNTL=5V
VOUT=1.2V
0
50
100
150
200
TJ=25oC
TJ=125oC
TJ=75oC
TJ=0oC
TJ=-25oC
Output Current, lOUT (A)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw7
Operating Waveforms
1.2 Using an MLCC as the Output Capacitor
- COUT=22µF/6.3V (ESR=3mΩ), CIN=22µF/6.3V
- IOUT=10mA to 1.5A to 10mA, Rise time=Fall time=1µs
IOUT = 10mA ->1.5AIOUT = 10mA -> 1.5A ->10mAIOUT = 1.5A ->10mA
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 500mA/Div
Time : 1µs/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 500mA/Div
Time : 20µs/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 500mA/Div
Time : 1µs/Div
1
2
VOUT
IOUT
1
2
VOUT
IOUT
1
2
IOUT
VOUT
R1=39kΩ, R2=78kΩ, C1=56pF
1
2
IOUT
VOUT
R1=39kΩ, R2=78kΩ, C1=56pF
1
2
VOUT
IOUT
1
2
VOUT
IOUT
1. Load Transient Response :
1.1 Using an Output Capacitor with ESR≥18mΩ
- COUT=150µF/6.3V (ESR=30mΩ), CIN=22µF/6.3V
- IOUT=10mA to 1.5A to 10mA, Rise time=Fall time=1µs
IOUT=10mA ->1.5AIOUT=10mA ->1.5A ->10mAIOUT =1.5A ->10mA
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 500mA/Div
Time : 1µs/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 500mA/Div
Time : 20µs/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 500mA/Div
Time : 1µs/Div
1
2
VOUT
IOUT
1
2
VOUT
IOUT
2
1
VOUT
IOUT
2
1
VOUT
IOUT
1
2
IOUT
R1=1kΩ, R2=2kΩ, C1=33nF
VOUT 1
2
IOUT
R1=1kΩ, R2=2kΩ, C1=33nF
VOUT
VOUT
IOUT
VOUT
IOUTIOUT
VOUT
VOUT
VOUT
VOUT
IOUTIOUTIOUT
R1=39kΩ, R2=78kΩ, C1=56pF
R1=1kΩ, R2=2kΩ, C1=33nF
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw8
2
1
3
4
Enable
VEN
VOUT
IOUT
VPOK
2
1
3
4
Enable
VEN
VOUT
IOUT
VPOK
Operating Waveforms (Cont.)
2. Power ON and Power OFF :
- VIN=1.5V, VCNTL=5V, VOUT=1.2V
- COUT=22µF/6.3V (ESR=3mΩ), CIN=22µF/6.3V
Ch1 : VIN, 1V/div
Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div
Ch4 : VCNTL, 2V/div
Time : 10ms/div
Ch1 : VIN, 1V/div
Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div
Ch4 : VCNTL, 2V/div
Time : 50ms/div
1
2
4
3
VIN
VOUT
VCNTL
VPOK
Power ON
1
2
4
3
VIN
VOUT
VCNTL
VPOK
Power ON
2
1
3
4
Power OFF
VIN
VOUT
VPOK VCNTL
VCNTL 2
1
3
4
Power OFF
VIN
VOUT
VPOK VCNTL
VCNTL
3. Shutdown and Enable :
- VIN=1.5V, VCNTL=5V, VOUT=1.2V
- COUT=22µF/6.3V (ESR = 3mΩ), CIN=22µF/6.3V
1
2
4
3
VEN
VOUT
POK IOUT
Shutdown
1
2
4
3
VEN
VOUT
POK IOUT
Shutdown
Ch1 : VEN, 5V/div
Ch2 : VOUT, 1V/div
Ch3 : IOUT, 1A/div
Ch4 : VPOK, 1V/div
Time : 1ms/div
Ch1 : VEN, 5V/div
Ch2 : VOUT, 1V/div
Ch3 : IOUT, 1A/div
Ch4 : VPOK, 1V/div
Time : 1ms/div
VOUT
VIN
VPOK
VPOK
VCNTL
VCNTL
VIN
VOUT
VCNTL
VENVEN
VOUTVOUT
IOUTIOUT
VPOKVPOK
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw9
2
1
3
VOUT
VIN
VPOK
POK Delay
2
1
3
VOUT
VIN
VPOK
POK Delay
4. POK Delay :
- VIN=1.5V, VCNTL=5V, VOUT=1.2V
- COUT=22µF/6.3V (ESR=3mΩ), CIN=22µF/6.3V
Operating Waveforms (Cont.)
Ch1 : VIN, 1V/div
Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div
Time : 1ms/div
VPOK
VOUT
VIN
Pin Description
PIN
NO. NAME FUNCTION
1 GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
2 FB
Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The
output voltage set by the resistor divider is determined by:
)V(
R2
R1
10.8 VOUT
+⋅=
where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A
bypass capacitor may be connected with R1 in parallel to improve load transient response.
3,4 VOUT Out
put of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to
connect a output capacitor with this pin for closed-
responses.
5 VIN,
Exposed
Pad
Main supply input pins for power con
versions. The Exposed Pad provides a very low impedance input
path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce
the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose.
6 VCNTL
Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage
provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On-
Reset
purpose.
7 POK Power-OK signal output pin. This pin is an open-
drain output used to indicate status of output voltage
by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the V
POK
threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK.
8 EN Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-
enabled,
the IC undergoes a new soft-start cycle. When leave this pin open, an internal current source 10µ
A
pulls this pin up to VCNTL voltage, enabling the regulator.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw10
Block Diagram
Typical Application Circuits
+5V
C3
1µFC4
470µF x2
C5
1000µF x2
L2
3.3µH
Q1
APM2014N
UGATE
LGATE 4
VCC
5
GND
3
OCSET
7
PHASE 8
Q2
APM2014N
C2
1µF
2
U2
APW7057
FB
6
BOOT 1
D1
1N4148
R7
2K C7
0.1µF
R5
1.75K
R8
8.2K
C6
0.1µF
Q3
Shutdown
R6
0
R4
2.2
C8
470pF
L1
1µH
C9
47µFVCNTL
+5V
VOUT
+1.2V/1.5A
CVCNTL
1µF
VIN
+1.5V
GND
VOUT
VCNTL
POK
VIN
CIN
22µF
COUT
150µF
EN
Enable EN
POK
R3
1K
7
3
61
8
5
U1
APL5915
R1
1K
C1
33nF
VOUT 4
FB 2
R2
2K
Test Circuit
GND
VOUT
VINVCNTL
Current
Limit
Thermal
Limit
EN
VREF
0.8V
FB
90%
VREF
Delay
POK
Power-
On-Reset
Soft-Start
and
Control Logic
0.4V
UV
EAMP
POK
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw11
Typical Application Circuits (Cont.)
1. Using an Output Capacitor with ESR≥18mΩ
2. Using an MLCC as the Output Capacitor
DESIGNATION DESCRIPTION
22µF ECJ3YBOJ226M
Panasonic
COUT 22µF GRM21BR60J226M
Murata
VOUT (V) R1 (kΩ) R2 (kΩ) C1 (pF)
1.05 43 137.6 47
1.5 27 30.86 82
1.8 15 12 150
VCNTL
+5V
VOUT
+1.2V / 1.5A
VIN
+1.5V
GND
VOUT
VCNTL
POK VIN
CIN
22µF
COUT
150µF
EN
Enable EN
POK
R3
1K 5
3
61
8
7
APL5915
R1
1K
C1
33nF (in the range of 12 ~ 48nF)
VOUT 4
FB 2
R2
2K
CCNTL
1µF
VCNTL
+5V
VOUT
+1.2V / 1.5A
CCNTL
1µF
VIN
+1.5V
GND
VOUT
VCNTL
POK VIN
CIN
22µF
COUT
22µF
EN
Enable EN
POK
R3
1K 5
3
61
8
7
APL5915
R1
39K
C1
56pF
VOUT 4
FB 2
R2
78K
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw12
Function Description
Power-On-Reset
A Power-On-Reset (POR) circuit monitors both input volt-
ages at VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
after the two supply voltages exceed their rising POR
threshold voltages during powering on. The POR func-
tion also pulls low the POK pin regardless the output
voltage when the VCNTL voltage falls below its falling
POR threshold.
Internal Soft-Start
An internal soft-start function controls rising rate of the
output voltage to limit the current surge at start-up. The
typical soft-start interval is about 2ms.
Output Voltage Regulation
An error amplifier works with a temperature-compensated
0.8V reference and an output NMOS regulates output to
the preset voltage. The error amplifier is designed with
high bandwidth and DC gain provides very fast transient
response and less load regulation. It compares the ref-
erence with the feedback voltage and amplifies the differ-
ence to drive the output NMOS which provides load cur-
rent from VIN to VOUT.
Current-Limit
The APL5915 monitors the current via the output NMOS
and limits the maximum current to prevent load and
APL5915 from damages during overload or short-circuit
conditions.
Under-Voltage Protection (UVP)
The APL5915 monitors the voltage on FB pin after soft-
start process is finished. Therefore, the UVP is disable
during soft-start. When the voltage on FB pin falls below
the under-voltage threshold, the UVP circuit shuts off the
output immediately. After a while, the APL5915 starts a
new soft-start to regulate output.
Thermal Shutdown
A thermal shutdown circuit limits the junction tempera-
ture of APL5915. When the junction temperature exceeds
+150°C, a thermal sensor turns off the output NMOS,
allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start cycle
after the junction temperature is cooled by 50°C, result-
ing in a pulsed output during continuous thermal over-
load conditions. The thermal shutdown is designed with
a 50oC hysteresis to lower the average junction tempera-
ture during continuous thermal overload conditions, ex-
tending lifetime of the device.
For normal operation, device power dissipation should
be externally limited so that junction temperatures will
not exceed +125°C.
Enable Control
The APL5915 has a dedicated enable pin (EN). A logic
low signal (VEN<0.3V) applied to this pin shuts down the
output. Following a shutdown, a logic high signal re-en-
ables the output through initiation of a new softstart cycle.
Left open, this pin is pulled up by an internal current source
(10µA typical) to enable operation. It’s not necessary to
use an external transistor to save cost.
Power-OK and Delay
The APL5915 indicates the status of the output voltage by
monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK threshold
(VPOK), an internal delay function starts to perform a delay
time. At the end of the delay time, the IC turns off the
internal NMOS of the POK to indicate the output is OK. As
the VFB falls and reaches the falling Power-OK threshold
(VPNOK), the IC immediately turns on the NMOS of the POK
to indicate the output is not OK without a delay time.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw13
Application Information
Power Sequencing
The power sequencing of VIN and VCNTL is not neces-
sary to be concerned. However, do not apply a voltage to
VOUT for a long time when the main voltage applied at
VIN is not present. The reason is the internal parasitic
diode from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
Output Capacitor
The APL5915 requires a proper output capacitor to
maintain stability and improve transient response over
temperature and current. The output capacitor selection
is to select proper ESR (equivalent series resistance)
and capacitance of the output capacitor for good stability
and load transient response.
The APL5915 is designed with a programmable feedback
compensation adjusted by an external feedback network
for the use of wide ranges of ESR and capacitance in all
applications. Ultra-low-ESR capacitors (such as ceramic
chip capacitors) and low-ESR bulk capacitors (such as
solid Tantalum, POSCap, and Aluminum electrolytic
capacitors) can all be used as an output capacitor. The
value of the output capacitors can be increased without
limit.
During load transients, the output capacitors, depending
on the stepping amplitude and slew rate of load current,
are used to reduce the slew rate of the current seen by
the APL5915 and help the device to minimize the variations
of output voltage for good transient response. For the
applications with large stepping load current, the low-
ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the load
and ground pins as close as possible and the impedance
of the layout must be minimized.
Input Capacitor
The APL5915 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input rail from dropping. Because the parasitic in-
ductor from the voltage sources or other bulk capacitors
to the VIN pin limit the slew rate of the surge currents,
more parasitic inductance needs more input capacitance.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as an input capacitor of VIN. For most of
applications, the recommended input capacitance of VIN
is 10µF at least. If the drop of the input voltage is not
cared, the input capacitance can be less than 10µF. More
capacitance reduces the variations of the input voltage of
VIN pin.
Feedback Network
Figure 1 shows the feedback network among VOUT, GND,
and FB pins. It works with the internal error amplifier to
provide proper frequency response for the linear regulator.
The ESR is the equivalent series resistance of the output
capacitor. The COUT is ideal capacitance in the output
capacitor. The VOUT is the setting of the output voltage.
VERR VFB
R1
R2
C1
VOUT
FB
VOUT
VREF
EAMP
APL5915
COUT
ESR
Figure 1.
The feedback network selection depends on the values
of the ESR and COUT which has been classified into three
conditions:
• Condition 1 : Large ESR ( ≥18mΩ )
- Select the R1 in the range of 400Ω ~ 2.4kΩ
- Calculate the R2 as the following :
- Calculate the C1 as the following :
(1) ..........
0.8(V)-(V)V0.8(V)
)R1(k)R2(k OUT
⋅Ω=Ω
(2) ......
)R1(k(V)V
40C1(nF)
)R1(k(V)V
10 OUTOUT Ω
⋅≤≤
Ω
⋅
• Condition 2 : Middle ESR
- Calculate the R1 as the following:
(3) ......... 15(V)V37.5
)ESR(m
2157
)R1(k OUT +⋅−
Ω
=Ω
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw14
Application Information (Cont.)
Feedback Network (Cont.)
Select a proper R1(selected) to be a little larger than the
calculated R1.
- Calculate the C1 as the following :
[ ]
(4) ........
)R1(k F)(C
101)ESR(m0.71C1(pF) OUT Ω
µ
⋅+Ω⋅=
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller than
the calculated C1.
- The C1 calculated from equation (4) must meet the
following equation:
(5) ..
)R1(k (V)V37.5
1
)ESR(m
143
17.2C1(pF) OUT
Ω
⋅
+⋅
Ω
+⋅≥
Where R1=R1(calculated) from equation (3)
If the C1(calculated) can not meet the equation (5), please
use the Condition 3.
- Use equation (2) to calculate the R2.
• Condition 3 : Low ESR (eg. Ceramic Capacitors)
- Calculate the R1 as the following:
Select a proper R1(selected) to be a little larger than the
calculated R1. The minimum selected R1 is equal to
1kΩ when the calculated R1 is smaller than 1k or
negative.
- Calculate the C1 as the following :
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller than
the calculated C1.
- The C1 calculated from equation (7) must meet the
following equation :
Where R1=R1(calculated) from equation (6)
(6) .. ...........................(V).......V37.5 F)(C300))ESR(m(2.1)R1(k
OUT
OUT
⋅−µ⋅+Ω⋅=Ω
(7) ...............................
)R1(k (V)V37.5
1
F)(C34.2))ESR(m(0.24C1(pF)
OUT
OUT
Ω
⋅
+⋅
µ⋅+Ω⋅=
(8) ............................ F)(C)ESR(m )R1(k (V)V1.25
0.033C1(pF)
OUT
OUT
µ⋅Ω⋅Ω
⋅
+≥
If the C1(calculated) can not meet the equation (8), please
use the Condition 2.
- Use equation (2) to calculate the R2.
The reason to have three conditions described above is
to optimize the load transient responses for all kinds of
the output capacitor. For stability only, the Condition 2,
regardless of equation (5), is enough for all kinds of output
capacitor.
PCB Layout Consideration
1. Please solder the Exposed Pad and VIN together on
the PCB. The main current flow is through the exposed
pad.
2. Please place the input capacitors for VIN and VCNTL
pins near pins as close as possible.
3. Ceramic decoupling capacitors for load must be placed
near the load as close as possible.
4. To place APL5915 and output capacitors near the load
is good for performance.
5. The negative pins of the input and output capacitors
and the GND pin of the APL5915 are con nected to the
ground plane of the load.
6. Please connect PIN 3 and 4 together by a wide track.
7. Large current paths must have wide tracks.
8. See the Typical Application (See Next Page Figure 2)
- Connect the one pin of the R2 to the GND of APL5915
- Connect the one pin of R1 to the Pin 3 of APL5915
- Connect the one pin of C1 to the Pin 3 of APL5915
Figure 2.
VCNTL
VOUT
CCNTL
VIN
GND
VOUT
VCNTLVIN
CIN
COUT
APL5915
R1
C1
VOUT
FB
R2
Load
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw15
Application Information (Cont.)
Thermal Consideration
See Figure 3. The SOP-8P is a cost-effective package
featuring a small size like a standard SOP-8 and a bot-
tom exposed pad to minimize the thermal resistance of
the package, being applicable to high current
applications. The exposed pad must be soldered to the
top VIN plane. The copper of the VIN plane on the Top layer
conducts heat into the PCB and air. Please enlarge the
area to reduce the case-to-ambient resistance (θCA).
Figure 3.
Exposed
Pad
Die Top
VIN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8-P
5
6
7
8
1
2
3
4
Top
VOUT
plane
Exposed
Pad
Die Top
VIN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8P
5
6
7
8
1
2
3
4
Top
VOUT
plane
0.212
0.072
0.050
0.024
1 2 3 4
8 7 6 5
0.118
0.138
Unit : Inch
Recommended Minimum Footprint
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw16
Package Information
SOP-8P
THERMAL
PAD
D
D1
E2
E1
E
eb
h X 45o
c
SEE VIEW A
A2
A
A1
VIEW AL
0.25
GAUGE PLANE
SEATING PLANE
θ
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
0.020
0.010
0.020
0.050
0.006
0.063
MAX.
0.40L
00oC
E
e
h
E1
0.25
D
c
b
0.17
0.31
0.016
1.27
8oC0oC8oC
0.50
1.27 BSC
0.51
0.25
0.050 BSC
0.010
0.012
0.007
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.00
1.25
SOP-8P
MAX.
0.15
1.60
MIN.
0.000
0.049
INCHES
D1 2.50 0.098
2.00 0.079E2
3.50
3.00
0.138
0.118
4.80 5.00 0.189 0.197
3.80 4.00 0.150 0.157
5.80 6.20 0.228 0.244
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw17
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
SOP-8P Tape & Reel 2500
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Application A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8P
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Devices Per Unit
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw18
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw19
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL5915
www.anpec.com.tw20
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838