APL5915 0.8V Reference Ultra Low Dropout (0.2V@1.5A) Linear Regulator Features General Description * The APL5915 is a 1.5A ultra low dropout linear regulator. This product is specifically designed to provide well sup- Ultra Low Dropout - 0.2V(typical) at 1.5A Output Current * ply volatage for motherboards NB and VGA card applications. The IC needs two supply voltages, a control Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable * 0.8V Reference Voltage * High Output Accuracy voltage for the circuitry and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5915 integrates many functions into a single - 1.5% over Line, Load, and Temperature * Fast Transient Response * Adjustable Output Voltage by External Resistors * Power-On-Reset Monitoring on both VCNTL and package. A Power-On-Reset (POR) circuit monitors both supply voltages to prevent wrong operations. Thermal shutdown and current limit functions protect the device against thermal and current over-loads. POK indicates VIN Pins * Internal Soft-Start * Current-Limit Protection * Under-Voltage Protection * Thermal Shutdown with Hysteresis * Power-OK Output with a Delay Time * Shutdown for Standby or Suspend Mode * Simple SOP-8P Package with Exposed Pad * Lead Free and Green Devices Available the output status with time delay which is set internally. It can control other converter for power sequence. The APL5915 is enabled by other power system. Pulling and holding the EN pin below 0.3V to shuts off the output. The APL5915 is available in SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 1~2W applications. (RoHS Compliant) Pin Configuration Applications * GND FB VOUT VOUT Note Book PC Applications * Motherboard Applications * VGA Card Applications 1 8 2 7 3 4 VIN 6 5 EN POK VCNTL VIN SOP-8P (Top View) = Exposed Pad (connected to VIN plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 1 www.anpec.com.tw APL5915 Ordering and Marking Information Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handing Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL5915 Assembly Material Handling Code Temperature Range Package Code APL5915 XXXXX APL5915 KA: XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCNTL Parameter VCNTL Supply Voltage (VCNTL to GND) VIN VIN Supply Voltage (VIN to GND) VI/O EN and FB to GND VPOK POK to GND PD Power Dissipation Rating Unit -0.3 ~ 7 V -0.3 ~ 3.9 V -0.3 ~ VCNTL+0.3 V -0.3 ~ 7 V 2.8 W TJ Junction Temperature 150 o TSTG Storage Temperature -65 ~ 150 o 260 o TSDR Maximum Lead Soldering Temperature, 10 Seconds C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA JC Parameter Typical Value Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8P Junction-to-Case Thermal Resistance (Note 3) SOP-8P Unit 44 o 19 o C/W C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The "Thermal Pad Temperature" is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 8 VIN 7 6 5 Measured Point PCB Copper Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 2 www.anpec.com.tw APL5915 Recommended Operating Conditions Symbol VCNTL Parameter Range Unit 3.1 ~ 6 V 1.1 ~ 3.5 V 0.8 ~ 1.2 0.8 ~ VIN-0.2 V VCNTL Supply Voltage VIN VIN Supply Voltage Output Voltage VOUT VCNTL=3.35% VCNTL=5.05% IOUT VOUT Output Current TJ 0 ~ 1.5 Junction Temperature A o -40 ~ 125 C Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = -40 to 85C, unless otherwise specified. Typical values refer to TA = 25C. Symbol Parameter APL5915 Test Conditions Unit Min. Typ. Max. 0.4 1 2 mA - 180 380 A 2.7 2.9 3.1 V - 0.4 - V 0.8 0.9 1.0 V - 0.5 - V - 0.8 - V SUPPLY CURRENT ICNTL ISD VCNTL Supply Current EN = VCNTL, VFB is well regulated VCNTL Shutdown Current EN = GND POWER-ON-RESET VCNTL POR Threshold VCNTL Rising VCNTL POR Hysteresis VIN POR Threshold VIN Rising VIN POR Hysteresis OUTPUT VOLTAGE VREF Reference Voltage FB =VOUT o Output Voltage Accuracy IOUT=0A ~1.5A, TJ= -40~125 C -1.5 - +1.5 % Line Regulation VCNTL=3.3 ~ 5.5V -0.13 - 0.13 %/V Load Regulation IOUT=0A ~1.5A - 0.06 0.15 % VOUT = 1.2V - 0.12 0.18 VOUT = 2.5V - 0.17 0.23 VOUT = 1.2V - - 0.25 VOUT = 2.5V - - 0.3 VCNTL=5V, TJ= 25oC 2.1 2.8 3.5 VCNTL=5V, TJ= -40 ~ 125oC 1.8 - - DROPOUT VOLTAGE Dropout Voltage IOUT = 1.5A, VCNTL=5V, TJ= 25oC IOUT = 1.5A, VCNTL=5V, TJ= -40~125oC V V PROTECTION ILIM TSD Current Limit Thermal Shutdown Temperature TJ Rising - Thermal Shutdown Hysteresis Under-Voltage Threshold Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 VFB Falling 3 150 A A - o o - 50 - - 0.4 - C C V www.anpec.com.tw APL5915 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = -40 to 85C, unless otherwise specified. Typical values refer to TA = 25C. Symbol Parameter Test Conditions APL5915 Unit Min. Typ. Max. 0.3 0.4 0.5 V - 30 - mV - 10 - A - 2 - ms ENABLE AND SOFT-START EN Logic High Threshold Voltage VEN Rising EN Hysteresis EN Pin Pull-Up Current TSS EN=GND Soft-Start Interval POWER OK AND DELAY VPOK POK Threshold Voltage for Power OK VFB Rising 90% 92% 94% VREF VPNOK POK Threshold Voltage for Power Not OK VFB Falling 79% 81% 83% VREF POK Low Voltage POK sinks 5mA - 0.25 0.4 V 1 3 10 ms TDELAY POK Delay Time Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 4 www.anpec.com.tw APL5915 Typical Operating Characteristics VCNTL Supply Current vs. Junction Temperature Current-Limit vs. Junction Temperature 2.9 VCNTL=5V 0.9 0.8 VCNTL=5V 2.8 Current-limit, ILIM (A) VCNTL Supply Current, ICNTL (mA) 1.0 0.7 0.6 VCNTL=3.3V 0.5 0.4 0.3 0.2 2.7 VCNTL=3.3V 2.6 2.5 0.1 0.0 -50 -25 0 25 50 75 100 Junction Temperature (C) 2.4 -50 125 4.5 0.806 4.3 125 4.1 0.804 0.802 0.800 0.798 0.796 VCNTL=5V 3.9 3.7 3.5 3.3 VCNTL=3.3V 3.1 2.9 0.794 2.7 0.792 -50 -25 0 25 50 75 100 Junction Temperature (C) 2.5 -50 125 -25 VCNTL PSRR vs. Frequency 125 0 VCNTL=5V VCNTL=5V -10 V =200mV IN PK-PK -10 VCNTLPK-PK=200mV VIN=1.5V IOUT=1A -20 V =1.2V OUT -20 IOUT=1A VOUT=1.2V COUT=22F VIN PSRR (dB) -30 0 25 50 75 100 Junction Temperature (C) VIN PSRR vs. Frequency 0 VCNTL PSRR (dB) 0 25 50 75 100 Junction Temperature (C) POK Delay Time vs. Junction Temperature 0.808 POK Delay Time (ms) Reference Voltage, VREF (mV) Reference Voltage vs. Junction Temperature -25 -40 -50 -60 COUT=22F VIN=1.5V -40 -50 VIN=1.8V -60 VIN=1.6V -70 -70 -80 100 -30 -80 1000 10000 100000 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 -90 100 1000000 5 1000 10000 100000 Frequency (Hz) 1000000 www.anpec.com.tw APL5915 Typical Operating Characteristics (Cont.) VIN Dropout Voltage vs. Output Current VIN Dropout Voltage vs. Output Current 200 VCNTL=5V VOUT=2.5V 250 TJ=25oC VIN Dropout Voltage (mV) VIN Dropout Voltage (mV) 300 200 TJ=75oC 150 TJ=125oC TJ=0oC 100 TJ=-25oC 50 0 VCNTL=5V VOUT=1.8V TJ=25oC 150 TJ=75oC 100 TJ=125oC TJ=0oC 50 TJ=-25oC 0 0.5 1 Output Current, lOUT (A) 0 1.5 0 0.5 1 Output Current, lOUT (A) 1.5 VIN Dropout Voltage vs. Output Current 200 VIN Dropout Voltage (mV) VCNTL=5V VOUT=1.2V TJ=25oC 150 TJ=75oC 100 TJ=125oC TJ=0 oC 50 0 TJ=-25oC 0 0.5 1 1.5 Output Current, lOUT (A) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 6 www.anpec.com.tw APL5915 Operating Waveforms 1. Load Transient Response : 1.1 Using an Output Capacitor with ESR18m - COUT=150F/6.3V (ESR=30m), CIN=22F/6.3V - IOUT=10mA to 1.5A to 10mA, Rise time=Fall time=1s IOUT=10mA ->1.5A IOUT=10mA ->1.5A ->10mA VVOUT OUT 1 R1=1k, R2=2k, R1=1k, R2=2k,C1=33nF C1=33nF VVOUT OUT IIOUT OUT IOUT =1.5A ->10mA OUT VVOUT 1 IIOUT OUT IOUT IOUT 2 2 2 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 500mA/Div Time : 1s/Div 1 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 500mA/Div Time : 20s/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 500mA/Div Time : 1s/Div 1.2 Using an MLCC as the Output Capacitor - COUT=22F/6.3V (ESR=3m), CIN=22F/6.3V - IOUT=10mA to 1.5A to 10mA, Rise time=Fall time=1s IOUT = 10mA ->1.5A IOUT = 10mA -> 1.5A ->10mA IOUT = 1.5A ->10mA R1=39k, C1=56pF R1=39k, R2=78k, R2=78k, C1=56pF VVOUT OUT 1 IIOUT OUT VVOUT OUT 1 IIOUT OUT Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 1 IIOUT OUT 2 2 Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 500mA/Div Time : 1s/Div VVOUT OUT Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 500mA/Div Time : 20s/Div 7 2 Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 500mA/Div Time : 1s/Div www.anpec.com.tw APL5915 Operating Waveforms (Cont.) 2. Power ON and Power OFF : - VIN=1.5V, VCNTL=5V, VOUT=1.2V - COUT=22F/6.3V (ESR=3m), CIN=22F/6.3V Power ON Power OFF IN VVIN 1 VVOUT OUT 2 IN VVIN VVCNTL CNTL VVOUT OUT 2 VVCNTL CNTL VVPOK POK VVPOK POK 3 VVCNTL CNTL 1 3 4 4 Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Ch4 : VCNTL, 2V/div Time : 10ms/div Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Ch4 : VCNTL, 2V/div Time : 50ms/div 3. Shutdown and Enable : - VIN=1.5V, VCNTL=5V, VOUT=1.2V - COUT=22F/6.3V (ESR = 3m), CIN=22F/6.3V Shutdown Enable VEN V EN 1 VVOUT OUT 2 IIOUT OUT OUT VVOUT 2 3 PVOK POK 4 Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 1 IIOUT OUT 3 POK VVPOK VEN V EN 4 Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div 8 www.anpec.com.tw APL5915 Operating Waveforms (Cont.) 4. POK Delay : - VIN=1.5V, VCNTL=5V, VOUT=1.2V - COUT=22F/6.3V (ESR=3m), CIN=22F/6.3V VVIN IN 1 POK Delay VVOUT OUT 2 VVPOK POK 3 Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Time : 1ms/div Pin Description PIN NO. NAME 1 GND FUNCTION Ground pin of the circuitry. All voltage levels are measured with respect to this pin. 2 FB Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: R1 VOUT = 0.8 1 + (V) R2 where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient response. 3,4 VOUT Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improve transient responses. 5 VIN, Exposed Pad Main supply input pins for power conversions. The Exposed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. 6 VCNTL Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On-Reset purpose. 7 POK Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. 8 EN Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle. When leave this pin open, an internal current source 10A pulls this pin up to VCNTL voltage, enabling the regulator. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 9 www.anpec.com.tw APL5915 Block Diagram EN VCNTL VIN PowerOn-Reset Soft-Start and Control Logic UV Thermal Limit 0.4V VREF 0.8V EAMP VOUT Current Limit FB Delay POK GND 90% VREF POK Typical Application Circuits Test Circuit R4 C2 1F L1 1H 2.2 +5V 5 C8 R8 8.2K 470pF VCC BOOT 7 PHASE Shutdown C6 0.1F 2 FB VIN +1.5V VCNTL 5 VIN CIN 22F C5 1000F x2 Q2 APM2014N LGATE POK Q1 APM2014N L2 3.3H 4 VCNTL +5V CVCNTL 1F 8 U2 APW7057 6 C9 47F 6 UGATE C4 470F x2 1 OCSET Q3 C3 1F D1 1N4148 POK VOUT VOUT 7 R3 1K VOUT +1.2V/1.5A 3 4 COUT 150F U1 APL5915 GND 3 R5 1.75K EN Enable 8 EN FB GND 1 R7 2K C7 0.1F Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 2 R2 2K R1 1K C1 33nF R6 0 10 www.anpec.com.tw APL5915 Typical Application Circuits (Cont.) 1. Using an Output Capacitor with ESR18m VCNTL +5V CCNTL 1F 6 R3 1K VCNTL 7 POK VIN POK VOUT VOUT 5 VOUT +1.2V / 1.5A 3 4 COUT 150F APL5915 8 EN EN FB 2 GND Enable VIN +1.5V CIN 22F 1 R2 2K R1 1K C1 33nF (in the range of 12 ~ 48nF) 2. Using an MLCC as the Output Capacitor VCNTL +5V CCNTL 1F 6 R3 1K VCNTL 7 POK VIN POK VOUT VOUT 5 VOUT +1.2V / 1.5A 3 4 COUT 22F APL5915 8 EN EN FB 2 GND Enable VIN +1.5V CIN 22F 1 R2 78K R1 39K C1 56pF DESIGNATION DESCRIPTION 22F ECJ3YBOJ226M Panasonic COUT 22F GRM21BR60J226M Murata VOUT (V) R1 (k) R2 (k) C1 (pF) 1.05 43 137.6 47 1.5 27 30.86 82 1.8 15 12 150 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 11 www.anpec.com.tw APL5915 Function Description allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic after the junction temperature is cooled by 50C, resulting in a pulsed output during continuous thermal over- controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR load conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction tempera- threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output ture during continuous thermal overload conditions, extending lifetime of the device. voltage when the VCNTL voltage falls below its falling POR threshold. For normal operation, device power dissipation should be externally limited so that junction temperatures will Internal Soft-Start not exceed +125C. An internal soft-start function controls rising rate of the output voltage to limit the current surge at start-up. The Enable Control typical soft-start interval is about 2ms. The APL5915 has a dedicated enable pin (EN). A logic Output Voltage Regulation low signal (VEN<0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-en- An error amplifier works with a temperature-compensated 0.8V reference and an output NMOS regulates output to ables the output through initiation of a new softstart cycle. Left open, this pin is pulled up by an internal current source the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient (10A typical) to enable operation. It's not necessary to use an external transistor to save cost. response and less load regulation. It compares the reference with the feedback voltage and amplifies the differ- Power-OK and Delay ence to drive the output NMOS which provides load current from VIN to VOUT. The APL5915 indicates the status of the output voltage by Current-Limit (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold The APL5915 monitors the current via the output NMOS and limits the maximum current to prevent load and internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold APL5915 from damages during overload or short-circuit conditions. (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. Under-Voltage Protection (UVP) The APL5915 monitors the voltage on FB pin after softstart process is finished. Therefore, the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5915 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5915. When the junction temperature exceeds +150C, a thermal sensor turns off the output NMOS, Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 12 www.anpec.com.tw APL5915 Application Information capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to can all be used as an input capacitor of VIN. For most of applications, the recommended input capacitance of VIN VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic is 10F at least. If the drop of the input voltage is not cared, the input capacitance can be less than 10F. More diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. capacitance reduces the variations of the input voltage of VIN pin. Output Capacitor Feedback Network The APL5915 requires a proper output capacitor to Figure 1 shows the feedback network among VOUT, GND, and FB pins. It works with the internal error amplifier to maintain stability and improve transient response over temperature and current. The output capacitor selection provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of the output is to select proper ESR (equivalent series resistance) and capacitance of the output capacitor for good stability capacitor. The C OUT is ideal capacitance in the output capacitor. The VOUT is the setting of the output voltage. and load transient response. The APL5915 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all VOUT VOUT applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as APL5915 R1 solid Tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an output capacitor. The VERR value of the output capacitors can be increased without limit. C1 FB VFB EAMP ESR COUT R2 VREF During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5915 and help the device to minimize the variations Figure 1. of output voltage for good transient response. For the applications with large stepping load current, the low- The feedback network selection depends on the values of the ESR and COUT which has been classified into three conditions: ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load * Condition 1 : Large ESR ( 18m ) and ground pins as close as possible and the impedance of the layout must be minimized. - Select the R1 in the range of 400 ~ 2.4k - Calculate the R2 as the following : 0.8(V) .......... (1) VOUT(V) - 0.8(V) - Calculate the C1 as the following : R2(k ) = R1(k) Input Capacitor The APL5915 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic in- 10 ductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, *Condition 2 : Middle ESR - Calculate the R1 as the following: more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 VOUT(V) VOUT(V) C1(nF) 40 ...... (2) R1(k) R1(k) R1(k) = 13 2157 - 37.5 VOUT(V) + 15 ......... (3) ESR(m) www.anpec.com.tw APL5915 Application Information (Cont.) Feedback Network (Cont.) If the C1(calculated) can not meet the equation (8), please use the Condition 2. Select a proper R1(selected) to be a little larger than the - Use equation (2) to calculate the R2. The reason to have three conditions described above is calculated R1. - Calculate the C1 as the following : COUT(F) C1(pF) = [0.71 ESR(m) + 101] ........ (4) R1(k) Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output capacitor. the calculated C1. - The C1 calculated from equation (4) must meet the PCB Layout Consideration 1. Please solder the Exposed Pad and VIN together on the PCB. The main current flow is through the exposed following equation: 143 37.5 VOUT(V) C1(pF) 7.2 1 + 1 + .. (5) R1(k) ESR(m) pad. 2. Please place the input capacitors for VIN and VCNTL Where R1=R1(calculated) from equation (3) If the C1(calculated) can not meet the equation (5), please pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed use the Condition 3. - Use equation (2) to calculate the R2. near the load as close as possible. 4. To place APL5915 and output capacitors near the load *Condition 3 : Low ESR (eg. Ceramic Capacitors) is good for performance. 5. The negative pins of the input and output capacitors - Calculate the R1 as the following: and the GND pin of the APL5915 are con nected to the ground plane of the load. R1(k) = (2.1 ESR(m ) + 300) COUT (F) - 37.5 VOUT (V).................................. .. (6) 6. Please connect PIN 3 and 4 together by a wide track. 7. Large current paths must have wide tracks. Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 8. See the Typical Application (See Next Page Figure 2) - Connect the one pin of the R2 to the GND of APL5915 1k when the calculated R1 is smaller than 1k or negative. - Connect the one pin of R1 to the Pin 3 of APL5915 - Connect the one pin of C1 to the Pin 3 of APL5915 - Calculate the C1 as the following : VCNTL C1(pF) = (0.24 ESR(m) + 34.2) COUT (F) CCNTL 37.5 VOUT (V) 1 + ............................... (7) R1(k) CIN VCNTL APL5915 Select a proper C1(selected) to be a little smaller than the calculated C1. VOUT VOUT VOUT - The C1 calculated from equation (7) must meet the following equation : C1(pF) 0.033 + VIN VIN Where R1=R1(selected) COUT C1 FB Load GND 1.25 VOUT (V) R1(k ) R1 R2 ESR(m ) COUT (F) ............................ (8) Where R1=R1(calculated) from equation (6) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 Figure 2. 14 www.anpec.com.tw APL5915 Application Information (Cont.) Thermal Consideration See Figure 3. The SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (CA). 102 mil 118 mil 1 8 2 7 SOP-8-P SOP-8P 3 6 5 4 Top VOUT plane Die Exposed Pad Top VIN plane Ambient Air PCB Figure 3. Recommended Minimum Footprint 8 7 6 5 0.072 0.024 0.118 0.212 0.138 1 2 0.050 3 4 Unit : Inch Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 15 www.anpec.com.tw APL5915 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L SOP-8P MIN. MAX. A A1 INCHES MILLIMETERS MIN. MAX. 1.60 0.063 0.000 0.15 0.00 0.006 0.049 A2 1.25 b 0.31 0.51 c 0.17 0.25 0.007 0.010 0.197 0.012 0.020 D 4.80 5.00 0.189 D1 2.50 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 0.157 0.118 E1 3.80 4.00 0.150 E2 2.00 3.00 0.079 0.020 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 L 0.40 1.27 0.016 0.050 0o C 8oC 0 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 16 www.anpec.com.tw APL5915 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0 0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.400.20 5.200.20 2.10 0.20 SOP-8P 4.00.10 8.00.10 W E1 12.00.30 1.750.10 F 5.50.05 (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 17 www.anpec.com.tw APL5915 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 18 www.anpec.com.tw APL5915 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 19 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA www.anpec.com.tw APL5915 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 20 www.anpec.com.tw