MC803128K32L-7R5I - Monolithic Memories, Inc.

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 1

MS

YSO

®

• High performance, low power pipeline burst SRAM

 Ultra low power for green PC and battery

powered PC

• High performance

 100-150MHz Speed grades

 3-1-1-1 Burst Read

 1-1-1-1 Burst Write

 3-1-1-1-1-1-1-1... pipeline operation

• Low power

 Low active power

 Ultra low power ZZ standby mode

 Single 3.3V supply (VDD)

 Isolated 3.3V or 2.5V I/O supply (VDDQ)

• Compatibility

 Individual Byte Write and Global Write mask-

ing

 Interleave and burst address support

 Industry standard 100-Pin PBSRAM pinout

 Industry standard PBSRAM specification

• Applications

 Pentium® and PowerPC™ pipelined L2 Cache

 Ideal for high speed, low power communica-

tions buffers

 Power sensitive portable DSP applications

______________________________________________

Overview

The MoSys MC803128K32 is a high performance,

low power pipeline-burst-SRAM (PBSRAM). Fabri-

cated using an advanced low power, high perform-

ance CMOS process, the MoSys MC803128K32 is

backward pin and function compatible with stan-

dard 32Kx32 and 64Kx32 PBSRAMs wit h additional

operating features like low power ZZ standby

mode and linear burst order addressing. These ad-

ditional operating f eatures are def ined so that, wit h

proper implementation, PC boards can work trans-

parently with 32Kx32, 64Kx32, or 128Kx32 conf igu-

rations, allowing the designer maximum configura-

tion flexibility within a single footprint layout.

The MoSys MC803128K32 supports PBSRAM op-

erating modes at maximum burst frequency in-

cluding indefinite pipeline read or writ e (3-1-1-1-1-1-

1...)

Parameter Symbol -10 -7R5 -6R6 Unit

Cycle Time tKC 10 7.5 6.6 ns

Access Time tKQ 5.5 4.5 4 ns

C l ock to High- Z tKQHZ 5 4 3.5 ns

The MC803128K32 is packaged in a standard 100

lead LQFP.

Lowest Power

The MC803128K32 PBSRAMs afford systems

dramatic power savings due to t he benef its of t heir

proprietary MoSys technology. Peak operating

power of a typical PBSRAM is 5x that of the

MC803128K32. Making it ideal for portable applica-

tions, as well as applications requiring a large

amount of RAM.

Part Number Designation

Example

: MC803128K32L-10I

Device Designation:

MC8

:, Series:

03

Organization:

128K32

Package Type:

L

=LQFP

Speed: –

10

100MHz

–

7R5

133MHz

–

6R6

150MHz

Temp:

I

= Industrial Temperature, optional

1

NC, (DQP3) 80 NC, (DQP2)

10

VSSQ 71 VSSQ

19

DQ26 62

CE3#

DQ7

39

2

DQ17 79 DQ16

11

VDDQ 70

A6

VDDQ

31

LBO#

20

VDDQ 61

VDD

VDDQ

40

VSS

3

DQ18 78 DQ15

12

DQ23 69

A7

DQ10

DQ9

32

A5

21

VSSQ 60

VSS

VSSQ

41

VDD

4

VDDQ 77 VDDQ

13

DQ24 68

CE1#33

A4

22

DQ27 59

CLK

DQ6

42

5

VSSQ 76 VSSQ

14

NC 67

CE2

VSS

34

A3

23

DQ28 58

GW#

DQ5

43

6

DQ19 75 DQ14

15

VDD 66

BW4#

NC

35

A2

24

DQ29 57

BWE#

DQ4

44

A10

28

DQ31 53

ADV#

DQ2

48

A14

7

DQ20 74 DQ13

16

NC 65

BW3#

VDD

36

A1

25

DQ30 56

OE#

DQ3

45

A11

29

DQ32 52

A8

DQ1

VIS128KZ

49

A15

8

DQ21 73 DQ12

17

VSS 64

BW2#

ZZ

37

A0

26

VSSQ 55

ADSC#

VSSQ

46

A12

30

NC, (DQP4) 51

A9

NC, (DQP1)

50

A16

9

DQ22 72 DQ11

18

DQ25 63

BW1#

DQ8

38

100

91

82

99

90

81

98

89

97

88

96

87

95

86

94

85

93

84

92

83

27

VDDQ 54

ADSP#

VDDQ

47

A13

100 Pin QFP

20 mm x 14 mm body

0.65 mm nominal pin pitch

NC

Figure 1. Pin Function

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 2

MS

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®

GW#

BWE#

D Q

Address

Re

g

ister

CE#

CLK

D Q

DQ[32:2

B

y

teWrite

Re

g

isters

CLK

D Q

DQ[24:17]

B

y

teWrite

Re

g

isters

CLK

D Q

DQ[16:9

B

y

teWrite

Re

g

isters

CLK

D Q

DQ[8:1]

B

y

teWrite

Re

g

isters

CLK

D Q

Enable

Re

g

ister

CE#

CLK

D Q

Enable

Dela

y

Re

g

ister

CLK

64/128K x 32

Memory

Array

Binar

y

Counter

CLK

CE# Q1

CLR

Out

p

ut

Re

g

ister In

p

ut

Re

g

ister

CLK

ADSC#

ADV#

ADSP#

A[16:0]

BW3#

BW4#

BW2#

BW1#

CE2

CE3#

CE1#

OE#

OE

4

17 15 17

32 32

32 DATA[32:1]

LBO#

Figure 2 Functional Block Diagram

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 3

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Table 1. Pin Description

Pin Number Symbol Type Description

50, 49, 48, 47, 46, 45, 44, 81, 82, 99,

100, 32, 33, 34, 35, 36 ,37 A[16:0] Input Processor Addresses

96,95, 94, 93 BW[4:1]# Input Processor host bus byte enables.

88 GW# Input Global Write from cache controller

87 BWE# Input Byte Write Enable from controller

89 CLK Input Processor host bus clock

98 CE1# Input ADSP# mask and ADSC# chip enable

97 CE2 Input Depth expansion chip enable

92 CE3# Input Depth expansion chip enable

86 OE# Input Asynchronous output enable

83 ADV# Input Burst address counter advance

84 ADSP# Input ADS# of processor

85 ADSC# Input ADS# of controller

64 ZZ Low power sleep mode

31 LBO# Linear Burst Order

29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9,

8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69,

68, 63, 62, 59, 58, 57, 56, 53, 52

DQ[32:1] I/O Data I/O pins

30, 1, 80, 51 NC/DQP[4:1] I/O Data parity I/O pins

16, 38, 39, 42, 43, 66 NC - unused

15, 41, 65, 91 VDD 3.3 Volts Power

17, 40, 67, 90 VSS Ground Ground

4, 11, 20, 27, 54, 61, 70, 77 VDDQ I/O Sup-

ply I/O Buffer Supply

5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O

Ground I/O Buffer Ground

Table 2. Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD Core Supply Voltage 4.0 V

VDDQ I/O Supply Voltage VDDQ VDD +0.5,

VDDQ 4.0 V

Vih Input High Voltage VDDQ +0.5 V

Vil Input Low Voltage VSSQ-0.5 V

Ts Storage Temperature -65 150 °C

Notes: Max Vih is not to exceed maximum VDDQ

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 4

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Table 3. Recommended Operating Conditions

Symbol Parameter Condition Min Max Units

VDD Supply Voltage 3.3V ±5% 3.135 3.465 V

VDDQ I/O Supply Voltage 2.5V +38%/-5% 2.375 3.465 V

Vih Input High Voltage 1.8 VDDQ + .3 V

Vil Input Low Voltage -0.3 0.8 V

Voh Output High Voltage Ioh = -5 mA 2.4 V

Vol Output Low Voltage Iol = 5 mA 0.4 V

Topr Operating Temperature 0 70 °C

Table 4. Absolute Maximum AC Operating Conditions

Symbol Parameter Min Max Units

Vih Input High Voltage 1.8 VDDQ+1.0 V

Vil Input Low Voltage VSSQ - 1.0 0.8 V

tOVR Overshoot/Undershoot Voltage Duration 0.2*tCY ns

tSET Overshoot/Undershoot Settling Time 0.8*tCY ns

Table 5. Maximum DC Current Requirements

Symbol Condition Current Units

IDD Operating current, device selected; all inputs < Vil or > Vih; cycle time > tKC

min, VDD= max, 0 pF load 50 mA

IDD1 Idle current, device selected; ADSP#, ADSC#, GW#, BW#s, ADV# and all other

inputs > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load 10 mA

IDDZ Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max 2mA

Table 6. Maximum DC Current Requirements

Symbol Parameter Max Units

CIInput Pin Capacitance 4 pF

CI/O I/O Pin Capacitance 6 pF

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 5

MS

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®

Table 7. AC Timing Characteristics at Recommended Operating Conditions

-6R6

(150 MHz) -7R5

(133 MHz) -10

(100 MHz)

Sym Parameter Min Max Min Max Min Max Units

tAAH ADV# hold 0.5 0.5 0.5 ns

tAAS ADV# setup 1.5 2 2 ns

tADSH ADSx# hold 0.5 0.5 0.5 ns

tADSS ADSx# setup 1.5 2 2 ns

tAH Address hold 0.5 0.5 0. 5 ns

tAS Address setup 1.5 2 2 ns

tCEH Chip Enable hold 0.5 0.5 0. 5 ns

tCES Chip Enable setup 1.8 2 2 ns

tDH Write Data hold 0.5 0.5 0.5 ns

tDS W rite Data setup 1.5 2 2 ns

tKC Clock cycle 6.6 7.5 10 ns

tKH Cl ock high 1.8 2 3.2 ns

tKL Clock low 1.8 2 3.2 ns

tKQ Clock to output valid 4 4.5 5.5 ns

tKQHZ Clock to output high-Z 1. 5 3.5 1.5 4 1.5 5 ns

tKQLZ Clock t o output low-Z 0 0 0 ns

tKQX Clock to output i nval i d 1.5 1. 5 1.5 ns

tOELZ OE# to out put l ow-Z 0 0 0 ns

tOEHZ OE# to output hi gh-Z 4 4.5 5.5 ns

tOEQ OE# to output valid 4 4.5 5. 5 ns

tOEQX OE# to output invalid 0 0 0 ns

tW S GW#, BW x# setup 1.5 2 2 ns

tW H GW#, BWx# hold 0.5 0.5 0.5 ns

tZZs ZZ standby 100 100 100 ns

tZZREC ZZ recovery 100 100 100

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 6

MS

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®

CLK

ADSP#

ADSC#

ADV#

A[16:0]

GW#

BWE#

BW[4:1]

CE1#

CE2

CE3#

OE#

Data-Out

Data-In

RD1 RD2 RD3

Single Read Burst Read Pipeline Read

1a 2a 2b 2c 2d 3d

tADSS tADSH

tKC

tKLtKH

tADSS tADSH

tAS tAH

tWS tWH

tCES tCEH

tOEQ

tOELZ tOEQX

tKQLZ tKQ

tOEHZ

tKQX

tKQHZ

tKQX

Unselected

Unsele ct e d wit h CE 2CE2 and CE3# only sampled with ADSP# and ADSC#

CE1# masks ADSP#

Suspend Burst

ADSC# initiated read

ADSP# is blocked by CE1# inactive

Figure 3 Read Cycle Timing

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 7

MS

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CLK

ADSP#

ADSC#

ADV#

A[16:0]

GW#

BWE#

BW[4:1]

CE1#

CE2

CE3#

OE#

Data-Out

Data-In

WR1 WR2 WR3

Single Write Burst Write

tADSS tADSH

tKC

tKLtKH

tADSS tADSH

tAS tAH

tWS tWH

tCES tCEH

Write Unselected

WR1 WR2 WR3

1a 3a2d2c2b2a

tDS tDH

Unselected with CE2CE2 and CE3# only sampled with ADSP# and ADSC#

BW[4:1]# only are applied to first cycle of WR2

CE1# msdkd ADSP#

GW# allows processor addresses (and BE#=BW#)

to be pipelined during a writeback

ADV# Must be inactive for ADSP# write

tAAS tAAH

ADSC# initiated write

ADSP# is blocked by CE1# inactive

Figure 4 Write Cycle Timing

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 8

MS

YSO

®

CLK

ADSP#

ADSC#

ADV#

A[16:0]

GW#

BWE#

BW[4:1]

CE1#

CE2

CE3#

OE#

Data-Out

Data-In

RD1 WR1 RD2

Single Read

WR1

Single Write Burst Read

1a

2a 2b 2c 2d

ADSP# is blocked by CE1# inactive

ADSC# initiated read

CE1# masks ADSP#

CE2 and CE3# only sampled with ADSP# and ADSC#

Unselected with CE3#

tADSHtADSS

tAHtAS

tWHtWS

tCEHtCES

tOEHZtOEQ

tOELZ

tKQLZ

tKQ

tOEQX

tDHtDS tKQHZ

tKQZ

Figure 5 Read/Write Cycle Timing

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 9

MS

YSO

®

CLK

ADSP#

ADSC#

ADV#

A[16:0]

GW#

BWE#

BW[4:1]

CE1#

CE2

CE3#

OE#

Data-Out

Data-In

RD1 RD2

Single Read Snooze - With Data Retention

1a

tADSS tADSH

tKC

tKLtKH

tAS tAH

tWS tWH

tCES tCEH

tOEQ

tOELZ tOEQX

tKQLZ tKQ

tOEHZ

Read

tAAS tAAH

tWS tWH

RDRD RD

ZZ

tZZS tZZREC

Figure 6 ZZ and RD Timing

MC803128K32

128Kx32 Pipeline Burst SRAM

DS09, Rev 1.9 – 07/22/99 Page 10

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®

Test and Measurement

Notes 1 Valid Delay Measurement is made from the VDDQ / 2 on the input waveform to the VDDQ / 2 on the output

waveform. Input waveform should have a slew rate of 1V/ns.

2 Tri -st ate t off measurement is made from the VDDQ/2 on the input waveform to the output waveform moving

20% from its initial to final value VDDQ/2.

Output Load

T Measurement

Tri-State Measurement

Input

Waveform

Output

Waveform

V

Capacitive load consists

of all components of

the test environment.

50 W

Output

Buffer

30 pf

Z=50W

V

Input

Waveform

t

Output

Waveform

V=

PLH

tPHL

SS

0

L

VDDQ

2

VDDQ

2

VDDQ

2

VDDQ

2

DLY

t

ON

OFF

H

L

Z

V -(0.2(V -V ))

HHZ

V -(0.2(V -V ))

HLZ

0.2(V -V )

LZ

V +(0.2(V -V ))

HLZ

Test Structure and Measurement Points

Figure 7. LQFP Mechanical Characteristics