MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) * High performance, low power pipeline burst SRAM Overview The MoSys MC803128K32 is a high performance, low power pipeline-burst-SRAM (PBSRAM). Fabricated using an advanced low power, high performance CMOS process, the MoSys MC803128K32 is backward pin and function compatible with standard 32Kx32 and 64Kx32 PBSRAMs with additional operating features like low power ZZ standby mode and linear burst order addressing. These additional operating features are defined so that, with proper implementation, PC boards can work transparently with 32Kx32, 64Kx32, or 128Kx32 configurations, allowing the designer maximum configuration flexibility within a single footprint layout. The MoSys MC803128K32 supports PBSRAM operating modes at maximum burst frequency including indefinite pipeline read or write (3-1-1-1-1-11...) Parameter Symbol -10 -7R5 -6R6 Unit Cycle Time tKC 10 7.5 6.6 ns Access Time tKQ 5.5 4.5 4 ns Clock to High-Z tKQHZ 5 4 3.5 ns 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin QFP 20 mm x 14 mm body 0.65 mm nominal pin pitch 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC, (DQP2) DQ16 DQ15 VDDQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VDDQ DQ10 DQ9 VSS NC VDD ZZ DQ8 DQ7 VDDQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VDDQ DQ2 DQ1 NC, (DQP1) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC, (DQP3) DQ17 DQ18 VDDQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VDDQ DQ23 DQ24 NC VDD NC VSS DQ25 DQ26 VDDQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VDDQ DQ31 DQ32 NC, (DQP4) LBO# A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 Ultra low power for green PC and battery powered PC * High performance 100-150MHz Speed grades 3-1-1-1 Burst Read 1-1-1-1 Burst Write 3-1-1-1-1-1-1-1... pipeline operation * Low power Low active power Ultra low power ZZ standby mode Single 3.3V supply (VDD) Isolated 3.3V or 2.5V I/O supply (VDDQ) * Compatibility Individual Byte Write and Global Write masking Interleave and burst address support Industry standard 100-Pin PBSRAM pinout Industry standard PBSRAM specification * Applications (R) TM Pentium and PowerPC pipelined L2 Cache Ideal for high speed, low power communications buffers Power sensitive portable DSP applications ______________________________________________ A6 A7 CE1# CE2 BW4# BW3# BW2# BW1# CE3# VDD VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A8 A9 VIS128KZ Figure 1. Pin Function The MC803128K32 is packaged in a standard 100 lead LQFP. Lowest Power The MC803128K32 PBSRAMs afford systems dramatic power savings due to the benefits of their proprietary MoSys technology. Peak operating power of a typical PBSRAM is 5x that of the MC803128K32. Making it ideal for portable applications, as well as applications requiring a large amount of RAM. Part Number Designation Example: MC803128K32L-10 I Device Designation: MC8:, Series: 03 Organization: 128K32 Package Type: L=LQFP 100MHz Speed: - 10 - 7R5 133MHz - 6R6 150MHz Temp: I = Industrial Temperature, optional DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 1 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Binary Counter CLK LBO# CLK ADV# ADSC# ADSP# 64/128K x 32 Memory Array CE# Q1 CLR 17 A[16:0] 15 17 D Q Address Register CE# CLK GW# BWE# BW4# D Q DQ[32:2 ByteWrite Registers CLK D 32 32 Q DQ[24:17] ByteWrite BW3# Registers CLK D Q DQ[16:9 ByteWrite Registers CLK BW2# D Q DQ[8:1] BW1# ByteWrite Registers CLK CE1# CE2 CE3# 4 D Q Enable Register CE# CLK Output Register Input Register OE D Q Enable Delay Register CLK OE# 32 DATA[32:1] Figure 2 Functional Block Diagram DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 2 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Table 1. Pin Description Pin Number 50, 49, 48, 47, 46, 45, 44, 81, 82, 99, 100, 32, 33, 34, 35, 36 ,37 96,95, 94, 93 88 87 89 98 97 92 86 83 84 85 64 31 29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9, 8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69, 68, 63, 62, 59, 58, 57, 56, 53, 52 30, 1, 80, 51 16, 38, 39, 42, 43, 66 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 Symbol A[16:0] Type Input Description Processor Addresses BW[4:1]# GW# BWE# CLK CE1# CE2 CE3# OE# ADV# ADSP# ADSC# ZZ LBO# DQ[32:1] Input Input Input Input Input Input Input Input Input Input Input Processor host bus byte enables. Global Write from cache controller Byte Write Enable from controller Processor host bus clock ADSP# mask and ADSC# chip enable Depth expansion chip enable Depth expansion chip enable Asynchronous output enable Burst address counter advance ADS# of processor ADS# of controller Low power sleep mode Linear Burst Order Data I/O pins NC/DQP[4:1] NC VDD VSS VDDQ I/O 3.3 Volts Ground I/O Supply I/O Ground 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Data parity I/O pins unused Power Ground I/O Buffer Supply I/O Buffer Ground Table 2. Absolute Maximum Ratings Symbol VDD Parameter Min Core Supply Voltage VDDQ I/O Supply Voltage Vih Input High Voltage Vil Input Low Voltage Ts Storage Temperature Max Units 4.0 V VDDQ VDD +0.5, V VDDQ 4.0 VDDQ +0.5 VSSQ-0.5 -65 V V 150 C Notes: Max Vih is not to exceed maximum VDDQ DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 3 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Table 3. Recommended Operating Conditions Symbol VDD Parameter Condition Min Max Units 3.3V 5% 3.135 3.465 V 2.5V +38%/-5% 2.375 3.465 V Supply Voltage VDDQ I/O Supply Voltage Vih Input High Voltage 1.8 VDDQ + .3 V Vil Input Low Voltage -0.3 0.8 V Voh Output High Voltage Vol Output Low Voltage Topr Ioh = -5 mA Iol = 5 mA 2.4 Operating Temperature V 0 0.4 V 70 C Table 4. Absolute Maximum AC Operating Conditions Symbol Parameter Min Max Units Vih Input High Voltage 1.8 VDDQ+1.0 V Vil Input Low Voltage VSSQ - 1.0 0.8 V tOVR Overshoot/Undershoot Voltage Duration 0.2*tCY ns tSET Overshoot/Undershoot Settling Time 0.8*tCY ns Table 5. Maximum DC Current Requirements Symbol Condition Current Units IDD Operating current, device selected; all inputs < Vil or > Vih; cycle time > tKC min, VDD= max, 0 pF load 50 mA IDD1 Idle current, device selected; ADSP#, ADSC#, GW#, BW#s, ADV# and all other inputs > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load 10 mA IDDZ Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max 2 mA Max Units Table 6. Maximum DC Current Requirements Symbol Parameter CI Input Pin Capacitance 4 pF CI/O I/O Pin Capacitance 6 pF DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 4 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Table 7. AC Timing Characteristics at Recommended Operating Conditions -6R6 (150 MHz) Sym Parameter Min Max -7R5 (133 MHz) Min Max -10 (100 MHz) Min Max Units tAAH ADV# hold 0.5 0.5 0.5 ns tAAS ADV# setup 1.5 2 2 ns tADSH ADSx# hold 0.5 0.5 0.5 ns tADSS ADSx# setup 1.5 2 2 ns tAH Address hold 0.5 0.5 0.5 ns tAS Address setup 1.5 2 2 ns tCEH Chip Enable hold 0.5 0.5 0.5 ns tCES Chip Enable setup 1.8 2 2 ns tDH Write Data hold 0.5 0.5 0.5 ns tDS Write Data setup 1.5 2 2 ns tKC Clock cycle 6.6 7.5 10 ns tKH Clock high 1.8 2 3.2 ns tKL Clock low 1.8 2 3.2 ns tKQ Clock to output valid tKQHZ Clock to output high-Z 1.5 tKQLZ Clock to output low-Z 0 0 0 ns tKQX Clock to output invalid 1.5 1.5 1.5 ns tOELZ OE# to output low-Z 0 0 0 ns tOEHZ OE# to output high-Z 4 4.5 5.5 ns tOEQ OE# to output valid 4 4.5 5.5 ns tOEQX OE# to output invalid tWS 4 3.5 4.5 1.5 4 1.5 5.5 ns 5 ns 0 0 0 ns GW#, BWx# setup 1.5 2 2 ns tWH GW#, BWx# hold 0.5 0.5 0.5 ns tZZs ZZ standby tZZREC ZZ recovery 100 100 100 100 100 ns 100 DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 5 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Pipeline Read Unselected Burst Read Single Read tKC CLK tADSS tADSH tKH tKL ADSP# is blocked by CE1# inactive ADSP# tADSS tADSH ADSC# initiated read ADSC# Suspend Burst ADV# tAS A[16:0] tAH RD1 RD2 tWS tWH tWS tWH RD3 GW# BWE# BW[4:1] tCES tCEH tCES tCEH tCES tCEH CE1# masks ADSP# CE1# CE2 and CE3# only sampled with ADSP# and ADSC# Unselected with CE2 CE2 CE3# tOEQ tOEHZ OE# tOELZ Data-Out tOEQX 1a tKQLZ tKQX 2a tKQX 2b tKQ 2c 2d 3d tKQHZ Data-In Figure 3 Read Cycle Timing DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 6 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Single Write Burst Write Write Unselected tKC CLK tADSS tADSH tKH tKL ADSP# is blocked by CE1# inactive ADSP# tADSS tADSH tAAS tAAH ADSC# initiated write ADSC# ADV# tAS A[16:0] tAH WR1 ADV# Must be inactive for ADSP# write WR2 tWS tWH tWS tWH WR3 GW# allows processor addresses (and BE#=BW#) to be pipelined during a writeback GW# BWE# BW[4:1] WR1 tCES tCEH tCES tCEH tCES tCEH WR2 WR3 CE1# msdkd ADSP# CE1# CE2 and CE3# only sampled with ADSP# and ADSC# Unselected with CE2 CE2 CE3# OE# Data-Out tDS Data-In tDH 1a BW[4:1]# only are applied to first cycle of WR2 2a 2b 2c 2d 3a Figure 4 Write Cycle Timing DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 7 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Single Read Single Write Burst Read CLK tADSS tADSH ADSP# is blocked by CE1# inactive ADSP# tADSS tADSH ADSC# initiated read ADSC# tADSS tADSH ADV# tAS A[16:0] tAH RD1 WR1 tWS tWH tWS tWH RD2 GW# BWE# tWS BW[4:1] tWH WR1 tCES tCEH tCES tCEH tCES tCEH CE1# masks ADSP# CE1# CE2 and CE3# only sampled with ADSP# and ADSC# CE2 Unselected with CE3# CE3# tOEQ tOEHZ OE# tOELZ Data-Out tKQZ tOEQX 1a tKQLZ tKQ Data-In 2a tDS tDH 2b 2c 2d tKQHZ 1a Figure 5 Read/Write Cycle Timing DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 8 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Single Read Read Snooze - With Data Retention tKC CLK tADSS tADSH tKH tKL ADSP# ADSC# tAAS tAAH ADV# tAS tAH RD1 A[16:0] RD2 tWS tWH GW# tWS tWH tWS tWH BWE# RD BW[4:1] tCES tCEH tCES tCEH tCES tCEH RD RD CE1# CE2 CE3# tOEHZ tOEQ OE# tOELZ Data-Out tOEQX 1a tKQLZ tKQ Data-In tZZS tZZREC ZZ Figure 6 ZZ and RD Timing DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 9 MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS (R) Test and Measurement Tri-State Measurement Input Waveform Output Waveform t OFF TDLY Measurement VDDQ 2 Input Waveform VDDQ 2 t ON VH VL VH -(0.2(VH -VZ )) V +(0.2(V -V )) Z H L VZ VZ -(0.2(VH-VL )) 0.2(VZ -VL ) Z 0 = 50 W tPHL t PLH VDDQ 2 Output Waveform Output Load Output Buffer 50 W VL = VDDQ 2 30 pf Capacitive load consists VSS of all components of the test environment. Test Structure and Measurement Points Notes 1 Valid Delay Measurement is made from the VDDQ / 2 on the input waveform to the VDDQ / 2 on the output waveform. Input waveform should have a slew rate of 1V/ns. 2 Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final value VDDQ/2. Figure 7. LQFP Mechanical Characteristics DS09, Rev 1.9 - 07/22/99 (c) 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086 Page 10