TPA5050
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FEATURES APPLICATIONS
DESCRIPTION
SIMPLIFIED APPLICATION DIAGRAM
BCLK
LRCLK
DATA DATA_OUT
3
3.3V
BCLK
LRCLK
DATA
TPA5050
Digital Amplifier
SCLK
AudioProcessor
SCLK
BCLK
LRCLK
DATA
SDA
SCL
ADDx
(2:0)
I CDelay
Control
2
VDD
GND
TAS3103A
or
ATSC
Processor
TAS5504A
+TAS5122
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I
2
C CONTROL
•High Definition TV Lip-Sync Delay•Digital Audio Formats: 16-24-bit I
2
S,Right-Justified, Left-Justified
•Flat Panel TV Lip-Sync Delay•Home Theater Rear-Channel Effects•I
2
C Bus Controlled
•Wireless Speaker Front-Channel•Single Serial Input Port
Synchronization•Delay Time: 170 ms/ch at fs = 48 kHz•Delay Resolution: One Sample•Delay Memory Cleared on Power-Up or After
The TPA5050 accepts a single serial audio input,Delay Changes
buffers the data for a selectable period of time, and– Eliminates Erroneous Data From Being
outputs the delayed audio data on a single serialOutput
output. One device allows delay of up to 170 ms/ch(fs = 48 kHz) to synchronize the audio stream to the•3.3 V Operation With 5 V Tolerant I/O and I
2
C
video stream in systems with complex videoControl
processing algorithms. If more delay is needed, the•Supports Audio Bit Clock Rates of 32 to 64 fs
devices can be connected in series.with fs = 32 kHz–192 kHz•No external crystal or oscillator required– All Internal Clocks Generated From theAudio Clock•Surface Mount 4mm ×4mm, 16-pin QFNPackage
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN DESCRIPTIONS
BCLK
DATA_OUT
GND
VDD
ADD1
LRCLK
SCL
GND
ADD0
ADD2
GND
DATA
7
5
6
11
9
10
12
16
15
14
13
3
1
2
4
SDA
8
GND
GND
GND
RSA (QFN)PACKAGE
(TOP VIEW)
FUNCTIONAL BLOCK DIAGRAM
DATA
BCLK
LRCLK
INPUT
BUFFER
OUTPUT
BUFFER DATA_OUT
CONTROL
2
3
I C
2
ADDx(2:0)
DELAY
MEMORY
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
ADD0 10 I I
2
C address select pin – LSBADD1 11 I I
2
C address select pinADD2 12 I I
2
C address select pin – MSBBCLK 16 I Audio data bit clock input for serial input. 5V tolerant input.DATA 2 I Audio serial data input for serial input. 5V tolerant input.DATA_OUT 15 O Delayed audio serial data output.GND 5–9, 14 P Ground – All ground terminals must be tied to GND for proper operationLRCLK 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input.SCL 3 I I
2
C communication bus clock input. 5V tolerant input.SDA 4 I/O I
2
C communication bus data input. 5V tolerant input.VDD 13 P Power supply interface.Connect to ground. Must be soldered down in all applications to properly secure device on theThermal Pad -
PCB.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
over operating free-air temperature (unless otherwise noted)
(1)
VALUE UNIT
V
DD
Supply voltage –0.3 to 3.6 VDATA, LRCLK, BCLK, SCL, SDA –0.3 to 5.5 VV
I
Input voltage
ADD[2:0] –0.3 to VDD+0.3Continuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range –40 to 85 °CT
J
Operating junction temperature range –40 to 125 °CT
stg
Storage temperature range –65 to 125 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE T
A
≤25 °C DERATING T
A
= 70 °C T
A
= 85 °CPOWER RATING FACTOR POWER RATING POWER RATING
RSA 2.5 W 25mW/ °C 1.375 W 1.0 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad mustbe soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017 D and SLUA271 for more information aboutusing the QFN thermal pad.
MIN MAX UNIT
V
DD
Supply voltage VDD 3 3.6 VV
IH
High-level input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] 2 VV
IL
Low-level input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] 0.8 VT
A
Operating free-air temperature –40 85 °C
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DC CHARACTERISTICS
TIMING CHARACTERISTICS
(1) (2)
SCL
SDA
tw(H) tw(L)
tsu1 th1
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition StopCondition
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
T
A
= 25 °C, V
DD
= 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
DD
Supply current V
DD
= 3.3 V, fs = 48 kHz, BCLK = 32 fs 1.5 3 mAI
OH
High-level output current DATA_OUT = 2.6 V 7 13 mAI
OL
Low-level output current DATA_OUT = 0.4 V 7 13 mADATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V 20I
IH
High-level input current µAADD[2:0], Vi = 3.6V, VDD = 3.6V 5DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0], Vi = 0V,I
IL
Low-level input current 1 µAVDD = 3.6V
For I
2
C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHzt
w(H)
Pulse duration, SCL high 0.6 µst
w(L)
Pulse duration, SCL low 1.3 µst
su1
Setup time, SDA to SCL 100 nst
h1
Hold time, SCL to SDA 10 nst
(buf)
Bus free time between stop and start condition 1.3 µst
su2
Setup time, SCL to start condition 0.6 µst
h2
Hold time, start condition to SCL 0.6 µst
su3
Setup time, SCL to stop condition 0.6 µs
(1) V
Pull-up
= V
DD(2) A pull-up resistor ≤2 k Ωis required for a 5 V I
2
C bus voltage.
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
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Serial Audio Input Ports
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
AUDIO DATA FORMATS AND TIMING
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
Frequency, BCLK 32 ×fs, 48 ×fs, 64 ×fs 1.024 12.288 MHzt
su1
Setup time, LRCLK to BCLK rising edge 10 nst
h1
Hold time, LRCLK from BCLK rising edge 10 nst
su2
Setup time, DATA to BCLK rising edge 10 nst
h2
Hold time, DATA from BCLK rising edge 10 nsLRCLK frequency 32 48 192 kHzBCLK duty cycle 50%LRCLK duty cycle 50%BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 64 BCLK edges
Figure 3. Serial Data Interface Timing
The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK,BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA intothe serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge ofBCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers ofthe serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64times the sampling frequency for right-justified, left-justified, and I
2
S formats. A system clock is not necessary forthe operation of the TPA5050.
The TPA5050 supports industry-standard audio data formats, including right-justified, I
2
S, and left-justified. Thedata formats are shown in Figure 4 . Data formats are selected using the I
2
C interface and register map (seeTable 1 ).
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LRCK
(2)I2SDataFormat;L-Channel=LOW,R-Channel=HIGH
MSB LSB
1/fS
(= 32fS,48fS, or64fS)
18-BitRight-Justified,BCK=48f Sor64fS
1/fS
(1) Right-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
(3)Left-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
MSB LSB
20-Bit Right-Justified,BCK=48f Sor64fS
MSB LSB
24-BitRight-Justified,BCK=48f Sor64fS
1/fS
(=32fS,48fS, or64fS)
(=32fS,48fS, or64fS)
MSB LSB
16-BitRight-Justified,BCK=32f S
16-BitRight-Justified,BCK=48f Sor64fS
MSB LSB
L-Channel R-Channel
BCK
DATA 14 15 16 1 2 3 14 15 16
14 15 16 1 2 3 14 15 16
16 17 18
DATA
DATA
DATA
DATA
1 2 3 16 17 18
18 19 20 1 2 3 18 19 20
22 23 24 1 2 3
MSB LSB
MSB LSB
MSB LSB
MSB LSB
1 2 3 14 15 16
1 2 3 14 15 16
1 2 3 16 17 18
1 2 3 18 19 20
22 23 24
MSB LSB
1 2 3 22 23 24
L-Channel R-ChannelLRCK
BCK
DATA 1 2 3 1 2
MSB
N–2 N
N–1
LSB
1 2 3
MSB
N–2 N
N–1
LSB
L-Channel R-Channel
LRCK
BCK
DATA 1 2 3 N–2 N
N–1 1 2 3 N–2 N
N–1 1 2
MSB LSB LSBMSB
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
Figure 4. Audio Data Formats
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GENERAL I
2
C OPERATION
Register(N)
8-BitDatafor 8-BitDatafor
Register(N+1)
SINGLE-AND MULTIPLE-BYTE TRANSFERS
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
The I
2
C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in asystem. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus isacknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the masterdevice driving a start condition on the bus and ends with the master device driving a stop condition on the bus.The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bittransitions must occur within the low time of the clock period. These conditions are shown in Figure 5 . Themaster generates the 7-bit slave address and the read/write (R/W) bit to open communication with anotherdevice and then wait for an acknowledge condition. The TPA5050 holds SDA low during acknowledge clockperiod to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence.Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices sharethe same signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. Whenthe bus level is 5 V, pull-up resistors between 1 k Ωand 2 k Ωin value must be used.
Figure 5. Typical I
2
C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When thelast word transfers, the master generates a stop condition to release the bus. A generic data transfer sequenceis shown in Figure 5 .
The 7-bit address for the TPA5050 is selectable using the 3 address pins (ADD2, ADD1, ADD0). Table 1 liststhe 8 possible slave addresses.
Table 1. I
2
C Slave Address
SELECTABLE ADDRESS BITSFIXED ADDRESS
(4 MSB bits)
ADD2 ADD1 ADD0
1101 0 0 01101 0 0 11101 0 1 01101 0 1 11101 1 0 01101 1 0 11101 1 1 01101 1 1 1
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA5050 responds with data, a byte at a time, starting at the registerassigned, as long as the master device continues to respond with acknowledges.
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SINGLE-BYTE WRITE
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register DataByte
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
Register
SINGLE-BYTE READ
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
The TPA5050 supports sequential I
2
C addressing. For write transactions, if a register is issued followed by datafor that register and all the remaining registers that follow, a sequential I
2
C write transaction has taken place. ForI
2
C sequential write transactions, the register issued then serves as the starting point, and the amount of datasubsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
As shown is Figure 6 , a single-byte data write transfer begins with the master device transmitting a startcondition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction ofthe data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I
2
Cdevice address and the read/write bit, the TPA5050 responds with an acknowledge bit. Next, the mastertransmits the register byte corresponding to the TPA5050 internal memory address being accessed. Afterreceiving the register byte, the TPA5050 again responds with an acknowledge bit. Next, the master devicetransmits the data byte to be written to the memory address being accessed. After receiving the data byte, theTPA5050 again responds with an acknowledge bit. Finally, the master device transmits a stop condition tocomplete the single-byte data write transfer.
Figure 6. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytesare transmitted by the master device to the TPA5050 as shown in Figure 7 . After receiving each data byte, theTPA5050 responds with an acknowledge bit.
Figure 7. Multiple-Byte Write Transfer
As shown in Figure 8 , a single-byte data read transfer begins with the master device transmitting a startcondition followed by the I2C device address and the read/write bit. For the data read transfer, both a writefollowed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memoryaddress to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA5050 address and the read/write bit, the TPA5050 responds with an acknowledge bit.The master then sends the internal memory address byte, after which the TPA5050 issues an acknowledge bit.The master device transmits another start condition followed by the TPA5050 address and the read/write bitagain. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA5050 transmits the databyte from the memory address being read. After receiving the data byte, the master device transmits anot-acknowledge followed by a stop condition to complete the single-byte data read transfer.
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A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register DataByte
D7 D6 D1 D0 ACK
I2CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6 A0 ACK
Acknowledge
I2CDeviceAddressand
Read/WriteBit
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition Not
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
TPA5050 Operation
VDD
DATA
LRCLK
BCLK
GND
DATA_OUT
SDA
SCL
ADD0
ADD1
ADD2
GND
3.3V
0.1 Fm
Digital Audio
WordClock
BitClock
Delayed Audio
I CClock
2
I CData
2
I C Address
Select
2
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Figure 8. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytesare transmitted by the TPA5050 to the master device as shown in Figure 9 . With the exception of the last databyte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 9. Multiple-Byte Read Transfer
The following sections describe the registers configurable via I
2
C commands for the TPA5050.
Only a single decoupling capacitor (0.1 µF–1 µF) is required across VDD and GND. The ADDx terminals can bedirectly connected to VDD or GND. Table 1 describes the I
2
C addresses selectable via the ADDx terminals. Aschematic implementation of the TPA5050 is shown in Figure 10 .
Figure 10. TPA5050 Schematic
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SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01)
AUDIO DELAY REGISTERS (0x02–0x05)
FRAME DELAY REGISTERS (0x06)
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Table 2. Serial Control Register Summary
REGISTER REGISTER NAME NO. OF CONTENTS INITIALIZATIONBYTES VALUE
0x01 Control Register 1 Description shown in subsequent section 000x02 Right Delay Upper (5 bits) 1 Description shown in subsequent section 000x03 Right Delay Lower (8 bits) 1 Description shown in subsequent section 000x04 Left Delay Upper (5 bits) 1 Description shown in subsequent section 000x05 Left Delay Lower (8 bits) 1 Description shown in subsequent section 000x06 Frame Delay 1 Description shown in subsequent section 000x07 RJ Packet Length 1 Description shown in subsequent section 000x08 Complete Update 1 Description shown in subsequent section 00
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I
2
S,Right-Justified, or Left-Justified.
Table 3. Control Registers (0x01)
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 X X X X – – Left and Right channel are active.
0 1 X X X X – – Left channel is MUTED.1 0 X X X X – – Right channel is MUTED.1 1 X X X X – – Left and Right channel are MUTED.– – X X X X 0 0 I
2
S data format
– – X X X X 0 1 Right-justified data format (see PACKET LENGTH register 0x07)– – X X X X 1 0 Left-justified data format– – X X X X 1 1 Bypass mode – data is passed straight through without delay.
(1) Default values are in bold.
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper andlower registers as specified in Table 1 . A multiple byte transfer should be performed starting with the controlregister and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.The decimal value of D0–D12 equals the number of samples to delay. The maximum number of delayedsamples is 8191 for the TPA5050. This equates to 170.65 ms [8191 ×(1/fs)] at 48 kHz.
Table 4. Audio Delay Registers (0x02–0x05)
(1)
D12 D11 D10–D2 D1 D0 FUNCTION
0 0 0 0 0 Left and Right audio is passed to output with no delay.
0 0 0 0 1 Left and Right audio is delayed by 1 sample (1/fs = delay time)1 1 1 1 1 Left and Right audio is delayed by 8191 samples (8191/fs = delay time)
(1) Default values are in bold.
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delaybased on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:Audio Delay (in samples) = int [# Delay Frames ×(1/Frame Rate) ×Audio Sample Rate]
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RJ PACKET LENGTH REGISTERS (0x07)
COMPLETE UPDATE REGISTER (0x08)
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
If the result of the formula above is greater than the maximum number of delay samples (8191 for TPA5050),then the value is limited to this maximum before passing to the delay block.
Table 5. Frame Delay Registers (0x06)
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Settings in this register are masked and audio delay is determined bysettings in the right/left audio delay registers.
1 Right/left audio delay registers are masked and delay is determined by settings inthis register.
0 Frame rate = 50 Hz
1 Frame rate = 59.94 Hz
0 0 0 Audio sample rate = 32 kHz
0 0 1 Audio sample rate = 44.1 kHz0 1 0 Audio sample rate = 48 kHz0 1 1 Audio sample rate = 88.2 kHz1 0 0 Audio sample rate = 96 kHz1 0 1 Audio sample rate = 176.4 kHz1 1 0 Audio sample rate = 192 kHz1 1 1 Audio sample rate = 192 kHz
0 0 0 Delay frames = 1
0 0 1 Delay frames = 21 1 1 Delay frames = 8
(1) Default values are in bold.
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of theuseable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions mustbe greater than or equal to the packet length selected in this register. The maximum packet length value is 24bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits.
Table 6. RJ Package Length (0x07)
(1)
D5 D4 D3 D2 D1 D0 FUNCTION
000000Packet length = 0 bits0 0 0 0 0 1 Packet length = 1 bits0 1 1 X X X Packet length = 24 bits
(1) Default values are in bold.
Since the audio delay values are divided among several registers, it is likely that multiple writes would benecessary to configure the device. This may cause interruptions in the audio stream and unwanted pops andclicks might occur as register data is passed to delay functional block.
To avoid this from happening, the Complete Update register is used to transfer the user settings from theregister file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data havepassed.
Note that the individual channels can be muted using the upper bits of the Control Registers without writing tothe Complete Update registers.
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APPLICATION EXAMPLES
Single Byte Write
D2Start ACK 01 ACK C0 ACK Stop
TPA5050 Addressand
Write
Register Address Data
Multiple Byte Write
D2Start ACK
01 00 0F
ACK
Stop
TPA5050 Addressand
Write
Register Address
(ControlRegister)
Data
(RightDelayUpperBits)
ACK ACK FF ACK
Data
(ControlRegister)
Data
(RightDelayLowerBits)
10 ACK
00 00 00
ACK
Data
(LeftDelayUpperBits)
Data
(RJPacket=0Bits)
ACK ACK 01 ACK
Data
(FrameDelay)
Data
(CompleteUpdate)
Data
(LeftDelayLowerBits)
Combination Single Byte Write and Sequential Write
D2
Start ACK 01 ACK 01 ACK Stop
TPA5050 Addressand
Write
Register Address
(ControlRegister)
Data
(ControlRegister)
D2Start ACK 06 ACK 91 ACK 10
TPA5050 Addressand
Write
Register Address
(FrameDelay)
Data
(FrameDelay)
01
ACK
Data
(RJPacket=16Bits)
Stop
Data
(CompleteUpdate)
ACK
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Table 7. Complete Update Registers (0x08)
(1)
D7–D1 D0 FUNCTION
X0 No data from the register settings is passed to the delay block.
X 1 Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
(1) Default values are in bold.
The following are some examples of I
2
C commands used to read or write to the TPA5050. For all conditions,assume the address of the TPA5050 is set to 001.
In this example, the TPA5050 is set to mute both left and right channels, and to operate in I
2
S mode.
In this example, the TPA5050 is set to make both the left and right channels active, operate in I
2
S mode, delaythe right channel by 4095 samples, and delay the left channel by 4096 samples. This is a sequential write, so allregisters must have data written to them.
In this example, the TPA5050 is set to operate in the Right Justified mode, with a packet length of 16 bits. Thedevice is to delay the audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs)= 48 kHz, and the Frame rate = 50 Hz. This is a combination of single writes and a sequential write. Since theRight Justified mode is set in the Control Register, and the Frame Delay is set in register 0x06, the data inregisters 0x02–0x05 can be ignored.
Note that in every circumstance where a delay was written into the memory of the TPA5050, a 1must be writtento the Complete Data register for the change to take effect. This does not apply to muting, which occurs in theControl register.
12
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Single Byte Read
D2
Start ACK 01 ACK Start D3 XX
TPA5050 Addressand
Write
Register Address
(ControlRegister)
Stop
ACK
DataRead
(ControlRegister)
No
ACK
TPA5050 Addressand
Read
Multiple Byte Read
XX ACK
XX XX XX
DataRead
(FrameDelay)
DataRead
(LeftDelayUpper)
ACK ACK XX ACK
DataRead
(RightDelayLower)
D2
Start ACK
01 Start ACK
D3
TPA5050 Addressand
Read
Register Address
(ControlRegister)
ACK XX ACK XX
DataRead
(ControlRegister)
TPA5050 Addressand
Write
ACK
XX Stop
No
ACK
DataRead
(CompleteUpdate)
DataRead
(LeftDelayLower)
DataRead
(RJPacketLength)
ACK
DataRead
(RightDelayUpper)
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by isread by the master device, the master device issues a Not Acknowledge, before stopping the communication.
Often, when it is necessary to read what is contained in one register, it is necessary to determine whatinformation is contained in all registers. In such a case, a sequential read should be used. In situations wheredata must be read from a register at the beginning (0x01), and a register towards the end (0x07), a sequentialread is likely to be faster to implement than multiple single byte reads.
In this example, a sequential read is initiated with the Control Register (0x01), and ends with the CompleteUpdate Register (0x08).
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DEVICE CURRENT CONSUMPTION
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
32 52 72 92 112 132 152 172 192
fs-SamplingFrequency-kHz
I-SupplyCurrent-mA
DD
V =3.6V
DD
V =3.3V
DD
V =3V
DD
BCLK=64fs
Data=24bit
SUPPLY CURRENT
vs
SAMPLINGFREQUENCY
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
The TPA5050 draws different amounts of supply current depending upon the conditions under which it isoperated. As V
DD
increases, so too does I
DD
. Likewise, as V
DD
decreases, I
DD
decreases. The same is true ofthe sampling frequency, fs. An increase in fs causes an increase in I
DD
.Figure 11 illustrates the relationshipbetween operating condition and typical supply current.
Figure 11. Typical Supply Current
14
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA5050RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5050RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5050RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5050RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA5050RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA5050RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA5050RSAR QFN RSA 16 3000 367.0 367.0 35.0
TPA5050RSAT QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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