NE C ELECTRONICS INC GLE D MM G42752S 0035324 775 MRNECE NEC ar 16,384 x 1-Bit NEC Electronics Inc. 10K ECL RAM T= 6+ 22-0 Description Pin Configurations The LPB10480 is a very high-speed 10K interface ECL _29-Pin Cerdip 25g RAM organized as 16,384 words by 1 bit and designed with noninverted, open-emitter outputs and low power consumption. Two versions with fast access times of m0 4 , * Db ne 10 ns and 15ns maximum are available in hermetic, A, q3 it 300-mil, 20-pin cerdip or 20-pin ceramic flatpack pack- Ag+ @ whwe aging. Ag O15 3 1810 Aig Ags =& 18P Ave Features Ag Oi7 14 Any ; ae Ag Oa A O 16,384-word x 1-bit organization ho le a ho. O 10K ECL interface Vee C10 1B Ag O Noninverted, open-emitter outputs aatt-5190A O Fast access times Low power consumption . CD 300-mil, 20-pin cerdip or 20-pin ceramic flatpack 20-Pin Ceramic Flatpack packaging 4 Voc Ordering Information 2 DL 3 cs Power rr Access Consumption ; 8 WE PartNumber Time (max) (max) Package ; 2 nt a 12 yPB10480D-10 10 ns 1.4W 20-pin cerdip 7 = Ait D-15 15 ns 1.3W 8 Aig pPB10480B-10 40 ns 1L4W 20-pin ceramic "0 n BAS 15 ns 13W flatpack sensi 60034NE C ELECTRONICS INC bLE D MM 6427525 0035325 601 MENECE PB10480 N; KC Pin identification Absolute Maximum Ratings Symbol Function Supply voltage, Vee -7.0 to +0.5V Ag - Aig Address inputs input voltage, Viy Veg to +0.5V Dd} Data input Output current, lout 30 to +0.1 mA DO Data output Storage temperature, Tstg -65 to + 150C ts Chip select Storage temperature undor bias, Tstg (bias) -55 to + 125C WE Write enable Exposure to Absolute Maximum Ratings for extended periods may Voc Ground affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits specified Vee ~5.2-volt power supply under DC and AG Characteristics. Capacitance Truth Table f = 1 MHz = = cs WE Din Output Mode Parameter Symbol Min Typ Max Unit out a S a - H xX x L Not selected Input capacitance ~ ; pa " 5 5 _ L L L L Write 0 utput capacitance eee OuT P L L H L write 1 L H x Dour Read Notes: (1) X = don't care. Block Diagram A2 A X-Address Word Memory Cell DO AL Decoder Driver Array 128 x 128 4 As Ag Sense Amp. and cs Write Divers WE Y-Address Decoder DI Az Ag Ag Ajo Ais Ata Ars AUH-49928NE ELECTRONICS INC BLE D MM 6427525 0035326 S48 MINECE NV: KE Cc #PB10480 DC Characteristics Ta = Oto +75C; Veg = -5.2 V; output bad = 500 to -2.0V Parameter Symbol Min Typ Max Unit Test Conditions Output voltage, high Vou -1000 -840 mV Vin & Vig max or Vip min; Ta = 0C -960 ~810 mV Vin = Vig max or Vip min; Ta = 26C -900 ~720 mv Vin Vin max or Vy min; Ta = 75C Output voltage, low Vor -1870 1665 mv Vin @ Vin max or Vip min; Ta = 0C 1850 ~1650 mV Vin = Vin max or Vip min; Ta = 25C 1830 - 1625 mV Vin = Vin max or Vip min; Ta = 75C Output threshold voltage, high Vouc ~1020 mV Vin = Vin min or Vy max; Ta = OC -980 mV Vin = Vig min or yp max; Ty = 25C -920 mV Vin = Vin min or Vie max; Ta = 75C Qutput threshold voltage, low VoLc 1645 mv Vin & Vig min or Vp max; Ta = 0C ~1630 mV Vin = Vig min or Vip max Ta = 25C ~1605 mv Vin = Vin min or Vi_ max; Ta = 76C Input voltage, high Vin -1145 -840 mv For all inputs: Ta = 0C -1105 ~810 mV For all inputs: Ta = 25C -1045 -720 mV For all inputs: Ta = 75C Input voltage, low Vit -1870 -1490 mV For all inputs: Ta = 0C 1850 ~1475 mv For all inputs: Ta = 25C 1830 ~1450 mV For all inputs: Ta = 75C Input current, high hy 220 pA Vin = Ving max Input current, low ie 0.6 170 pA For CS: Vin = Vi_ min -650 pA For all others: Viy = Vi_ min Supply current lEE -260 mA For pPB10480-10: all inputs and outputs open 240 mA For #PB10480-15; all inputs and outputs open Notes: (1) The device under test is mounted in a test socket and measured at a thermal equilibrium established with a transverse air flow maintained at greater than 2.0 m/s.NE C ELECTRONICS INC BLE D MM b4e7525 003953e7? 484 MNECE #PB10480 N: KG AC Characteristics Ta Oto +75C; Vee = -5.2 V 25% pPB10460-10 pPB10480-15 Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions Read Operation Address access time taa 10 15 ns Chip select recovery time tacs 5 8 ns Chip select access time tacs 5 8 ns Write Operation Write pulse width tw 10 18 ns Data setup time twsp 2 3 ns Data hold time twHb 1 2 ns Address setup time twsa 2 3 ns Address hold time tWHA 1 2 ns Chip select setup time twses 2 3 ns Chip select hold time twres 1 2 ns Write disable time tws 5 8 ns Write recovery time twa 1 7 ns Output Risa and Fall Times Output rise time tr 2 2 ns Output fall time tr 2 2 ns Notes: (1) The device under test is mounted in a test socket and measured (2) Input pulse levels -1,7 to -0.9V; input rise and fall times at a thermal equilibrium established with a transverse air flow (measured between 20% and 80% or 80% to 20%) = 2.5 ns; Input maintained at greater than 2.0 mys. and output timing reference level = 50%,N E ELECTRONICS INC NEC b1iE >) b4e7S525 00395328 zPB10480 Figure ft. Loading Conditions Test Circuit Voo (GND) Device Under DO Test RL T CL . ~2.0V 6.01 pF | Notes: | [1] AL =50a, = b {2] CL =30pF. VEE S3H-6036B, Figure 2. Input Pulse -09V 80% 80% 2n% 20% -17V ta te Note: [1] tp=t =2.5ns (typ). S3IH-9435 310 MMNECE pleteNE ELECTRONICS INC BLE D MM 6427525 0035329 257 MNECE PB10480 N KE Cc Timing Waveforms Chip Select Access Cycle cs tacs DO Note: (1) Address is valid more than 2 ns prior to the low transition of CS. {_ + SH-G1645 Address Access Cycle Address 50% TAA Note: [1] CS=ViL B3IH-6144B Write Cycle cs Address x Di fag $$ yp nner twsp p+ I WH WE y f -~tyys 4_ TWHA ~ ~~ |ws CS 'WHCS' BO Pat$ Tyys; jt ! WR: 8314-59508