CLC012AJE-TR13 - National Semiconductor

CLC012

CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery

Literature Number: SNLS032D

CLC012

OBSOLETE

September 21, 2011

Adaptive Cable Equalizer for ITU-T G.703 Data Recovery

General Description

National's CLC012 adaptive cable equalizer is a low-cost

monolithic solution for equalizing data transmitted over cable

(or any media with similar dispersive loss characteristics).

The CLC012 simplifies the task of high-speed data recovery

with a one-chip solution and a minimal number of external

components. The equalizer automatically adapts to equalize

any cable length from zero meters to lengths that attenuate

the signal by 40 dB at 200 MHz. This corresponds to 300 me-

ters of Belden 8281 or 120 meters of Category 5 UTP (un-

shielded twisted pair).

The CLC012 provides superior jitter performance: 180pspp for

270 Mbps data that has passed through 200 meters of Belden

8281 cable. This exceptional performance provides wide er-

ror margin in digital data links. The equalizer operates on a

single supply with a power consumption of only 290 mW. The

small 14-pin SOIC package allows for high-density placement

of components for multi-channel applications such as routers.

The equalizer operates over a wide range of data rates from

less than 50 Mbps to rates in excess of 650 Mbps.

The equalizer is flexible in allowing either single-ended or dif-

ferential input drive. Its high common mode rejection provides

excellent immunity to interference from noise sources. On-

chip quantized feedback eliminates baseline wander.

Additional features include a Loss of Signal output and an

output mute pin which, when tied together, mute the output

when no signal is present. A buffered eye monitor output is

provided, for viewing the equalized signal prior to the com-

parator. Differential AEC pins allow the user to set the internal

adaptive loop time constant with one external capacitor.

Features

■Automatic equalization of coaxial and twisted pair cables

■Loss of Signal detect and output mute

■Output eye monitor

■Single supply operation: +5V or −5.2V

■Single-ended or differential input

■Low cost

Applications

■ITU-T G.703 serial data recovery

■Serial digital data routing and distribution

■Serial digital data equalization and reception

■Data recovery equalization: ATM, CAD networks, medical,

set top terminals, industrial video networks

Key Specifications

■Low jitter: 180pspp @ 270 Mbps through 200 meters of

Belden 8281 coaxial cable

■High data rates: < 50 Mbps to > 650 Mbps

■Excellent input return loss: 19 dB @ 270 MHz

■Low supply current: 68 mA

■Equalizes up to 300+ meters of Belden 8281 or 120 meters

of Cat 5 UTP cable

Typical Application

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CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery

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Connection Diagram

Pinout SOIC

10014501

14-Pin SOIC

Order Number CLC012AJE

See NS Package Number M14A

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CLC012

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC–VEE)−0.3V, +6.5V

Maximum Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering 4 sec.) +260°C

ESD Rating (Note 14)≥500V

θJA 14-Pin SOIC (AJE) 95°C/W

MTTF (based on limited life test

data)

4.8 x 107 hours

Recommended Operating

Conditions

Supply Voltage (VCC–VEE)4.5V to 5.5V

Operating Temperature Range −40°C to +85°C

Series Input Resistance

(In Series w/DI & DI) 100Ω

Input Coupling Capacitance 1.0 μF

AEC Capacitor (Connected

between AEC+ & AEC−) 50 pF to 1 μF

Cable Input Voltage Swing

(Note 4)720 to 880 mVpp

DO/DO Minimum Voltage

(Note 15)VCC–1.6V

Electrical Characteristics

(VCC = +5V, VEE = 0V, signal source swing = 0.8 Vpp(Note 4), CAEC = 100 pF)

Parameter Conditions Typ

+25°C

Min/Max

+25°C

Min/Max

−40°C to

+85°C

Units

DYNAMIC PERFORMANCE

Residual Jitter

10 meters Belden 8281 311 Mbps PRN (Note 5) 150 250 400 pspp

300 meters Belden 8281 311 Mbps PRN (Note 3, Note 5) 350 500 750 pspp

Equalization Time Constant

100 meters Belden 8281 CAEC = 100 pF (Note 6) 1.5 _ _ μs

200 meters Belden 8281 CAEC = 100 pF (Note 6) 2.0 _ _ μs

300 meters Belden 8281 CAEC = 100 pF (Note 6) 3.2 _ _ μs

output rise and fall time (20%–80%) Rcollector = 75Ω 750 _ _ ps

output duty cycle distortion 30 _ _ ps

minimum average transition density 1/50 _ _ trans/ns

maximum average data rate 150m Belden 8281 (Note 7) 650 _ _ Mbps

VCC Jitter Sensitivity

27 MHz 0.85 _ _ ns/V

270 MHz 1.90 _ _ ns/V

VEE Jitter Sensitivity

27 MHz 0.55 _ _ ns/V

270 MHz 1.45 _ _ ns/V

STATIC PERFORMANCE

Supply Current (Includes Output Current)

VAEC = 0V (Note 3) 68 48/75 40/80 mA

VAEC = 0.4V (Note 3) 53 43/64 37/70 mA

Input and Output Parameters

DO/DO output current 10 8.7/11.3 8.0/12 mA

DO/DO output voltage swing Rcollector = 75Ω (Note 3)750 650/850 600/900 mV

DI/DI common mode voltage 3.4 _ _ V

AEC differential voltage Belden 8281 1.5 _ _ mV/meter

AEC+/AEC− common mode 3.6 _ _ V

output eye monitor (OEM) bias potential 3.2 _ _ V

Loss of Signal (LOS) current output-HIGH LOS VOH = 4.5V −400 _ _ μA

Loss of Signal (LOS) current output-LOW LOS VOL = 0.5V 600 _ _ μA

MUTE voltage input-HIGH (Note 3) 1.8 2.0 2.0 V

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CLC012

Parameter Conditions Typ

+25°C

Min/Max

+25°C

Min/Max

−40°C to

+85°C

Units

MUTE voltage input-LOW (Note 3) 1.2 0.8 0.8 V

MUTE current input-HIGH VIH = 5V (Note 3) 5.0 ±100 ±500 nA

MUTE current input-LOW VIL = 0V (Note 3) 0.2 ±100 ±500 nA

TIMING PERFORMANCE

LOS Response Time

carrier applied (Note 8) 150 1000 1000 ns

carrier removed (Note 9) 150 1000 1000 ns

MUTE response time (Note 10) 2.0 _ _ ns

MISCELLANEOUS PERFORMANCE

input resistance single-ended 7.3 _ _ kΩ

input capacitance single-ended (Note 11) 1.0 _ _ pF

input return loss @ 270 MHz Zo = 75Ω (Note 12)19 _ _ dB

maximum cable attenuation 200 MHz (Note 13) 40 _ _ dB

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: J-level: spec. is 100% tested at +25°C.

Note 4: These specifications assume an 800 mVpp signal at the cable input. Levels above and below 800 mV are allowable, but performance may vary. The cable

will attenuate the signal prior to entering the equalizer.

Note 5: Peak-to-peak jitter is defined as 6 times the rms jitter.

Note 6: For more information, see “CLC012 Operation” and “Design Guidelines”.

Note 7: 50% eye opening.

Note 8: Time from application of a valid signal to when the LOS output asserts high.

Note 9: Time from the removal of a valid signal to when the LOS output asserts low.

Note 10: Time from assertion of MUTE to when the output responds.

Note 11: Device only. Does not include typical pc board parasitics.

Note 12: Includes typical pc board parasitics.

Note 13: This sets the maximum cable length for the equalizer.

Note 14: Human body model, 1.5 kΩ in series with 100 pF; based on limited test data.

Note 15: To maintain specified performance, do not reduce DO/DO below this level.

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Typical Performance Characteristics

10014505 10014509

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CLC012

Pin Definitions

Name Pin # Description

DI, DI 8, 9 Differential data inputs.

DO, DO 13, 14 Differential collector data

outputs (ECL compatible).

AEC+,

AEC−

6, 7 AEC loop filter pins.

A capacitor connected between

these pins governs the loop

response for the adaptive

equalization loop.

OEM 3 Eye monitor output. The output

of the equalization filter.

LOS 5 Loss of Signal. (Low when no

signal is present).

MUTE 12 Output MUTE. (Active low.)

Loss of Signal (LOS) may be

tied to this pin to inhibit the

output when no signal is

present.

VCC 1, 2, 4 Positive supply pins (ground or

+5V).

VEE 10, 11 Negative supply pins (−5.2V or

ground).

Operation

The CLC012 Adaptive Cable Equalizer provides a complete

solution for equalizing high-bit-rate digital data transmitted

over long transmission lines. The following sections furnish

design and application information to assist in completing a

successful design:

•Block diagram explanation of the CLC012

•Recommended standard input and output interface

connections

•Common applications for the CLC012

•Measurement, PC layout, and cable emulation boxes

For applications assistance in the U.S., call 800-272-9959 to

contact a technical staff member.

10014520

FIGURE 1. CLC012 Equalizer Application Circuit

BLOCK DESCRIPTION

The CLC012 is an adaptive equalizer that reconstructs serial

digital data received from transmission lines such as coaxial

cable or twisted pair. Its transfer function approximates the

reciprocal of the cable loss characteristic. The block diagram

in Figure 2 depicts the main signal conditioning blocks for

equalizing digital data at the receiving end of a cable. The

CLC012 receives baseband differential or single-ended digi-

tal signals at its inputs DI and DI.

The Equalizer block is a two-stage adaptive filter. This filter

is capable of equalizing cable lengths from zero meters to

lengths that require 40 dB of boost at 200 MHz.

The Quantized Feedback Comparator block receives the

differential signals from the equalizer filter block. This block

includes two comparators. The first comparator incorporates

a self-biasing DC restore circuit. This is followed by a second

high-speed comparator with output mute capability. The sec-

ond comparator receives and slices the DC-restored data. Its

outputs DO and DO are taken from the collectors of the output

transistors. MUTE latches DO and DO when a TTL logic low

level is applied.

The Adaptive Servo Control block produces the signal for

controlling the filter block, and outputs a voltage proportional

to cable length. It receives differential signals from the output

of the filter block and from the quantized-feedback compara-

tor (QFBC) to develop the control signal. The servo loop

response is controlled by an external capacitor placed across

the AEC+ and AEC− pins. Its output voltage, as measured

differentially across AEC+ and AEC−, is roughly proportional

to the length of the transmission line. For Belden 8281 coaxial

cable this differential voltage is about 1.5 mV/meter. Once this

voltage exceeds 500 mV, no additional equalization is pro-

vided.

The Loss of Signal (LOS) block monitors the signal power

out of the equalizing filter and compares it to an internal ref-

erence to determine if a valid signal is present. A CMOS high

output indicates that data is present. The output of LOS can

be connected to the MUTE input to automatically latch the

outputs (DO and DO), preventing random transitions when no

data is present.

The Output Eye Monitor (OEM) provides a single-ended

buffered output for observing the equalized eye pattern. The

OEM output is a low impedance high-speed voltage driver

capable of driving an AC-coupled 100Ω load.

10014521

FIGURE 2. CLC012 Block Diagram

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CLC012

DEVICE TESTING

Performance or compliancy testing of the CLC012 with Cable

Clones is not allowed. Use of these devices is contrary to the

product's specifications and test procedures. Testing for prod-

uct specifications or performance using cable clones is invalid

since cable clones have a different frequency response than

the actual cable. Testing with full length cable samples is rec-

ommended.

Input Interfacing

The CLC012 accepts either differential or single-ended input

voltage specified in Static Performance. The following sec-

tions show several suggestions for interfaces for the inputs

and outputs of the CLC012.

SINGLE-ENDED INPUT INTERFACE: 75Ω Coaxial Cable

The input is connected single-ended to either DI or DI as

shown in Figure 3. Balancing unused inputs helps to lessen

the effects of noise. Use the equivalent termination of 37.4Ω

to balance the input impedance seen by each pin. It also helps

to terminate grounds at a common point. Resistors Rx and

R y are recommended for optimum performance. The equal-

izer inputs are self-biasing. Signals should be AC coupled to

the inputs as shown in Figure 3.

10014522

FIGURE 3. Single-Ended 75Ω Cable Input Interface

DIFFERENTIAL INPUT INTERFACE: Twisted Pair

A recommended differential input interface is shown in Figure

4. Proper voltage levels must be furnished to the input pins

and the proper cable terminating impedance must be provid-

ed. For Category 5 UTP this is approximately 100Ω. Figure

4 shows a generalized network which may be used to receive

data over a twisted pair. Resistors R1 and R2 provide the

proper terminating impedance and signal level adjustment.

The blocking capacitors provide AC coupling of the attenuat-

ed signal levels. The plots in the Typical Performance Char-

acteristics section demonstrate various equalized data rates

using Category 5 UTP at 100 meter lengths. A full schematic

of a recommended driver and receiver circuit for 100Ω Cate-

gory 5 UTP is provided in the Typical Applications section

with further explanation.

10014524

FIGURE 4. Twisted Pair Input Interface

Output Interfacing

The outputs DO and DO produce ECL logic levels when the

recommended output termination networks are used. The DO

and DO pins are not complementary emitter coupled log-

ic outputs. Instead, the outputs are taken off of the collectors

of the transistors. Therefore, care must be taken to meet the

interface threshold levels required by ECL families. Recom-

mended interfaces for standard ECL families are shown in the

following circuits.

DIFFERENTIAL LOAD-TERMINATED OUTPUT

INTERFACE

Figure 5 shows a recommended circuit for implementing a

differential output that is terminated at the load. A diode or

75Ω resistor provides a voltage drop from the positive supply

(+5V for PECL or Ground for ECL operation) to establish

proper ECL levels. The resistors terminate the cable to the

characteristic impedance. The output voltage swing is deter-

mined by the CLC012 output current (10 mA) times the ter-

mination resistor. For the circuit in Figure 5, the nominal

output voltage swing is 750 mV.

10014525

FIGURE 5. Differential Load Terminated

Output Interface

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CLC012

DIFFERENTIAL SOURCE-TERMINATED OUTPUT

INTERFACE

Figure 6 is similar to Figure 5 except that the termination is

provided at the source. This configuration may also be used

for single-ended applications. However, the unused output

must still be terminated as shown.

10014526

FIGURE 6. Differential Source Terminated

Output Interface

TERMINATING PHYSICALLY SEPARATED OUTPUTS

When the two outputs must be routed to physically separate

locations, the circuit in Figure 6 may be applied. Alternatively,

if load termination is desired, the circuit in Figure 7 may be

used. The resistive divider network provides 75Ω termination

and establishes proper ECL levels. This circuit consumes

slightly more power than the previous circuits.

10014527

FIGURE 7. Alternative Load Terminated

Output Interface

Design Guidelines

SELECTING THE AUTOMATIC EQUALIZER CAPACITOR

The AEC capacitor sets the loop time constant τ for the

equalizer's adaptive loop response time. The following for-

mula is used to set the loop time constant:

τ = R • CAEC • 10 −6

R is a conversion factor that is set by internal equalizer pa-

rameters and cable length. For Belden 8281 coaxial cable,

the R values are (τ = μs, CAEC in pF):

Cable

Length

R Value

(Ohms)

100 meters 15000

200 meters 20000

300 meters 32000

For example, a CAEC value of 100 pF results in an adaptive

loop time constant of 2 μs at 200 meters of cable.

CONNECTION AND OPERATION OF LOS AND MUTE

Loss of Signal (LOS) is a CMOS output that indicates the

presence of equalized data from the filter. This LOS output

can be connected to MUTE to suspend changes in the data

outputs DO and DO, if no valid signal exists. This simple con-

figuration prevents random output transitions due to noise.

For sparse transition patterns it is recommended that a ca-

pacitor be connected to LOS as shown in Figure 1.

Add a capacitor to pin 5 to slow the response time of Loss of

Signal when LOS is connected to MUTE. The capacitor re-

duces sensitivity to pathological patterns. Pathological pat-

terns are defined as sparse data sequences with few

transitions.

OUTPUT EYE MONITOR OEM CONNECTIONS

The OEM is a high-speed, buffered output for monitoring the

equalized eye pattern prior to the output comparator. Its out-

put is designed to drive an AC-coupled 50Ω coaxial cable with

a series 50Ω backmatch resistor. The cable should be termi-

nated with 50Ω at the oscilloscope. Figure 1 shows a

schematic with a typical connection.

MINIMUM DATA TRANSITIONS

The CLC012 specifies a minimum transition rate. For the

CLC012 this sets the minimum data rate for transmitting data

through any cable medium. The CLC012 minimum average

transition density is found in the Electrical Characteristics

section of the datasheet.

POWER SUPPLY OPERATION AND THERMAL

CONSIDERATIONS

The CLC012 operates from either +5V or −5.2V single sup-

plies. Refer to Figure 1 when operating the part from +5V.

When operating with a −5.2V supply, the VEE pins should be

bypassed to ground. The evaluation board and associated

literature provide for operation from either supply.

Maximum power dissipation occurs at minimum cable length.

Under that condition, ICC = 58 mA.

Total power dissipated:

PT = (58 mA)(5V) = 290 mW

Power in the load:

PL = (0.7V)(11 mA) + (37.5)(11 mA)2 = 12 mW

Maximum power dissipated on the die:

PDMAX = PT–PL = 278 mW

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CLC012

Junction Temperature =

(θJA)(278 mW) + TA = T A + 26°C

Layout and Measurement

The printed circuit board layout for the CLC012 requires prop-

er high-speed layout to achieve the performance specifica-

tions found in the datasheet. The following list contains a few

rules to follow:

1. Use a ground plane.

2. Decouple power pins with 0.1 μF capacitors placed

≤ 0.1” (3mm) from the power pins.

3. Design transmission strip lines from the CLC012's input

and output pins to the board connectors.

4. Route outputs away from inputs.

5. Keep ground plane ≥ 0.025” (0.06mm) away from the

input and output pads.

Figure 8 shows a block level measurement diagram, while

Figure 15 on depicts a detailed schematic. A pseudo-random

pattern generator with low output jitter was used to provide a

NRZI pattern to create the eye diagrams shown in the Typical

Performance Characteristics section.

Since most pattern generators have a 50Ω output impedance,

a translation can be accomplished using a CLC005 Cable

Driver as an impedance transformer. A wide bandwidth os-

cilloscope is needed to observe the high data rate eye pattern.

When monitoring a single output that is terminated at both the

equalizer output and the oscilloscope, the effective output

load is 37.4Ω. Consequently, the signal swing is half that ob-

served for a single-ended 75Ω termination.

10014528

FIGURE 8. Typical Measurement Block

Troubleshooting with scope probes can affect the equaliza-

tion. For high data rates, use a low capacitance probe with

less than 2 pF probe capacitance. Evaluation boards and lit-

erature are available for quick prototyping and evaluation of

the CLC012 Adaptive Cable Equalizer. The CLC012 contains

CMOS devices and operators should use grounding straps

when handling the parts.

Figure 9 shows the CLC012's internal power supply routing.

Bypass VCC (pin 4) by:

•Monolithic capacitor of about 0.1 μF placed less than

0.1” (3mm) from the pin

•Tantalum capacitor of about 6.8 μF for large current signal

swings placed as close as convenient to the CLC012

10014529

FIGURE 9. Power Package Routing Fixture

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CLC012

To minimize ringing at the CLC012's inputs, place a 100Ω

resistor in series with the input. This resistor reduces induc-

tance effects.

Several layout techniques can improve high speed perfor-

mance:

•Keep input, output and AEC traces well separated

•Use balanced input termination's

•Avoid routing traces close to the CLC012's input trace

•Maintain common return points for components

•Use guard traces

The input lines of the CLC012 use a 100Ω series resistors at

the input pins. This decreases the inductive effects internal to

the part to reduce ringing on fast rise and fall times. Refer to

the evaluation board layout for further suggestions on layout

for the CLC012 Adaptive Equalizer.

EQUALIZATION CURVE

The CLC012 Adaptive Cable Equalizer has a maximum

equalization response as shown in Figure 10. This response

may be obtained by forcing >0.5V differentially at the AEC

pins.

10014530

FIGURE 10. Maximum Equalization Response

CABLE EMULATION BOXES

Some cable emulation boxes will not mimic cables correctly.

When evaluating the CLC012, it is strongly recommended

that actual cable be used to determine the various perfor-

mance parameters.

Typical Applications

COAXIAL CABLE RECEIVER (Page 1)

The CLC012 equalizer application shown on page 1 will

equalize a variety of coaxial cables up to lengths that attenu-

ate the signal by 40 dB at 200 MHz. The application shows

the proper connection for a single cable driven with a CLC005

driver. Loss of Signal (LOS) is connected to MUTE to latch

outputs DO and DO in the absence of an input signal to the

equalizer.

Refer to the CLC012's evaluation board layout for additional

suggestions.

National can supply most of the major components required

to design a transmission line repeater. Figure 11 shows a

typical repeater design using the CLC005, CLC012, and the

CLC016. The design functions supported by each chip are:

CLC005: Cable connection chip

Boosts drive for transmission to next repeater or

final destinations

CLC012: Receive serialized digital data from incoming

transmission lines

Equalizes the incoming data

CLC016: Retimes the equalized data (improving jitter)

The CLC016 is a multi-rate data retiming PLL. The circuit

(Figure 11) will work at up to 4 different data rates with no

additional components or manual tuning.

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CLC012

10014531

FIGURE 11. Typical Repeater Design

DIGITAL VIDEO (SDV) ROUTERS

The CLC012 provides performance that complies with the

ITU-T G.703 standard for serial digital data transmission over

coaxial cable. One common application is in routers, which

provide a switching matrix for connecting source equipment

to destination equipment.

Figure 12 shows a typical configuration for a router, including

equalizers, a crosspoint switch, data retimers, and cable

drivers. The CLC012 is used in its standard configuration in

this application, and automatically equalizes cable lengths

from zero meters to greater than 300 meters at 360 MHz (see

plots in Typical Performance Characteristics section). The

equalized outputs are connected to the differential inputs of

the crosspoint switch. The CLC016 Data Retimer receives the

data from the crosspoint and performs the clock and data re-

covery functions, further reducing jitter. Finally, the retimed

data is driven into the coaxial cable by a CLC005 ITU-T G.

703 Cable Driver (with two amplitude-adjustable outputs).

10014532

FIGURE 12. Data Routing Block Diagram

TWISTED PAIR DRIVER

A low-cost medium for transmitting data is twisted pair. Cat-

egory 5 UTP has an attenuation characteristic similar to

Belden 8281 coaxial cable but scaled in length: 120 meters

of Category 5 UTP is roughly equivalent to 300 meters of

Belden 8281 cable. When properly implemented, the CLC012

will equalize data rates up to 625 Mbps over Category 5 UTP.

The maximum data rate depends upon the cable length. A

plot of Maximum Data Rate vs Cable Length is found in the

Typical Performance Characteristics section for Belden

8281, and can be scaled as stated above to estimate maxi-

mum cable lengths and data rates for UTP.

Category 5 UTP has a characteristic impedance of approxi-

mately 100Ω. The CLC005 in Figure 13 is used to drive the

twisted pair AC-coupled with a series 0.1 μF capacitor and a

50Ω resistor in each differential output. The CLC012 Adaptive

Equalizer requires 800 mVpp from the transmit side of the ca-

ble. A voltage divider is necessary to scale the voltage to the

required level at the input of the CLC012. This resistor net-

work also provides the correct impedance match for twisted

pair.

For Category 5 UTP, the approximate AEC voltage per length

is 3.75 mV/m (see Block Description). The CLC005 pro-

vides a trim adjust for fine tuning the output signal with the

resistor R. Refer to the CLC005 datasheet for tuning direc-

tions.

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CLC012

10014533

FIGURE 13. Twisted Pair Equalization

10014534

FIGURE 14. Before and After Equalization at 622 Mbps Through 50 Meters of Category 5 UTP

10014535

FIGURE 15. Typical Measurement Setup

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CLC012

Evaluation Board

Evaluation boards are available for a nominal charge that

demonstrate the basic operation of the SDI/SDV/SDH de-

vices. The evaluation boards can be ordered through

National's Distributors. Supplies are limited, please check for

current availability.

The SD012EVK evaluation kit for the CLC012, Adaptive Ca-

ble Equalizer for ITU-T G.703 Data Recovery, provides an

operating environment in which the cable equalizer can be

evaluated by system / hardware designers. The evaluation

board has all the needed circuitry and connectors for easy

connection and checkout of the device circuit options as dis-

cussed in the CLC012 datasheet. A schematic, parts list and

pictorial drawing are provided with the board.

From the WWW, the following information may be viewed /

downloaded for most evaluation boards: www.national.com/

appinfo/interface

•Device Datasheet and / or EVK User Manual

•View a picture of the EVK

•View the EVK Schematic

•View the top assembly drawing and BOM

•View the bottom assembly drawing and BOM

PCB LAYOUT

The CLC012 requires proper high-speed layout techniques to

obtain best results. A few recommended layout rules to follow

for best results when using the CLC012 Adaptive Cable

Equalizer are:

1. Use a ground plane.

2. Decouple power pins with 0.01 μF capacitors placed

≤ 0.1” (3mm) from the power pins.

3. Design transmission lines to the inputs and outputs.

4. Route outputs away from inputs.

5. Remove ground plane ≥ 0.025” (0.06mm) from the input

and output pads.

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CLC012

Physical Dimensions inches (millimeters) unless otherwise noted

14-Pin SOIC

Order Number CLC012AJE

NS Package Number M14A

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Notes

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CLC012

Notes

CLC012 Adaptive Cable Equalizer for ITU-T G.703 Data Recovery

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