SLVS443 – DECEMBER 2002
FEATURES
DTwo-Input, One-Output Power Multiplexer
With Low rDS(on) Switches:
– 84 mΩ Typ (TPS2111)
– 120 mΩ Typ (TPS2110)
DReverse and Cross-Conduction Blocking
DWide Operating Voltage Range . . . .2.8 V to
5.5 V
DLow Standby Current . . . . 0.5-µA Typ
DLow Operating Current . . . . 55-µA Typ
DAdjustable Current Limit
DControlled Output Voltage Transition Times,
Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance
DCMOS and TTL Compatible Control Inputs
DManual and Auto-Switching Operating Modes
DThermal Shutdown
DAvailable in a TSSOP-8 Package
APPLICATIONS
DPCs
DPDAs
DDigital Cameras
DModems
DCell phones
DDigital Radios
DMP3 Players
1
2
3
4
8
7
6
5
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
PW PACKAGE
(TOP VIEW)
DESCRIPTION
The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a battery and
a wall adapter, each operating at 2.8–5.5 V and delivering up to 1 A. The TPS211x family includes extensive protection
circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply
transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power
multiplexer applications.
TYPICAL APPLICATION
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2110/1 C1
0.1 µF
C2
0.1 µF
CLRL
IN1: 2.8 – 5.5 V
IN2: 2.8 – 5.5 V
RILIM
EN1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
SLVS443 – DECEMBER 2002
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE TPS2110 TPS2111 TPS2112 TPS2113 TPS2114 TPS2115
Current Limit Adjustment Range 0.31–0.75A 0.63–1.25A 0.31–0.75A 0.63–1.25A 0.31–0.75A 0.63–1.25A
Switching modes
Manual Yes Yes No No Yes Yes
Switching modes Automatic Yes Yes Yes Yes Yes Yes
Switch Status Output No No Yes Yes Yes Yes
Package TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8
ORDERING INFORMATION
TAPACKAGE ORDERING NUMBER(1) MARKINGS
40°Cto85°C
TSSOP 8 (PW)
TPS2110PW 2110
–40°C to 85°CTSSOP-8 (PW) TPS2111PW 2111
(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS21 10PWR) to indicate tape and reel.
PACKAGE DISSIPATION RATINGS
PACKAGE DERATING FACTOR ABOVE
TA = 25°CTA ≤ 25°C
POWER RATING TA = 70°C
POWER RATING TA = 85°C
POWER RATING
TSSOP-8 (PW) 3.87 mW/°C386.84 mW 212.76 mW 154.73 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS2110, TPS2111
Input voltage range at pins IN1, IN2, D0, D1, VSNS, ILIM(2) –0.3 V to 6 V
Output voltage range, VO(OUT)(2) –0.3 V to 6 V
Continuous out
p
ut current IO
TPS2110 0.9 A
Continuous output current, IOTPS2111 1.5 A
Continuous total power dissipation See Dissipation Rating Table
Operating virtual junction temperature range, TJ–40°C to 125°C
Storage temperature range, Tstg –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Inputvoltage at IN1 V
VI(IN2) ≥ 2.8 V 1.5 5.5
V
Input voltage at IN1, VI(IN1) VI(IN2) < 2.8 V 2.8 5.5 V
Input voltage at IN2 V
VI(IN1) ≥ 2.8 V 1.5 5.5
V
Input voltage at IN2, VI(IN2) VI(IN1) < 2.8 V 2.8 5.5 V
Input voltage, VI(DO), VI(D1), VI(VSNS) 0 5.5 V
C t li it dj t t I
TPS2110 0.31 0.75
A
Current limit adjustment range, IO(OUT) TPS2111 0.63 1.25 A
Operating virtual junction temperature, TJ–40 125 °C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN MAX UNIT
Human body model 2 kV
CDM 500 V
SLVS443 – DECEMBER 2002
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3
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS2110 TPS2111
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
POWER SWITCH
T25°C
VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110
Di
TJ = 25°C,
IL= 500 mA
VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 mΩ
rDS( )(1)
Drain-source
on state resistance
I
L =
500
m
A
VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110
mΩ
rDS(on)
(1)
on-state resistance
(INx
–
OUT)
T 125°C
VI(IN1) = VI(IN2) = 5.0 V 220 150
(INx
–
OUT)
TJ = 125°C,
IL= 500 mA
VI(IN1) = VI(IN2) = 3.3 V 220 150 mΩ
I
L =
500
m
A
VI(IN1) = VI(IN2) = 2.8 V 220 150
(1) The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case,
the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS (D0 AND D1)
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.7 V
In
p
ut current at D0 or D1
D0 or D1 = High, sink current 1
µA
Input current at D0 or D1 D0 or D1 = Low, source current 0.5 1.4 5 µA
SUPPLY AND LEAKAGE CURRENTS
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A 55 90
Suppl
y
current from IN1 D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 1 12
µA
Su ly
current
from
IN1
(operating) D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A 75 µA
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 1
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A 1
Suppl
y
current from IN2 D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 75
µA
Su ly
current
from
IN2
(operating) D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2)= 3.3 V,
IO(OUT) = 0 A 1 12 µA
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 55 90
Quiescent current from IN1 D0 = D1 = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A 0.5 2
µA
Quiescent
current
from
IN1
(STANDBY) D0 = D1 = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 1µA
Quiescent current from IN2 D0 = D1 = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A 1
µA
Quiescent
current
from
IN2
(STANDBY) D0 = D1 = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A 0.5 2 µA
Forward leakage current from IN1
(measured from OUT to GND) D0 = D1 = High (inactive), VI(IN1) = 5.5 V, IN2 open,
VO(OUT) = 0 V (shorted), TJ = 25°C0.1 5 µA
Forward leakage current from IN2
(measured from OUT to GND) D0 =D1= High (inactive), VI(IN2) = 5.5 V, IN1 open,
VO(OUT) = 0 V (shorted), TJ = 25°C0.1 5 µA
Reverse leakage current to INx
(measured from INx to GND) D0 = D1 = High (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C 0.3 5 µA
SLVS443 – DECEMBER 2002
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4
ELECTRICAL CHARACTERISTICS Continued
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT CIRCUIT
TPS2110
RILIM = 400 Ω0.51 0.63 0.80
Current limit accuracy
TPS2110 RILIM = 700 Ω0.30 0.36 0.50
A
Current limit accuracy
TPS2111
RILIM = 400 Ω0.95 1.25 1.56 A
TPS2111 RILIM = 700 Ω0.47 0.71 0.99
tdCurrent limit settling time(1) Time for short–circuit output current to
settle within 10% of its steady state value. 1 ms
Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 0 µA
(1) Not tested in production.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSNS COMPARATOR
VSNS threshold voltage
VI(VSNS) ↑0.78 0.8 0.82
V
VSNS threshold voltage VI(VSNS) ↓0.735 0.755 0.775 V
VSNS comparator hysteresis(1) 30 60 mV
Deglitch of VSNS comparator (both ↑↓)(1) 90 150 220 µs
Input current 0 V ≤ VI(VSNS) ≤ 5.5 V –1 1 µA
UVLO
IN1 and IN2 UVLO
Falling edge 1.15 1.25
V
IN1 and IN2 UVLO Rising edge 1.30 1.35 V
IN1 and IN2 UVLO hysteresis(1) 30 57 65 mV
Internal V UVLO (the higher of IN1 and IN2)
Falling edge 2.4 2.53
V
Internal VDD UVLO (the higher of IN1 and IN2) Rising edge 2.58 2.8 V
Internal VDD UVLO hysteresis(1) 30 50 75 mV
UVLO deglitch for IN1, IN2(1) Falling edge 110 µs
(1) Not tested in production.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REVERSE CONDUCTION BLOCKING
∆VO(I_block) Minimum output-to-input voltage
difference to block switching
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5 V
supply through a series 1-kΩ resistor. Let D0 = low.
Slowly decrease the supply voltage until OUT connects
to IN1.
80 100 120 mV
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
Thermal shutdown threshold(1) TPS211x is in current limit. 135
Recovery from thermal shutdown(1) TPS211x is in current limit. 125 °C
Hysteresis(1) 10
C
IN2–IN1 COMPARATORS
Hysteresis of IN2–IN1 comparator 0.1 0.2 V
Deglitch of IN2–IN1 comparator, (both ↑↓)(1) 90 150 220 µs
(1) Not tested in production.
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SWITCHING CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS2110 TPS2111
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
POWER SWITCH
trOutput rise time from
an enable(1) VI(IN1) = VI(IN2) = 5 V TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a) 0.5 1.0 1.5 1 1.8 3 ms
tfOutput fall time from
a disable(1) VI(IN1) = VI(IN2) = 5 V TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a) 0.35 0.5 0.7 0.5 1 2 ms
tt
Transition time(1)
IN1 to IN2 transition,
VI(IN1) = 3.3 V,
VI(IN2) = 5 V
TJ = 125°C, CL = 10 µF,
IL = 500 mA
[Measure transition time
as 10 90% rise time or
40 60 40 60
µs
ttT ransition time
(1)
IN2 to IN1 transition,
VI(IN1) = 5 V,
VI(IN2) = 3.3 V
as 10–90% rise time or
from 3.4 V to 4.8 V on
VO(OUT)],
See Figure 1(b) 40 60 40 60
µs
tPLH1 Turn-on propagation
delay from enable(1) VI(IN1) = VI(IN2) = 5 V
Measured from enable to
10% of VO(OUT)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a) 0.5 1 ms
tPHL1 Turn-off propagation
delay from a
disable(1)
VI(IN1) = VI(IN2) = 5 V,
Measured from disable
to 90% of VO(OUT)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a) 3 5 ms
tPLH2 Switch-over rising
propagation delay(1)
Logic 1 to Logic 0
transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(D0) = 0 V,
Measured from D1 to
10% of VO(OUT)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c) 0.17 1 0.17 1 ms
tPHL2 Switch-over falling
propagation delay(1)
Logic 0 to Logic 1
transition on D1,
VI(IN1) = 1.5V,
VI(IN2) = 5V,
VI(D0) = 0 V,
Measured from D1 to
90% of VO(OUT)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c) 2 3 10 2 5 10 ms
(1) Not tested in production.
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TRUTH TABLE
D1 D0 VI(VSNS) > 0.8V VI(IN2) > VI(IN1) OUT(1)
0 0 X X IN2
0 1 YES X IN1
0 1 NO NO IN1
0 1 NO YES IN2
1 0 X X IN1
1 1 X X Hi-Z
(1)The under-voltage lockout circuit causes the output to go Hi-Z if the
selected power supply does not exceed the IN1/IN2 UVLO, or if neither
of the supplies exceeds the internal VDD UVLO.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
D0 1 I TTL and CMOS compatible input pins. Each pin has a 1-µA pull-up. The truth table shown above illustrates the
D1 2 I
µ
functionality of D0 and D1.
GND 5 I Ground
IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at
least one supply exceeds the internal VDD UVLO.
IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and
at least one supply exceeds the internal VDD UVLO.
ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2110 and TPS2111,
respectively.
OUT 7 O Power switch output
VSNS 3 I In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if the VSNS voltage is greater
than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The truth table shown above illustrates the
functionality of VSNS.
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FUNCTIONAL BLOCK DIAGRAM
Control
Logic
_
+VI(VSNS) >0.8 V
D1
D0
UVLO (IN1)
UVLO (IN2)
UVLO (VDD)
Q2 is ON Q1 is ON
_
+
_
++
0.6 V
EN2 EN1
Cross-Conduction
Detector
_
+
Q2
Q1
Charge
Pump
0.5 V
TPS2110: k = 0.2%
TPS2111: k = 0.1%
k ×IO(OUT)
_
+
VO(OUT) > VI(INx) +
100 mV
_
+
IO(OUT)
Vf = 0 V
EN1
IN2
IN1
7
4
OUT
ILIM
Internal VDD
Vf = 0 V
VDD
ULVO
Thermal
Sense
1 µA
IN2
ULVO
1 µA
IN1
ULVO
0.8 V
8
6
1
2
3
5
IN1
IN2
D0
D1
VSNS
GND
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PARAMETER MEASUREMENT INFORMATION
0 V 10%
90%
Switch Enabled
Switch Off Switch Off
90%
10%
3.3 V
5 V
Switch #1 Enabled Switch #2 Enabled
4.8 V
3.4 V
DO–D1
1.5 V 1.85 V
4.65 V
Switch #2 EnabledSwitch #1 Enabled Switch #1 Enabled
5 V
trtf
tPLH1 tPHL1
VO(OUT)
tt
VO(OUT)
VO(OUT)
DO–D1 tPLH2 tPHL2
(a)
(b)
(c)
DO–D1
Figure 1. Propagation Delays and Transition Timing Waveforms
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TYPICAL CHARACTERISTICS
Figure 2
VI(DO)
VI(D1)
VO(OUT)
t – Time – 1 ms/div
2V/Div
2V/Div
2V/Div
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2111PW 0.1 µF
0.1 µF
50 Ω
5 V
3.3 V
400 Ω
f = 28 Hz
78% Duty Cycle
1
µF
Output Switchover Response Test Circuit
OUTPUT SWITCHOVER RESPONSE
t – Time – 2 ms/div
Figure 3
VI(DO)
VI(D1)
VO(OUT)
2V/Div
2V/Div
2V/Div
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2111PW 0.1 µF
0.1 µF
50 Ω
5 V
3.3 V
400 Ω
f = 28 Hz
78% Duty Cycle
1
µF
OUTPUT TURN-ON RESPONSE
Output Turn-On Response Test Circuit
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10
TYPICAL CHARACTERISTICS
Figure 4
CL = 1 µF
CL = 0 µF
t – T ime – 40 µs/div
VI(DO)
VI(D1)
VO(OUT)
2V/Div
2V/Div
2V/Div
Output Switchover Voltage Droop Test Circuit
OUTPUT SWITCHOVER VOLTAGE DROOP
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2111PW 0.1 µF
0.1 µF
50 Ω
400 Ω
f = 580 Hz
90% Duty Cycle
5 V
CL
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TYPICAL CHARACTERISTICS
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.1 1 10 100
RL = 10 Ω
RL = 50 Ω
VI = 5 V
– Output Voltage Droop – V
CL – Load Capacitance – µF
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2111PW 0.1 µF
0.1 µF
VI
400 Ω
0.1 µF1 µF10 µF47 µF100 µF50 Ω10 Ω
Figure 5
f = 28 Hz
50% Duty Cycle
Output Switchover Voltage Droop Test Circuit
O(OUT)
∆V
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TYPICAL CHARACTERISTICS
0
50
100
150
200
250
300
0 20406080100
VI = 5 V
VI = 3.3 V
Inrush Current – mA
CL – Load Capacitance – µF
INRUSH CURRENT
vs
LOAD CAPACITANCE
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2111PW 0.1 µF
0.1 µF
VI
400 Ω
0.1 µF47 µF10 µF
50 Ω
To Oscilloscope
1 µF100 µF
Figure 6
f = 28 Hz
90% Duty Cycle
Output Capacitor Inrush Current Test Circuit
II–
NC
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TYPICAL CHARACTERISTICS
Figure 7
–50 0 50 100 150
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
60
80
100
120
140
160
180
TPS2110
TPS2111
– Switch On-Resistance – mΩ
rDS(on)
Figure 8
23456
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
VI(INx) – Supply Voltage – V
80
85
90
95
100
105
110
115
120
TPS2110
TPS2111
– Switch On-Resistance – mΩ
rDS(on)
Figure 9
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
23456
I(IN1)
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
Aµ
VI(IN1)– IN1 Supply Voltage – V
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
I– IN1 Supply Current –
Figure 10
40
42
44
46
48
50
52
54
56
58
60
23456
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VI(IN1) – Supply Voltage – V
I(IN1)– IN1 Supply Current –Aµ
IN1 Switch is ON
VI(IN2) = 0 V,
IO(OUT) = 0 A
I
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14
TYPICAL CHARACTERISTICS
Figure 11
0
0.2
0.4
0.6
0.8
1
1.2
–50 0 50 100 150
II(IN1) = 5.5 V
II(IN2) = 3.3 V
Device Disabled
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
I(INx) Supply Current – –Aµ
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I
Figure 12
0
10
20
30
40
50
60
70
80
–50 0 50 100 150
II(IN1)
II(IN2)
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
IN1 Switch is ON
VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I(INx) Supply Current – –Aµ
I
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15
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 13
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified threshold. Once
the voltage on IN1 falls below this threshold, the TPS2110/1 will select the higher of the two supplies. This
usually means that the TPS2110/1 will swap to IN2.
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2110/1 C1
0.1 µF
C2
0.1 µF
CLRL
IN1: 2.8 – 5.5 V
IN2: 2.8 – 5.5 V
R1
R2
RILIM
NC
Figure 13. Auto-Selecting for a Dual Power Supply Application
In Figure 14, the multiplexer selects between two power supplies based upon the EN1 logic signal. OUT
connects to IN1 if EN1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are
compatible with both TTL and CMOS logic.
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2110/1 C1
0.1 µF
C2
0.1 µF
CLRL
IN1: 2.8 – 5.5 V
IN2: 2.8 – 5.5 V
RILIM
EN1
Figure 14. Manually Switching Power Sources
SLVS443 – DECEMBER 2002
www.ti.com
16
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to
IN1 if VI(VSNS) is greater than 0.8 V, otherwise OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75–7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow
back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x
will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.
Once a supply has been connected to the output, it will remain connected regardless of output voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/ RILIM and 500/RILIM for the TPS2110 and
TPS2111, respectively. S etting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2110/1 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). ). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot plugging a load like a PCI card. The TPS2110/1 slews the output voltage
at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage
droop and reduces the output voltage hold-up capacitance requirement.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2110PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2110PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2111PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2110PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2111PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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