ICS840024AGILFT - Integrated Device Technology

DATA SHEET

FemtoClock® Crystal/LVCMOS-to-

LVCMOS/LVTTL Frequency Synthesizer

ICS840024I

VDDA

nPLL_SEL

TEST_CLK

nXTAL_SEL

VDD

GND

VDDO

GND

XTAL_IN

XTAL_OUT

General Description

The ICS840024I is a four output LVCMOS/LVTTL Synthesizer

optimized to generate Ethernet reference clock frequency. The

ICS840024I uses IDT’s 3RD generation low phase noise VCO

technology and can achieve 1ps or lower typical random RMS phase

jitter, easily meeting Ethernet jitter requirements. The ICS840024I is

packaged in a small 20-pin TSSOP package.

Features

•Four LVCMOS / LVTTL outputs, 17Ω output impedance

•Selectable crystal oscillator interface or LVCMOS / LVTTL

single-ended clock input

•Supports the following output frequency: 125MHz

•RMS phase jitter @125MHz (1.875MHz - 20MHz):

0.604ps (typical)

•Power supply modes:

Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

•-40°C to 85°C ambient operating temperature

•Available in lead-free (RoHS 6) package

Phase

Detector

VCO

M = ÷25 (fixed)

N = ÷5

OSC

nPLL_SEL

nXTAL_SEL

XTAL_IN

XTAL_OUT

TEST_CLK

Pullup

Pulldown

25MHz

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm

package body

G Package

Top View

Pin Assignment

Block Diagram

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2, 9, 20 nc Unused No connect pins.

3 nXTAL_SEL Input Pulldown PLL reference select control input. See Table 3A.

LVCMOS/LVTTL interface levels.

4 TEST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.

5 OE Input Pullup Output enable control pin. See Table 3B. LVCMOS/LVTTL interface levels.

6 MR Input Pulldown Master reset control pin. See Table 3C. LVCMOS/LVTTL interface levels.

7 nPLL_SEL Input Pulldown PLL bypass control input. See Table 3D. LVCMOS/LVTTL interface levels.

DDA Power Analog supply pin.

10 VDD Power Core supply pin.

11, 12 XTAL_OUT,

XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

13, 19 GND Power Power supply ground.

14, 15, 17, 18 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 17Ω output impedance.

LVCMOS/LVTTL interface levels.

16 VDDO Power Output supply pin.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

CPD

Power Dissipation Capacitance

(per output) 8pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ROUT Output Impedance VDDO = 3.3V ± 5% 17 Ω

VDDO = 2.5V ± 5% 21 Ω

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Function Tables

Table 3A. nXTAL_SEL PLL Reference Select Function Table

Table 3B. Output Enable Function Table

Table 3C. Master Reset Function Table

Table 3D. PLL Bypass Function Table

nXTAL_SEL PLL Reference Input

0 (default) XTAL Interface

1 TEST_CLK

OE Output Operation

0 Q[0:3] are disabled in high-impedance state.

1 (default) Q[0:3] are enabled.

MR Reset Operation

0 (default) Normal operation, internal dividers are enabled.

1 Internal dividers are reset, Q[0:3] are disabled in logic low state.

nPLL_SEL PLL Operation

0 (default) PLL is enabled

1 PLL is bypassed. The output frequency is equal to the selected reference frequency divided by the output divider of 5.

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5% , TA = -40°C to 85°C

Table 4B. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C

Table 4C. Power Supply DC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI

XTAL_IN

Other Inputs

0V to VDD

-0.5V to VDD + 0.5V

Outputs, VO-0.5V to VDDO + 0.5V

Package Thermal Impedance, θJA 86.7°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage VDD – 0.12 3.3 VDD V

VDDO Output Supply Voltage 3.135 3.3 3.465 V

IDD Core Supply Current 90 mA

IDDA Analog Supply Current 12 mA

IDDO Output Supply Current 8mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage VDD – 0.12 3.3 VDD V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Core Supply Current 90 mA

IDDA Analog Supply Current 12 mA

IDDO Output Supply Current 8mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 2.375 2.5 2.625 V

VDDA Analog Supply Voltage VDD – 0.12 2.5 VDD V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Core Supply Current 90 mA

IDDA Analog Supply Current 12 mA

IDDO Output Supply Current 8mA

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Table 4D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C

Table 5. Crystal Characteristics

NOTE: Characterized using an 18pF parallel resonant crystal.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage VDD = 3.465V 2 VDD + 0.3 V

VDD = 2.625V 1.7 VDD + 0.3 V

VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V

VDD = 2.625V -0.3 0.7 V

IIH

Input

High Current

OE VDD = VIN = 3.465V or 2.625V 5 µA

TEST_CLK, MR,

nXTAL_SEL, nPLL_SEL VDD = VIN = 3.465V or 2.625V 150 µA

IIL

Input

Low Current

OE VDD = 3.465V or 2.625V,

VIN = 0V -150 µA

TEST_CLK, MR,

nXTAL_SEL, nPLL_SEL

VDD = 3.465V or 2.625V,

VIN = 0V -5 µA

VOH Output High Voltage VDDO = 3.3V ± 5%; IOH = -12mA 2.6 V

VDDO = 2.5V ± 5%; IOH = -12mA 1.8 V

VOL Output Low Voltage VDDO = 3.3V ± 5% or 2.5V ± 5%;

IOL = 12mA 0.5 V

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 25 MHz

Equivalent Series Resistance (ESR) 50 Ω

Shunt Capacitance 7pF

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

AC Electrical Characteristics

Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Refer to phase noise plots.

Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Refer to phase noise plots.

Table 6C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Refer to phase noise plots.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 125 MHz

tsk(o) Output Skew; NOTE 1, 2 20 60 ps

tjit(Ø) RMS Phase Jitter (Random); NOTE 3 125MHz, Integration Range:

1.875MHz – 20MHz 0.604 ps

tLOCK PLL Lock Time 50 100 ms

tR / tFOutput Rise/Fall Time 20% to 80% 250 400 750 ps

odc Output Duty Cycle 42 50 58 %

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 125 MHz

tsk(o) Output Skew; NOTE 1, 2 20 60 ps

tjit(Ø) RMS Phase Jitter (Random); NOTE 3 125MHz, Integration Range:

1.875MHz – 20MHz 0.546 ps

tLOCK PLL Lock Time 50 100 ms

tR / tFOutput Rise/Fall Time 20% to 80% 250 400 750 ps

odc Output Duty Cycle 46 50 54 %

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 125 MHz

tsk(o) Output Skew; NOTE 1, 2 20 60 ps

tjit(Ø) RMS Phase Jitter (Random); NOTE 3 125MHz, Integration Range:

1.875MHz – 20MHz 0.544 ps

tLOCK PLL Lock Time 50 100 ms

tR / tFOutput Rise/Fall Time 20% to 80% 250 400 750 ps

odc Output Duty Cycle 42 50 58 %

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Typical Phase Noise at 125MHz (3.3V/3.3V)

Typical Phase Noise at 125MHz (3.3V/2.5V)

Offset Frequency (Hz)

Noise Power dBc

Offset Frequency (Hz)

Noise Power dBc

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Typical Phase Noise at 125MHz (2.5V/2.5V)

Offset Frequency (Hz)

Noise Power dBc

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Parameter Measurement Information

3.3V Core/3.3V LVCMOS Output Load AC Test Circuit

2.5V Core/2.5V LVCMOS Output Load AC Test Circuit

Output Skew

3.3V Core/2.5V LVCMOS Output Load AC Test Circuit

RMS Phase Jitter

Output Duty Cycle/Pulse Width/Period

SCOPE

GND

VDD,

1.65V±5%

-1.65V±5%

VDDO

1.65V±5%

VDDA

SCOPE

GND

VDD,

1.25V±5%

-1.25V±5%

VDDO

1.25V±5%

VDDA

tsk(o)

DDO

SCOPE

GND

VDD

1.25V±5%

-1.25V±5%

VDDO

2.05V±5%

VDDA

2.05V±5%

Offset Frequency

f1f2

Phase Noise Plot

Area Under Curve Defined by the Offset Frequency Markers

RMS Phase Jitter =

Noise Power

2 * * ƒ

Q[0:3]

tPERIOD

PERIOD

odc =

DDO

x 100%

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Parameter Measurement Information, continued

Output Rise/Fall Time

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

TEST_CLK Input

For applications not requiring the use of the test clock, it can be left

floating. Though not required, but for additional protection, a 1kΩ

resistor can be tied from the TEST_CLK to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

Outputs:

LVCMOS Outputs

All unused LVCMOS outputs can be left floating. There should be no

trace attached.

20%

80% 80%

20%

Q[0:3]

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by

one side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 1A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50Ω applications,

R1 and R2 can be 100Ω. This can also be accomplished by removing

R1 and changing R2 to 50Ω. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 1B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L _ O U T

XTA L _ I N

Zo = 50 ohms C2

.1uf

LVPECL Driver

Zo = 50 ohms

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Schematic Layout

Figure 2 shows an example of ICS840024I application schematic. In

this example, the device is operated at VDD = VDDO = 3.3V. An 18pF

parallel resonant 25MHz crystal is used. The load capacitance C1 =

22pF and C2 = 22pF are recommended for frequency accuracy.

Depending on the parasitics of the printed circuit board layout, these

values might require a slight adjustment to optimize the frequency

accuracy. Crystals with other load capacitance specifications can be

used. This will required adjusting C1 and C2.

As with any high speed analog circuitry, the power supply pins are

vulnerable to noise. To achieve optimum jitter performance, power

supply isolation is required. The ICS840024I provides separate

power supplies to isolate from coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1uF capacitor in each power pin filter should be placed on the

device side of the PCB and the other components can be placed on

the opposite side.

Figure 2. ICS840024I Application Schematic

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supply frequencies, it is recommended that component values

be adjusted and if required, additional filtering be added. Additionally,

good general design practices for power plane voltage stability

suggests adding bulk capacitances in the local area of all devices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure the logic control inputs are properly

set.

VDD

VDDO

100

Optional Termination

22 pF

RU1

RU 2

No t I n st al l

Zo = 50 Ohm

VDDO

RD1

Not Install

10 u

BLM18 BB221SN1

Fe r r i t e Bea d

1 2

nPLL_ SEL

28 MHz

VDD

100

nXTAL_ SEL

VDDA

VDD

22pF

Set Logic

Input to

'1'

XTAL_OUT

VDD= VDDO= 3.3V

VDDO

XTA L _ I N

Zo = 50 Ohm

3. 3 V

10u F

BLM18 BB221SN2

Fe r r i t e Bea d

1 2

LVCMOS

VDD

C10

10u F

TEST_CLK Q1

0. 1u

To Logic

Input

pins

R2 10

To Logic

Input

pins

Unused output can be left floating. There should

no trace attached to unused output. Device

characterized with all outputs terminated.

0. 1 uF

Set Logic

Input to

'0'

RD 2

0. 1u

3. 3 V

10 11

nXTAL_SEL

TEST _CL K

nPL L_SEL

VDDA

VDD XTAL_OUT

XTA L _ I N

GN D

VDDO

GN D

VDD

0. 1 u

LVCMOS

18pF

Logic Control Input Examples

0. 1 uF

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS840024I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS840024I is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)MAX = VDD_MAX * (IDD + IDDA + IDDO) = 3.465V *(90mA + 12mA + 8mA) = 381.15mW

Dynamic Power Dissipation at 125MHz

Power (125MHz) = CPD * Frequency * (VDD)2 = 8pF * 125MHz * (3.465V)2 = 12mW per output

Total Power (125MHz) = 12mW * 4 = 48mW

Total Power Dissipation

•Total Power

= Power (core)MAX + Power (125MHz)

= 381.15mW + 48mW

= 429.15mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 86.7°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.429W *86.7°C/W = 122.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

θJA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Reliability Information

Table 8. θJA vs. Air Flow Table for a 20 Lead TSSOP

Transistor Count

The transistor count for ICS40024I is: 3093

Package Outline and Package Dimensions

Package Outline - G Suffix for 20 Lead TSSOP Table 9. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N20

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D6.40 6.60

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Ordering Information

Table 10. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

840024BGILF ICS840024BIL “Lead-Free” 20 Lead TSSOP Tube -40°C to 85°C

840024BGILFT ICS840024BIL “Lead-Free” 20 Lead TSSOP Tape & Reel -40°C to 85°C

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Revision History Sheet

Rev Table Page Description of Change Date

B1 Block Diagram - corrected nXTAL_SEL to select XTAL when LOW (0) and select

TEST_CLK when HIGH (1). 8/30/2012

ICS840024I Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signif-

icantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.

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