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PRELIMINARY DATA
February 2005
This is preliminary information on a new product now in devel opment or unde rgoing ev aluation. Details are subject to change witho ut no tic e.
M25P64
64 Mbit, Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
FEATURES SUMMARY
■64Mbit of Flash Memory
■Page Program (up to 256 Bytes) in 1.4ms
(typical)
■Sector Erase (512Kbit)
■Bulk Erase (64Mbit)
■2.7 to 3.6V Single Supply Voltage
■SPI Bus Compa tib le Se rial Interf ace
■50MHz Clock Rate (m ax im um)
■Electronic Signatures
– JEDEC Standard Two-Byte Signature
(2017h)
– RES Instruction, One-Byte, Signature
(16h), for backward compatibility
■More than 100000 Erase/Program Cycles per
Sector
■More than 20-Year Data Retention
Figure 1. Packages
VDFPN8 (ME)
8x6mm (MLP8)
SO16 (MF)
300 mils width
M25P64
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M25P64
Figure 10.Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 16
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 17
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 20
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence 21
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Electronic Signature (RES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 19.Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence . . . . . 25
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 21.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 32
Figure 24.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M25P64
4/38
Figure 25.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 34
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27.SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35
Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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M25P64
SUMMARY D ESCRIPTION
The M25P64 is a 64Mbit (8M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, ac cesse d by a high s peed SPI-co mpatib le
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 128 sectors, each
containing 256 pages. Each page is 256 bytes
wide. Th us, the whol e memory ca n be viewe d as
consisting of 32768 pages, or 8388608 bytes.
The whol e memory can be eras ed using th e Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 2. Logic Diagram
Table 1. Signal Names
Figure 3. VDFPN Connections
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connec ted to any ot her voltage
or signal li ne on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
Figure 4. SO Connections
Note: 1. DU = Don’t Use
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
C Serial Clock
D Serial Data Input
Q Serial Data Output
SChip Select
W Write Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
AI07485
S
VCC
M25P64
HOLD
VSS
W
Q
C
D
1
AI08595
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P64
1
AI07486b
2
3
4
16
15
14
13
DU
DU DU
DU
VCC
HOLD
DUDU
M25P64
5
6
7
8
12
11
10
9WQ VSS
DU
DU
S
D
C
M25P64
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SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This i npu t sig nal is us ed t o
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clo ck (C) .
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at hi gh impedance. Unl ess an interna l Pro-
gram, Erase or Write Status Register cycle is in
progress , th e dev ice wi ll be i n the S tand by P owe r
mode . D riv in g Chip Se le ct (S ) Lo w se le cts t h e de-
vice, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial c ommunicatio ns with the dev ice
without deselecting the device.
During the Ho ld condition, the S erial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driv en Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).
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M25P64
SPI MODES
These de vices can be dr iven by a m icroco ntroller
with its SPI per ipheral run ning in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M25P64
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OPERATING FEATURES
Page Programming
To program one data byte, two instructions are re-
quired: Write Enable (WREN), w hich is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
internal Program cycle (of duration tPP).
To spread this ove rhead, the Pa ge Progr am (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of me mory need to h ave been er ased to all
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration tSE or tBE).
The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write S tatus
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) bit is provided in the Status Regis-
ter so that the applic ati on progr am can mo nit or its
value, polling it to establish when the previous
Write cy cle, Pr og ra m cy cle or Eras e cycl e is com -
plete.
Active Power and Standby Power Modes
When Chip Select (S) is Low, the de vi ce is se le c t-
ed, and in the Active Power mode.
When Chip Sel ec t ( S) is High, the d ev ice i s de se -
lected, but could remain in the Active Power mode
until all inte rnal cy cles have comp leted (Prog ram,
Erase, Write Status Register). The device then
goes in to the Standby Power mode. The device
consumption drops to ICC1.
Status Register
The Status Register contains a number of status
and contro l bi ts that c an be r ead o r set (as app ro -
priate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the de vice to b e put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0)
become read-only bits.
9/38
M25P64
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help comba t this, the M25P64 features
the following data protection mechanisms:
■Power On Reset and an internal timer (tPUW)
can provide protection against inadvertant
changes while the power supply is outside the
operati ng sp eci fi ca tio n.
■Program, Erase and Write Status Register
instr ucti ons ar e check ed th at they cons ist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
■All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction
completion
– Write Status Register (WRSR) instruction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
■The Bl o ck Pr ot e ct (BP 2 , B P1 , B P0) bi t s al lo w
part of the memory to be configured as read-
only. This is the Software Protected Mode
(SPM).
■The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
Mode (HPM) .
Table 2. Protected Area Sizes
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Status Register
Content Memory Content
BP2
Bit BP1
Bit BP0
Bit Protected Area Unprotected Area
0 0 0 none All secto rs1 (128 sectors: 0 to 127)
0 0 1 Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125)
0 1 0 Upper 32nd (4 sectors: 124 to 127) Lower 31/32nds (124 sectors: 0 to 123)
0 1 1 Upper sixteenth (8 sectors: 120 to 127) Lower 15/16ths (120 sectors: 0 to 119)
1 0 0 Upper eighth (16 sectors: 112 to 127) Lower seven-eighths (112 sectors: 0 to 111)
1 0 1 Upper quarter (32 sectors: 96 to 127) Lower three-quarters (96 sectors: 0 to 95)
1 1 0 Upper half (64 sectors: 64 to 127) Lower half (64 sectors: 0 to 63)
1 1 1 All sectors (128 sectors: 0 to 127) none
M25P64
10/38
Hold Condition
The Hol d ( HO LD) sign al is us ed to pau se any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register , Progr am or Eras e cyc le tha t is currentl y
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Seri al Cloc k (C) b eing Lo w (as s hown i n Fig-
ure 7.).
The Hold cond ition e nds on the risin g edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) be ing Low, th e Hold conditio n starts af -
ter Serial Clock (C) next goes Low. Similarly, if the
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in Figure
7.).
During the Ho ld condition, the S erial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Selec t (S) goe s High wh ile the de vic e is in
the Hold con dition, this ha s the effect of re setting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, a nd then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
Figure 7. Hold Condition Activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
11/38
M25P64
MEMORY ORGANIZATION
The memory is organized as:
■8388608 bytes (8 bits each)
■128 sectors (512Kbits, 65536 bytes each)
■32768 pages (256 bytes each).
Each page can be individually programmed (bits
are program med from 1 to 0). The device is Sector
or Bulk Erasable (bits a re erased from 0 to 1 ) but
not Page Erasab le.
Figure 8. Block Diagram
AI08520
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
7FFFFFh
000FFh
M25P64
12/38
Table 3. Memory Organization
Sector Address Range
127 7F0000h 7FFFFFh
126 7E0000h 7EFFFFh
125 7D0000h 7DFFFFh
124 7C0000h 7CFFFFh
123 7B0000h 7BFFFFh
122 7A0000h 7AFFFFh
121 790000h 79FFFFh
120 780000h 78FFFFh
119 770000h 77FFFFh
118 760000h 76FFFFh
117 750000h 75FFFFh
116 740000h 74FFFFh
115 730000h 73FFFFh
114 720000h 72FFFFh
113 710000h 71FFFFh
112 700000h 70FFFFh
111 6F0000h 6FFFFFh
110 6E0000h 6EFFFFh
109 6D0000h 6DFFFFh
108 6C0000h 6CFFFFh
107 6B0000h 6BFFFFh
106 6A0000h 6AFFFFh
105 690000h 69FFFFh
104 680000h 68FFFFh
103 670000h 67FFFFh
102 660000h 66FFFFh
101 650000h 65FFFFh
100 640000h 64FFFFh
99 630000h 63FFFFh
98 620000h 62FFFFh
97 610000h 61FFFFh
96 600000h 60FFFFh
95 5F0000h 5FFFFFh
94 5E0000h 5EFFFFh
93 5D0000h 5DFFFFh
92 5C0000h 5CFFFFh
91 5B0000h 5BFFFFh
90 5A0000h 5AFFFFh
89 590000h 59FFFFh
88 580000h 58FFFFh
87 570000h 57FFFFh
86 560000h 56FFFFh
85 550000h 55FFFFh
84 540000h 54FFFFh
83 530000h 53FFFFh
82 520000h 52FFFFh
81 510000h 51FFFFh
80 500000h 50FFFFh
79 4F0000h 4FFFFFh
78 4E0000h 4EFFFFh
77 4D0000h 4DFFFFh
76 4C0000h 4CFFFFh
75 4B0000h 4BFFFFh
74 4A0000h 4AFFFFh
73 490000h 49FFFFh
72 480000h 48FFFFh
71 470000h 47FFFFh
70 460000h 46FFFFh
69 450000h 45FFFFh
68 440000h 44FFFFh
67 430000h 43FFFFh
66 420000h 42FFFFh
65 410000h 41FFFFh
64 400000h 40FFFFh
63 3F0000h 3FFFFFh
62 3E0000h 3EFFFFh
61 3D0000h 3DFFFFh
60 3C0000h 3CFFFFh
59 3B0000h 3BFFFFh
58 3A0000h 3AFFFFh
57 390000h 39FFFFh
Sector Address Range
13/38
M25P64
56 380000h 38FFFFh
55 370000h 37FFFFh
54 360000h 36FFFFh
53 350000h 35FFFFh
52 340000h 34FFFFh
51 330000h 33FFFFh
50 320000h 32FFFFh
49 310000h 31FFFFh
48 300000h 30FFFFh
47 2F0000h 2FFFFFh
46 2E0000h 2EFFFFh
45 2D0000h 2DFFFFh
44 2C0000h 2CFFFFh
43 2B0000h 2BFFFFh
42 2A0000h 2AFFFFh
41 290000h 29FFFFh
40 280000h 28FFFFh
39 270000h 27FFFFh
38 260000h 26FFFFh
37 250000h 25FFFFh
36 240000h 24FFFFh
35 230000h 23FFFFh
34 220000h 22FFFFh
33 210000h 21FFFFh
32 200000h 20FFFFh
31 1F0000h 1FFFFFh
30 1E0000h 1EFFFFh
29 1D0000h 1DFFFFh
28 1C0000h 1CFFFFh
27 1B0000h 1BFFFFh
26 1A0000h 1AFFFFh
25 190000h 19FFFFh
24 180000h 18FFFFh
23 170000h 17FFFFh
22 160000h 16FFFFh
21 150000h 15FFFFh
Sector Address Range
20 140000h 14FFFFh
19 130000h 13FFFFh
18 120000h 12FFFFh
17 110000h 11FFFFh
16 100000h 10FFFFh
15 0F0000h 0FFFFFh
14 0E0000h 0EFFFFh
13 0D0000h 0DFFFFh
12 0C0000h 0CFFFFh
11 0B0000h 0BFFFFh
10 0A0000h 0AFFFFh
9 090000h 09FFFFh
8 080000h 08FFFFh
7 070000h 07FFFFh
6 060000h 06FFFFh
5 050000h 05FFFFh
4 040000h 04FFFFh
3 030000h 03FFFFh
2 020000h 02FFFFh
1 010000h 01FFFFh
0 000000h 00FFFFh
Sector Address Range
M25P64
14/38
INSTRUCTIONS
All instr uctions , addresses and data are shifte d in
and out of the device, most significant bit first.
Serial D ata Input (D) is s ample d on the fi rst ri sing
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4..
Every in structio n sequenc e starts with a o ne-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR), Read Identification
(RDID) or Read Electronic Signature (RES) in-
struction, the shifted-in instruction sequence is fol-
lowed by a data-out sequence. Chip Select (S) can
be driven High after any bit of the data-out se-
quence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN) or Write Disable
(WRDI), Chip Select (S) must be driven High ex-
actly at a byte bou nda ry, othe r wis e the in str uc tio n
is rejecte d, an d is not ex ecuted . That is, Chip Se -
lect (S) must driven High when the number of
clock pulses after Chip Select (S) being driven
Low is an exact multiple of eight.
All attempt s to access th e memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WR SR Write Status Regis ter 0000 000 1 0 1h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
RES Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞
15/38
M25P64
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 9.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 10.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
Figure 10. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P64
16/38
Read Identification (RDID)
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first byte (20h), and the memory capacity of the
device in the second byte (17h).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
The devi ce is first sel ected by driv ing Chip Se lect
(S) Low. Then, the 8-bit instruction code for the in-
struction is shifted in. This is followed by the 24-bit
device identification , stored in the memory, being
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 11..
The Read Identification (RDID) instruction is termi-
nated by dr iving Chip Sel ect (S) High at any time
during data output.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Table 5. Read Identification (RDID) Data-Out Sequence
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Manufacturer Identification Device Ide nt ific at ion
Memory Type Memory Capacity
20h 20h 17h
C
D
S
21 3456789101112131415
Instruction
0
AI06809b
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 17 18 28 29 30 31
17/38
M25P64
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is reco mmende d to check the Write In P rogr ess
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 12..
Table 6. Status Register Format
The statu s and c ontrol bits of the S tatus Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register , Program or Erase cycle . When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 t he interna l Wr ite Ena ble Latc h
is reset and no Wr ite Sta tus Regi ster , Program or
Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) in-
struction. When one o r more of th e Block Pr otect
(BP2, BP1, BP0) bits is set to 1, the relevant mem-
ory area (as defined in Table 2 .) becomes protect-
ed agains t Page Pr ogram (PP) and Secto r Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hard-
ware Protec ted mode has not been set. The B ulk
Erase (BE) instruction is executed if, and only if, all
Block Protect (BP2, BP1, BP0) bits are 0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the de vice to b e put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Writ e Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP2, BP1,
BP0) beco me read-only bits and the Write Statu s
Register (WRSR) instruction is no longer accepted
for execution.
Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M25P64
18/38
Write Statu s Register (WRSR)
The Write Status Reg ister (WRSR ) instructi on al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been de coded and executed , the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 13. .
The Write Status Register (WRSR) instruction has
no effect on b6 , b5, b1 and b0 of th e Status Reg -
ister. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (W RSR) instruc tion
is not executed. As soon as Chip Select (S) is dr iv-
en H igh, t he se lf-tim ed Wri te St atus Regist er cycl e
(whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of
the area th at is to be tr eated as re ad-only, as de-
fined in Table 2.. The Write Status Register
(WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD)
bit in accordance with the Write Protect (W) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Reg is ter ( W RS R) in str uct ion is no t e xe cut -
ed once the Hardware Protected Mode (HPM) is
entered.
Table 7. Protection Modes
Note: 1. As defined by the values in th e Block Protect (B P2, BP1, BP0) bits of the Status Register, as shown in Table 2..
The prote ction featu res of the devi ce are summa -
rized in T ab le 7.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possi bl e to wri te to the S tatu s Re gi ste r
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whethe r Write Prote ct
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be cons idered, de pending on the sta te of
Write Protect (W):
– If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
– If Write Protect (W) is driven Low, it is
not
possible to write to the Status Register
even
if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register,
are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
W
Signal SRWD
Bit Mode Write Protecti on of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
S tatus Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against Page
Progra m, Se cto r Era se
and Bulk Erase
Ready to accept Page
Progr am and S ector E rase
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardwa re wri te pro tec te d
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be chan ge d
Protected against Page
Progra m, Se cto r Era se
and Bulk Erase
Ready to accept Page
Progr am and S ector E rase
instructions
19/38
M25P64
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
– or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.
Figure 13. Write Status Register (WRSR) Instruction Sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P64
20/38
Read Data Bytes (READ)
The devi ce is first sel ected by driv ing Chip Se lect
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Out put (Q ), each bi t being shifte d out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 14. .
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be conti nued i ndefinitely.
The Read Data By tes (RE AD ) in struc ti on is term i-
nat ed by dri ving Ch ip Se le ct ( S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
Note: 1. Address bit A23 is Don’t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
21/38
M25P64
Read Data Bytes at Higher Speed
(FAST_READ)
The devi ce is first sel ected by driv ing Chip Se lect
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit be ing latched-in during the
rising edge of S erial Cloc k (C). The n the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, du ring the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 15. .
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any tim e du ring d ata o utput. Any Re ad
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an E rase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence
Note: Address bit A23 is Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
M25P64
22/38
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). B efo re i t c an be a cc ep ted, a W rite E nab le
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, th e device sets the W rite En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current page are programmed from the start
address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero).
Chip Se lect (S) m ust be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16. .
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
rectly wi thi n th e sam e page . If less than 25 6 D ata
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chi p Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 2. and Table 3.) is not execut-
ed.
Figure 16. Page Program (PP) Instruction Sequence
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
23/38
M25P64
Sector Erase (SE)
The Sect or Erase ( SE) ins truction s ets to 1 (FFh)
all bits inside the ch osen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction c ode, and th ree addres s bytes on S erial
Data Input (D). Any address inside the Sector (see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 17. .
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Er ase cy-
cle is in progress, the Status Register may be read
to check the v alue of the Write In P rogress (WIP )
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sector Erase (SE) instruc tion a pplie d to a pa ge
which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 2. and Table 3.) is not execut-
ed.
Figure 17. Sector Erase (SE) Instruction Sequence
Note: Address bit A23 is Don’t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P64
24/38
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, th e device sets the W rite En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 18. .
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip S elect (S) is dr iven High,
the self-timed Bulk Erase cycle (whose duration is
tBE) is initiated. While the Bulk Erase cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At som e un specifi ed ti me bef ore the cyc le
is compl eted, the Write E nable Latc h (WEL) bit i s
reset.
The Bulk Erase (BE) instruction is executed only if
all Bloc k Protect (BP2 , BP1, BP0) b its are 0. The
Bulk Erase (BE) instruction is ignored if one, or
more, sectors are protected.
Figure 18. Bulk Erase (BE) Instruction Sequence
C
D
AI03752D
S
21 345670
Instruction
25/38
M25P64
Read Electronic Signature (RES)
The instruction is used to read, on Serial Data Out-
put (Q), the old-style 8-bit Electronic Signature,
whose value for the
M25P64
is
16h
.
Please note that this is not the same as, or even a
subset of, the JEDEC 16-bit Electronic Signature
that is rea d by the Read Identi fier (RDID) ins truc-
tio n. Th e ol d- st yl e E le ct r on ic Signat ur e is sup p or t-
ed for reasons of backward compatibility, only, and
should not be used for new designs. New designs
should, instead, make use of the JEDEC 16-bit
Electronic Signature, and the Read Identifier
(RDID) instruction.
The dev ice is first s elected by dr iving Chi p Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the old-style 8-bit Electronic Sig-
nature, stored in the memory, is shifted out on Se-
rial Data Output (Q), each bit being shifted out
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 19.
The Read Electronic Signature (RES) instruction
is termi nat ed b y d ri ving Chip Sele ct ( S ) H igh after
the Electronic Signature has been read at least
once. Sending additional clock cycles on Serial
Clock (C), while Chip Select (S) is driven Low,
cause the Electronic Signature to be output re-
peatedly.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Drivi ng Ch ip Sele ct (S ) High after the 8-bit inst ruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time, still ensures that
the devic e is pu t in to S tan dby Po wer mo de. Onc e
in the Standby Power mode, the device waits to be
selected, so that it can receive, decode and exe-
cute instructions.
Figure 19. Read Electronic Signature (RES) Instruction Sequence an d Data-Out Sequence
Note: The value of the 8-b i t Electronic Signature, for t he M25P64, is 16h.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
MSB
M25P64
26/38
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on VCC) until VCC re aches the
correct value:
–V
CC(min) at Power-up, and then for a further
delay of tVSL
–V
SS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure sa fe and proper Po wer-up
and Power-d own.
To avoid data corruption and inadvertent write op-
erations during Power-up, a Power On Reset
(POR) ci rcuit is incl uded. The log ic inside th e de-
vice is held reset while VCC is less than the Power
On Reset (P OR) t hre shold volt age, VWI – all oper-
ations are disabled, and the device does not re-
spond to any instr uc ti on.
Moreover, the device ignores all Write Enable
(WREN), Page Pr ogram (P P), Secto r Erase (SE) ,
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of tPUW has
elapsed after the moment that VCC rises above the
VWI threshold. However, the correct operation of
the device is not guaranteed if, by this time, VCC is
still below VCC(min). No Write Status Register,
Program or Erase instructions should be sent until
the later of:
–t
PUW after VCC passed the VWI threshold
–t
VSL after VCC passed the VCC(min) level
These values are specified in Table 8..
If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
At Power-up, the device is in the following state:
– The device is in the Standby Power mode
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Each de-
vice in a system should have the VCC rail decou-
pled b y a suita ble capaci tor close t o the packa ge
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operat-
ing volta ge, to below the Power On Reset (POR)
threshold voltage, VWI, all operations are disabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 20. Power-up Timing
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
27/38
M25P64
Table 8. Power-Up Timing and VWI Threshold
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status
Register bits are 0).
Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to S low 30 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit Voltage 1.5 2.5 V
M25P64
28/38
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 9. may cause permanent damage to the de-
vice. Th ese are s tress r atings only, and oper ation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect de vice r eliability . Refer al so to
the STM icroelec tronics SURE P rogram and other
relevant quality documents.
Table 9. Absolute Maximum Ratings
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Rest rictions on Hazard ous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A 114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Tem p era tur e –65 150 °C
TLEAD Lead Temperature during Soldering See note (1) °C
VIO Input and Output Voltage (with respect to Ground) –0.5 4.0 V
VCC Supply Voltage –0.2 4.0 V
VESD Elect ros tatic Dis ch arg e Voltage (Human Body mode l) 2–2000 2000 V
29/38
M25P64
DC AND AC PARA METERS
This section summarizes th e operating and mea-
suremen t cond itions, and the D C and A C ch arac -
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. De si gne rs s ho uld c heck tha t th e op er ati ng
conditio ns in their circ uit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 10. Operating Conditions
Table 11. AC Measurement Conditions
Note: Output Hi-Z is defined as t he point where data out i s no lo nger driven.
Figure 21. AC Measurement I/O Waveform
Table 12. Capacitance
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Temperature –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
Symbol Parameter Test Condition Min.Max.Unit
COUT Outp ut Ca pa cita nc e (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
M25P64
30/38
Table 13. DC Characteristics
Symbol Parameter Test Co nd itio n
(in addition to those in Table 10.)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA
ICC3 Operating Current (READ)
C=0.1V
CC / 0.9.VCC at 50MHz,
Q = open 8mA
C=0.1V
CC / 0.9.VCC at 20MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 20 mA
ICC6 Operating Current (SE) S = VCC 20 mA
ICC7 Operating Current (BE) S = VCC 20 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.2 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µAV
CC–0.2 V
31/38
M25P64
Table 14. AC Characteristics
Note: 1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guar anteed by characterization, not 100% tested i n pr oduction.
3. Expressed as a slew-rate.
4. Only applic able as a constraint for a WRSR instruction when SRWD is set at 1.
Test conditions specified in Table 10. and Table 11.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions: FAST_READ,
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH (1) tCLH Clock High Time 9 ns
tCL (1) tCLL Clock Low Time 9 ns
tCLCH (2) Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL (2) Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S De sel ec t Time 100 ns
tSHQZ (2) tDIS Outp ut Dis ab le Time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Outp ut Ho ld Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX (2) tLZ HOLD to Output Low-Z 8 ns
tHLQZ (2) tHZ HOLD to Output High-Z 8 ns
tWHSL (4) Write Protect Setup Time 20 ns
tSHWL (4) Write Protect Hold Time 100 ns
tWWrite Status Regis ter Cycle Time 5 15 m s
tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time 1 3 s
tBE Bulk Erase Cycle Time 68 160 s
M25P64
32/38
Figure 22. Serial Input Timing
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
33/38
M25P64
Figure 24. Hold Timing
Figure 25. Output Timing
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
Q
AI01449e
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25P64
34/38
PACKAGE MECHANICAL
Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline
Note: Drawing is not to scale.
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 8.00 0.3150
D2 6.40 0.2520
ddd 0.05 0.0020
E 6.00 0.2362
E2 4.80 0.1890
e 1.27 – – 0.0500 – –
K0.20 0.0079
L 0.50 0.45 0.60 0.0197 0.0177 0.0236
L1 0.15 0.0059
N8 8
D
E
VDFPN-02
A
e
E2
D2
L
b
L1
A1 ddd
35/38
M25P64
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
Note: Drawing is not to scale.
Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
Symbol millimeters inches
Typ Min Max Typ Min Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e 1.27 – – 0.050 – –
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
θ0° 8° 0° 8°
ddd 0.10 0.004
E
16
D
C
H
18
9
SO-H
LA1
A
ddd
A2
θ
Be
h x 45˚
M25P64
36/38
PART NUMBERING
Table 17. Ordering Information Scheme
For a list of available options (speed, package,
etc.) or for further information on any aspect of this device, please c ontact yo ur neare st ST Sa les Of-
fice.
Example: M25P64 – V MF 6 T P
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
64 = 64Mbit (8M x 8)
Operatin g Voltage
V = VCC = 2.7 to 3.6V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Pa ck ing
T = Tape and Reel Packing
Plating Technology
blank = Standard Sn Pb plati ng
P or G = RoHS compliant
37/38
M25P64
REVISION HISTORY
Table 18. Document Revision History
Date Rev. Descrip tio n of Re vis io n
28-Apr-2003 0.1 Target Specification Document written in brief form
15-May-2003 0.2 Target Specification Document written in full
20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003 0.4 tPP, tSE and tBE revise d
02-Sep-2003 0.5 Voltage supply range changed
19-Sep-2003 0.6 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added
17-Dec-2003 0.7 Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package removed.
15-Nov-2004 1.0 Document status promoted from Target Specification to Preliminary Data. 8x6 MLP8 package
added. Minor wording changes.
24-Feb-2005 2.0
Deep Power-Down mode removed from datasheet (Figure 19., Read Electr onic Signature
(RES) Instruction Sequence and Data-Out Sequence modified and tRES1 and tRES2
removed from Table 14., AC Characteristics). SO16 Wide package specifications updated.
End timing line of tSHQZ mo dif ied in Figure 25., Output Timing. Figures moved below the
corresponding instructions in the INSTRUCTIONS section.
M25P64
38/38
Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences
of use of such informat ion nor for any inf ringement of pate nts or other rights of third parties whic h may result from it s use. No licens e is granted
by implication or other wise under any patent or pat ent rights of ST Microelectronics. Specificati ons mentioned i n this publication are subject
to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e not
authorize d for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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