1
FEATURES DESCRIPTION
µ
µ
UC1825A-SP
www.ti.com
..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
RAD-TOLERANT CLASS-V, HIGH-SPEED PWM CONTROLLER
•QML-V Qualified, SMD 5962-87681
The UC1825A PWM controller is an improved versionof the standard UC1825 family. Performance•Rad-Tolerant: 30 kRad (Si) TID
(1)
enhancements have been made to several of the•Compatible With Voltage-Mode or
circuit blocks. Error amplifier gain bandwidth productCurrent-Mode Control Methods
is 12 MHz, while input offset voltage is 2 mV. Current•Practical Operation at Switching Frequencies
limit threshold is assured to a tolerance of 5%.to 1 MHz
Oscillator discharge current is specified at 10 mA foraccurate dead time control. Frequency accuracy is•50-ns Propagation Delay to Output
improved to 6%. Startup supply current, typically 100•High-Current Dual Totem Pole Outputs
µA, is ideal for off-line applications. The output drivers(2-A Peak)
are redesigned to actively sink current during UVLO•Trimmed Oscillator Discharge Current
at no expense to the startup current specification. Inaddition each output is capable of 2-A peak currents•Low 100- µA Startup Current
during transitions.•Pulse-by-Pulse Current Limiting Comparator
xxx•Latched Overcurrent Comparator With FullCycle Restart
xxx
(1) Radiation tolerance is a typical value based upon initial devicequalification with dose rate = 10 mrad/sec. Radiation LotAcceptance Testing is available - contact factory for details.
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
J PACKAGE
(TOP VIEW)
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 .....................................................................................................................................................
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This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Functional improvements have also been implemented in this family. The UC1825 shutdown comparator is nowa high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch thatensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputsare in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge toinsure that the fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin hasbecome CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment andhas been buffered for easier interfacing.
The UC1825A has dual alternating outputs and the same pin configuration of the UC1825. Aversion parts haveUVLO thresholds identical to the original UC1825.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
– 55 ° C to 125 ° C CDIP-16 5962-8768105VEA UC1825AJ-SP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
THERMAL INFORMATION
PACKAGE θ
JA
θ
JC
J-16 80-120 28
(1)
(1) θJC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, " The baseline values shown are worst case (mean+ 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device diesize greater than 14400 square mils use the following values; dual-in-line, 11 ° C/W; flat pack, 10 ° C/W; pin grid array, 10 ° C/W " .
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ABSOLUTE MAXIMUM RATINGS
UC1825A-SP
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..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
CLK/LEB 4 O Output of the internal oscillatorTiming capacitor connection pin for oscillator frequency programming. The timing capacitor should beCT 6 I
connected to the device ground using minimal trace length.EAOUT 3 O Output of the error amplifier for compensationGND 10 Analog ground return pinILIM 9 I Input to the current limit comparatorINV 1 I Inverting input to the error amplifierNI 2 I Non-inverting input to the error amplifierOUTA 11 O High current totem pole output A of the on-chip drive stage.OUTB 14 O High current totem pole output B of the on-chip drive stage.PGND 12 Ground return pin for the output driver stageNon-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation,RAMP 7 I this serves as the input voltage feed-forward function by using the CT ramp. In peak current modeoperation, this serves as the slope compensation input.RT 5 I Timing resistor connection pin for oscillator frequency programmingSS 8 I Soft-start input pin which also doubles as the maximum duty cycle clamp.Power supply pin for the output stage. This pin should be bypassed with a 0.1- µF monolithic ceramicVC 13
low ESL capacitor with minimal trace lengths.Power supply pin for the device. This pin should be bypassed with a 0.1- µF monolithic ceramic low ESLVCC 15
capacitor with minimal trace lengths5.1-V reference. For stability, the reference should be bypassed with a 0.1- µF monolithic ceramic lowVREF 16 O
ESL capacitor and minimal trace length to the ground plane.
over operating free-air temperature range unless otherwise noted
(1)
VALUE UNIT
V
IN
Supply voltage, VC, VCC 22 VI
O
Source or sink current,DC OUTA, OUTB 0.5 AI
O
Source or sink current, pulse (0.5 µs) OUTA, OUTB 2.2 AINV, NI, RAMP – 0.3 to 7 VAnalog inputs
ILIM, SS – 0.3 to 6 VPower ground PGND ± 0.2 VOutputs OUTA, OUTB P
GND
- 0.3 to V
C
+ 0.3 VI
CLK
Clock output current CLK/LEB – 5 mAI
O(EA)
Error amplifier output current EAOUT 5 mAI
SS
Soft-start sink current SS 20 mAI
OSC
Oscillator charging current RT – 5 mAT
J
Operating virtual junction temperature range – 55 to 150 ° CT
STG
Storage temperature – 65 to 150 ° CLead temperature 1,6 mm (1/16 inch) from cases for 10 seconds 300 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 .....................................................................................................................................................
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over operating free-air temperature range (T
A
= T
J
= – 55 ° C to 125 ° C), unless otherwise noted.
MIN MAX UNIT
V
CC
Supply voltage 12 20 VSink/source output current (continuous or time average) 0 100 mAReference load current 0 10 mA
T
A
= – 55 ° C to 125 ° C, R
T
= 3.65 k Ω, C
T
= 1 nF, V
CC
= 12 V, T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE, V
REF
V
O
Ouput voltage range T
J
= 25 ° C, I
O
= 1 mA 5.05 5.1 5.15 VLine regulation 12 V ≤VCC ≤20 V 2 15
mVLoad regulation 1 mA ≤I
O
≤10 mA 5 20Total output variation Line, load, temperature 5.03 5.17 VTemperature stability
(1)
T
(min)
< T
A
< T
(max)
0.2 0.4 mV/ ° COutput noise voltage 10 Hz < f < 10 kHz 50 µV
RMS
Short circuit current VREF = 0 V 30 60 90 mA
OSCILLATOR
T
J
= 25 ° C 375 400 425 kHzf
OSC
Initial accuracy
(1)
R
T
= 6.6 k Ω, C
T
= 220 pF, T
A
= 25 ° C 0.9 1 1.1 MHzLine, temperature 350 450 kHzTotal variation
(1)
R
T
= 6.6 k Ω, C
T
= 220 pF 0.82 1.18 MHzVoltage stability 12 V < VCC < 20 V 1%Temperature stability T
(min)
< T
A
< T
(max)
± 5%High-level output voltage, clock 3.7 4Low-level output voltage, clock 0 0.2Ramp peak 2.6 2.8 3 VRamp valley 0.7 1 1.25Ramp valley-to-peak 1.55 1.8 2I
OSC
Oscillator discharge current R
T
= OPEN, V
CT
= 2 V 8.5 10 11 mA
ERROR AMPLIFIER
Input offset voltage 2 10 mVInput bias current 0.6 3
µAInput offset current 0.1 1Open loop gain 1 V < V
O
< 4 V 60 95CMRR Common mode rejection ratio 1.5 V < V
CM
< 5.5 V 75 95 dBPSRR Power supply rejection ratio 12 V < V
CC
< 20 V 85 110I
O(sink)
Output sink current V
EAOUT
= 1 V 1 2.5
mAI
O(src)
Output source current V
EAOUT
= 4 V – 0.5 – 1.3High-level output voltage I
EAOUT
= – 0.5 mA 4.5 4.7 5
VLow-level output voltage I
EAOUT
= – 1 mA 0 0.5 1Gain bandwidth product
(1)
f = 200 kHz 6 12 MhzSlew rate
(1)
5 7 V/ µs
(1) Parameters ensured by design and/or characterization, if not production tested.
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ELECTRICAL CHARACTERISTICS (Continued)
UC1825A-SP
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..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
T
A
= – 55 ° C to 125 ° C, R
T
= 3.65 k Ω, C
T
= 1 nF, V
CC
= 12 V, T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIIONS MIN TYP MAX UNIT
PWM COMPARATOR
I
BIAS
Bias current, RAMP V
RAMP
= 0 V – 1 – 8 µAMinimum duty cycle 0%Maximum duty cycle 85%t
LEB
Leading edge blanking time R
LEB
= 2 k Ω, C
LEB
= 470 pF 300 375 450 nsR
LEB
Leading edge blanking resistance V
CLK/LEB
= 3 V 8.5 10.0 11.5 k Ω
V
ZDC
Zero dc threshold voltage, EAOUT V
RAMP
= 0 V 1.10 1.25 1.4 Vt
DELAY
Delay-to-output time
(1)
V
EAOUT
= 5 V to 0 V step 50 120 ns
CURRENT LIMIT / START SEQUENCE / FAULT
I
SS
Soft-start charge current V
SS
= 2.5 V 8 14 20 µAV
SS
Full soft-start threshold voltage 4.3 5 VI
DSCH
Restart discharge current V
SS
= 2.5 V 100 250 350 µAI
SS
Restart threshold voltage 0.3 0.5 VI
BIAS
ILIM bias current 0 V ≤V
ILIM
≤1.5 V 15 µAI
CL
Current limit threshold voltage 0.95 1 1.05
VOvercurrent threshold voltage 1.14 1.2 1.26t
d
Delay-to-output time, ILIM
(1)
V
ILIM
= 0 V to 2 V step 50 80 ns
OUTPUT
I
OUT
= 20 mA 0.25 0.45Low-level output saturationvoltage
I
OUT
= 200 mA 1.2 2.2
VI
OUT
= -20 mA 1.9 2.9High-level output saturationvoltage
I
OUT
= -200 mA 2 3t
r
, t
f
Rise/fall time
(1)
C
L
= 1 nF 20 45 ns
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage 8.3 9.2 9.6
VUVLO hysteresis 0.4 0.8 1.25
SUPPLY CURRENT
I
su
Startup current VC = VCC = 8 V 100 300 µAI
CC
Input current 28 36 mA
(1) Parameters ensured by design and/or characterization, if not production tested.
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APPLICATION INFORMATION
RT+3 V
(10 mA) ǒ1*DMAXǓCT+ǒ1.6 DMAXǓ
ǒRT fǓ
(1)
UDG-95102
1 k 10 k
70
75
80
85
90
95
100
100 k
DMAX - Maximum Duty Cycle - %
RT - Timing Resistance - W
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
10 M
1 M
100 k
10 k
1 k 10 k 100 k
RT - Timing Resistance - W
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
f - Frequency - Hz
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 .....................................................................................................................................................
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The oscillator of the UC1825A is a saw tooth. The rising edge is governed by a current controlled by the RT pinand value of capacitance at the CT pin (C
CT
). The falling edge of the sawtooth sets dead time for the outputs.Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based onthe desired frequency (RT) and D
MAX
. The design equations are:
Recommended values for R
T
range from 1 k Ωto 100 k Ω. Control of D
MAX
less than 70% is not recommended.
Figure 1. Oscillator
Figure 2. Figure 3.
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LEADING EDGE BLANKING
tLEB +0.5 ǒRø10 kWǓ C
(2)
UDG-95105
UVLO, SOFT-START AND FAULT MANAGEMENT
UC1825A-SP
www.ti.com
..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
The UC1825A performs fixed frequency pulse width modulation control. The UC1825A outputs are alternatelycontrolled. During every other cycle, one output is off. Each output then switches at one-half the oscillatorfrequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of theoscillator. On the falling edge of the clock, the appropriate output is driven high. The end of the pulse iscontrolled by the PWM comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminatesthe pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of timeafter the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. ThePWM ramp input may not require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time setby C and the internal 10-k Ωresistor determines the blanked interval. The 10-k Ωresistor has a 10% tolerance.For more accuracy, an external 2-k Ω1% resistor (R) can be added, resulting in an equivalent resistance of1.66 k Ωwith a tolerance of 2.4%. The design equation is:
Values of R less than 2 k Ωshould not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-Vthreshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophicovercurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and theoutputs driven low. For this reason, some noise filtering may be required on the ILIM pin.
Figure 4. Leading Edge Blanking Operational Waveforms
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the erroramplifier output is also forced low. While the internal 9- µA source charges the SS pin, the error amplifier outputfollows until closed loop regulation takes over.
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UDG-95106
ACTIVE LOW OUTPUTS DURING UVLO
UDG-95106
UDG-95108
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 .....................................................................................................................................................
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Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is thendischarged by a 250- µA current sink. No more output pulses are allowed until soft-start is fully discharged andILIM is below 1.2 V. At this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitordoes not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuousfault conditions.
Figure 5. Soft-Start and Fault Waveforms
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip tooperate.
Figure 6. Output Voltage vs Output Current Figure 7. Output V and I During UVLO
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CONTROL METHODS
UDG-95109
UDG-95110
Current Mode Voltage Mode
.
SYNCHRONIZATION
UDG-95113
UDG-95112
UC1825A-SP
www.ti.com
..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
Figure 8. Control Methods
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program thefree running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. Thepulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edgeof the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin nolonger accepts an incoming synchronizing signal.
Figure 9. General Oscillator Synchronization Figure 10. Two Unit Interface
Figure 11. Operational Waveforms
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HIGH CURRENT OUTPUTS
UDG-95114
GROUND PLANES
UC1825A-SP
SLUS873A – JANUARY 2009 – REVISED APRIL 2009 .....................................................................................................................................................
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Each totem pole output of the UC1825A can deliver a 2-A peak current into a capacitive load. The output canslew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground(PGND) pins help decouple the device's analog circuitry from the high-power gate drive noise. The use of 3-ASchottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC andPGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type ofinductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forwardvoltage drop is required. DO NOT USE standard silicon diodes.
Figure 12. Power MOSFET Drive Circuit
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correctoperation of the chip. A ground plane must be employed. A unique section of the ground plane must bedesignated for high di/dt currents associated with the output stages. This point is the power ground to which thePGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at asingle point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCCshould be bypassed directly to power ground with a good high frequency capacitor. The sources of the powerMOSFET should connect to power ground as should the return connection for input power to the system and thebulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND.Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequencycapacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analogcircuitry should likewise be bypassed to the signal ground plane.
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UDG-95115
OPEN LOOP TEST CIRCUIT
UDG-95116
UC1825A-SP
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..................................................................................................................................................... SLUS873A – JANUARY 2009 – REVISED APRIL 2009
Figure 13. Ground Planes Diagram
This test fixture is useful for exercising many functions of this device family and measuring their specifications.As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a groundplane is highly recommended.
Figure 14. Open Loop Test Circuit Schematic
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8768102V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8768102VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
5962-8768105VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1825A-SP :
•Catalog: UC1825A
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 2
•Catalog - TI's standard catalog product
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