ARA3000 Address-Programmable Telephony Reverse Amplifier with Step Attenuator PRELIMINARY DATA SHEET - Rev 1.1 FEATURES * * * * * * * * * Low cost integrated amplifier with step attenuator Attenuation Range: 0-56 dB, adjustable in 2 dB increments via a 3 wire serial control Meets DOCSIS distortion requirements at a +60dBmV output signal level Programmable address allows multiple parts to share control bus Programmable 2 bit data port output Low distortion and low noise Frequency range: 5-100 MHz 5 Volt operation -40 to +85 oC temperature range APPLICATIONS * * * * DOCSIS Compliant IP Telephony Systems CATV Interactive Set-Top Box OpenCable Set-Top Box Residential Gateway S23 Package 28 Pin SSOP with Exposed Paddle PRODUCT DESCRIPTION The ARA3000 is designed to provide additional reverse path amplification and isolation in IP Telephony systems. It incorporates a digitally controlled precision step attenuator, followed by a single-stage output amplifier that exceeds DOCSIS distortion and noise requirements at a +60dBmV output level while only requiring a single polarity +5V supply. The precision attenuator can handle input powers up to +58 dBmV, and provides up to 56 dB of attenuation in 2 dB increments. The output amplifier stage can be shut down and bypassed by a low insertion loss switch on-chip to save power. The ARA3000 has a programmable address that allows multiple devices to share a common control bus, and a 2-bit data port for control of external devices. The ARA3000 is offered in a 28-pin SSOP package featuring an exposed paddle on the bottom of the package. Bypass 5 Bit Attenutor ATTNIN AMPOUT 32 / 16 / 8 / 4 / 2dB Data Port D[1:0] 2 Serial to Parallel Interface 2 CLK DAT EN Address C[1:0] VCTRL Figure 1. Functional Block Diagram 08/2001 ARA3000 1 AMPIN 2 ATTNOUT GND 28 Bypass 3 N/C 27 AMPACG2 4 26 ATTNACG2 GND 25 5 ATTNACG2 GND 24 6 ATTNACG2 AMPOUT 23 7 ATTNACG1 AMPACG1 22 8 ATTNACG1 VCTRL 21 9 ATTNIN GND 20 10 VATTN GNDCMOS 19 11 VCMOS D1 18 12 CLK D0 17 13 DAT C1 16 14 EN C0 15 Figure 2: Pin Out Table 1: Pin Description PIN N AME D ESC R IPTION PIN N AME 1 AMPIN 15 C0 D evi ce Address 0 2 ATTNOUT 16 C1 D evi ce Address 1 3 N/C 17 D0 D ata Port Output 0 4 ATTNACG2 Attenuator AC Ground 2 (3) 18 D1 D ata Port Output 1 5 ATTNACG2 Attenuator AC Ground 2 (3) 19 GND CMOS 6 ATTNACG2 Attenuator AC Ground 2 (3) 20 GND Ground 7 ATTNACG1 Attenuator AC Ground 1 (3) 21 VCTRL Ampli fi er C ontrol (Enable / Bypass) 8 ATTNACG1 Attenuator AC Ground 1 (3) 22 AMPACG1 Ampli fi er AC Ground 1 9 ATTNIN 23 AMPOUT Ampli fi er Output 10 VATTN Attenuator Supply 24 GND Ground 11 VCMOS Supply For D i gi tal C MOS C i rcui t 25 GND Ground 12 C LK C lock 26 AMPACG2 Ampli fi er AC Ground 2 13 D AT D ata 27 Bypass Ampli fi er Bypass Output 14 EN Enable 28 GND Ampli fi er Input Attenuator Output No C onnecti on Attenuator Input (2) (1) (2) Notes: (1) The N/C pin should be grounded (2) Pins should be AC-coupled. No external DC bias should be applied. (3) Pins should be AC-grounded. No external DC bias should be applied. 2 PRELIMINARY DATA SHEET - Rev 1.1 08/2001 D ESC R IPTION Ground for D i gi tal C MOS C i rcui t Ground (3) (3) (2) ARA3000 ELECTRICAL CHARACTERISTICS Table 2: Absolute Minimum and Maximum Ratings PAR AMETER MIN MAX U N IT Analog Supply (pi ns 10, 23) 0 9 VD C D i gi tal Supply: VCMOS (pi n 11) 0 6 VD C Ampli fi er C ontrol: VCTRL (pi n 21) -5 6 V RF Power at Input (pi n 9) - 58 dBmV D i gi tal Interface (pi ns 12, 13, 14, 15, 16) -0.5 VCMOS+0.5 V Storage Temperature -55 +200 o C Solderi ng Temperature - 260 o C Solderi ng Ti me - 5 S ec Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: 1. Pins 2, 9 and 27 should be AC-coupled. No external DC bias should be applied. 2. Pin 1 should be pulled to ground through a resistor. No external DC bias should be applied. 3. Pins 4, 5, 6, 7, 8, 22 and 26 should be AC-grounded. No external DC bias should be applied. Table 3: Operating Ranges PAR AMETER MIN TYP MAX U N IT Analog Supply: VDD (pi ns 10, 23) 4.5 5 7 VD C D i gi tal Supply: VCMOS (pi n 11) 3.0 - 5.5 VD C D i gi tal Interface (pi ns 12, 13, 14, 15, 16) 0 - VCMOS V Ampli fi er C ontrol: VCTRL (pi n 21) 0 3 5.5 V -40 25 85 C ase Temperature o C The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. PRELIMINARY DATA SHEET - Rev 1.1 08/2001 3 ARA3000 Table 4: DC Electrical Specifications TA=25C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed) PAR AMETER MIN TYP MAX U N IT C OMMEN TS Analog Supply C urrent (pi ns 10, 23) - 120 12 - mA Ampli fi er enabled Ampli fi er bypassed C MOS D i gi tal Supply C urrent (pi n 11) - 2 - mA Max attenuati on setti ng Total Power C onsumpti on - 610 70 - mW mW Ampli fi er enabled Ampli fi er bypassed Table 5: AC Electrical Specifications TA=25C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed) PAR AMETER MIN TYP MAX U N IT 14 16 - dB 0 dB attenuati on setti ng, ampli fi er enabled -2.5 -1.7 - dB 0 dB attenuati on setti ng, ampli fi er bypassed Gai n Flatness - 0.5 - dB 5 to 42 MHz Gai n Vari ati on over Temperature - -0.006 - dB/C 1.54 3.6 7.7 15.5 30.2 1.75 3.9 8.1 15.9 30.7 2.0 4.2 8.3 16.3 31.2 - 60 - Gai n Attenuati on Steps 2 dB 4 dB 8 dB 16 dB 32 dB Maxi mum Isolati on dB Monotoni c - dB 62 dB attenuti on setti ng, ampli fi er di sabled -55 -48 dB c POUT = +60 dBmV i nto 75 Ohms, ampli fi er enabled - -60 -48 dB c PIN = +58 dBmV from 75 Ohms, ampli fi er bypassed - -60 -48 dB c POUT = +60 dBmV i nto 75 Ohms, ampli fi er enabled - -60 -48 dB c PIN = +58 dBmV from 75 Ohms, ampli fi er bypassed 2nd Harmoni c D i storti on Level 3rd Harmoni c D i storti on Level Note: As measured in ANADIGICS test fixture 4 C OMMEN TS PRELIMINARY DATA SHEET - Rev 1.1 08/2001 ARA3000 continued: AC Electrical Specifications TA=25C; VDD, VCMOS = +5.0 VDC; VCTRL = +5.0 V (Amp enabled); VCTRL = 0 V (Amp bypassed) PAR AMETER MIN TYP MAX U N IT C OMMEN TS 78 - - dBmV Ampli fi er enabled 1 dB Gai n C ompressi on Poi nt - 70 - dBmV Ampli fi er enabled Noi se Fi gure - 3.5 - dB Input Impedance - 75 - Ohms Input Return Loss - -20 -13 - dB Output Impedance - 75 - Ohms Output Return Loss - -15 -13 - dB 3rd Order Output Intercept Ampli fi er enabled Ampli fi er bypassed Ampli fi er enabled Ampli fi er bypassed Note: As measured in ANADIGICS test fixture PRELIMINARY DATA SHEET - Rev 1.1 08/2001 5 ARA3000 6 +5 V 1uF 1 KOhm 0.1uF AMPIN 2 ATTNOUT 3 N/C 4 ATTNACG2 GND 25 ATTNACG2 GND 24 6 ATTNACG2 AMPOUT 23 7 ATTNACG1 AMPACG1 22 21 5 0.1uF 0.1uF 1uF 0.1uF 28 Bypass 27 0.1uF 0.1uF AMPACG2 26 8 ATTNACG1 VCTRL 9 ATTNIN GND 20 10 VATTN 11 VCMOS D1 18 12 CLK D0 17 13 DAT C1 16 14 EN C0 15 0.1uF 10uH 0.1uF RF Outpu (75 Ohms 0.1uF GNDCMOS 19 Note: Pins 15 and 16 are grounded on the ANADIGICS test fixture, identifying device address "00". D0 Data +5 V GND ARA3000 Enable RF Input (75 Ohms) Clock Figure 3: Test Circuit PRELIMINARY DATA SHEET - Rev 1.1 08/2001 0.1uF 1 ARA3000 LOGIC PROGRAMMING Programming Instructions The programming word is set through a 16 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register. Table 6: Programming Word D ATA B IT D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Value P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 C1 C0 A1 A0 Table 7: Data Description Table 8: Device Address LOGIC LEVEL IN PU T TO AD D R ESS D EVIC E VALU E R EGISTER AD D R E S S " 0 0 " FU N C TION R EGISTER AD D R ESS "11" FU N C TION (1=on, 0=by pass) C1 C0 Pin 16 (C 1) Pin 15 (C 0) P7 N/A N/A 0 0 0 0 P6 N/A N/A 1 0 1 0 P5 N/A 32 dB Attenuator Bi t 0 1 0 1 1 1 1 1 P4 N/A 16 dB Attenuator Bi t P3 N/A 8 dB Attenuator Bi t P2 N/A 4 dB Attenuator Bi t P1 External D ata Port 1 Output 2 dB Attenuator Bi t External D ata Port 0 Output N/A P0 DATA D15: MSB D14 The device is selected when the logic inputs at pins 16 and 15 match the values of data bits C1 and C0, respectively. Table 9: Register Address D8 A1 A0 FU N C TION 0 0 D ata Port Output Enabled 1 1 Attenuator C ontrol Enabled D7 D1 D0: LSB CLOCK ENABLE OR ENABLE Figure 4: Serial Data Input Timing PRELIMINARY DATA SHEET - Rev 1.1 08/2001 7 ARA3000 APPLICATION INFORMATION Amplifier Enable and Disable/Bypass The amplifier in the ARA3000 can be shut down and bypassed via external control pin VCTRL (pin 21). By applying a logic high voltage to this pin, the amplifier is enabled and the output is routed to AMPOUT (pin 23). A logic low will disable the amplifier, bypass it, and route the attenuator output to the Bypass pin (pin 27). A practical way to implement amplifier control is to connect one of the data port outputs to the VCTRL input, allowing the attenuator to be controlled through the serial programming interface. Output Power Control The amplifier is designed to achieve the specified distortion levels at a nominal output power of +60 dBmV. When higher input powers are applied to the device, the attenuator should be adjusted to maintain the appropriate output power. Thermal Layout Considerations The device package for the ARA3000 features an exposed paddle on the bottom of the package body. Use of the paddle is an integral part of the device design. Soldering this paddle to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the paddle is shown in Figure 5. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 6. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions. Figure 5: PC Board Layout 8 PRELIMINARY DATA SHEET - Rev 1.1 08/2001 ARA3000 Figure 6: Solder Mask Outline PRELIMINARY DATA SHEET - Rev 1.1 08/2001 9 ARA3000 PACKAGE OUTLINE SYMBOLS A A1 A2 b C D E H e L y T S DIMENSIONS IN INCHES MIN 0.057 0.000 0.057 0.008 0.007 0.386 0.150 0.228 0.025 0.016 --- 0 --- --- DIMENSIONS IN MILLIMETERS MAX 0.061 0.004 MIN 1.45 0.00 0.012 0.010 0.394 0.157 0.244 0.20 0.18 9.80 3.81 5.80 0.050 0.004 8 0.190 0.096 0.40 --- 0 --- --- 1.45 .64 MAX 1.55 0.10 NOTE 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND GATE BURRS 2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED 3. CONTROLLING DIMENSION ARE INCHES. 4. REF. - MO-137 0.30 0.25 10.00 4.00 6.20 1.27 0.10 8 4.82 2.43 Figure 7: S23 Package Outline - 28 Pin SSOP with Exposed Paddle 10 PRELIMINARY DATA SHEET - Rev 1.1 08/2001 ARA3000 COMPONENT PACKAGING Volume quantities of the ARA3000 are supplied on tape and reel. Each reel holds 3,500 pieces. Smaller quantities are available in plastic tubes of 50 pieces. Figure 8: Reel Dimensions DIRECTION OF FEED Figure 9: Tape Dimensions PRELIMINARY DATA SHEET - Rev 1.1 08/2001 11 ARA3000 ORDERING INFORMATION OR D ER N U MB ER TEMPER ATU R E R AN GE PAC K AGE D ESC R IPTION ARA3000S23P1 -40 to 85 oC 28 Pi n SSOP wi th Exposed Paddle 3,500 pi ece tape and reel ARA3000S23P0 -40 to 85 oC 28 Pi n SSOP wi th Exposed Paddle Plasti c tubes (50 pi eces per tube) C OMPON EN T PAC K AGIN G ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 12 PRELIMINARY DATA SHEET - Rev 1 08/2001