XRT91L32IQTR-F - Exar - Product.Network

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exa r.c om

xr XRT91L32

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

JUNE 2007 REV. 1.0.3

GENERAL DESCRIPTION

The XRT91L32 is a fully integrated SONET/SDH

transceiver for SONET/SDH 622.08 Mbps STS-12/

STM-4 or 155.52 Mbps STS-3/STM-1 applications.

The transceiver includes an on-chip Clock Multiplier

Unit (CMU), which uses a high frequency Phase-

Locked Loop (PLL) to generate the high-speed

transmit serial clock from a slower external clock

reference. It also provides Clock and Data Recovery

(CDR) function by synchronizing its on-chip Voltage

Controlled Oscillator (VCO) to the incoming serial

data stream. The internal CDR unit can be disabled

and bypassed in lieu of an externally recovered

received clock from the optical module. Either the

internal ly recov ered clock or the extern ally reco vered

clock can be used for loop timing applications. The

chip provides serial-to-parallel and parallel-to-serial

converters using an 8-bit wide LVTTL system

interface in both receive and transmit directions.

The transmit section includes an option to accept a

parallel clock signal from the framer/mapper to

synchronize the transmit section timing. The device

can inter nally monit or Los s of Signal (LO S) condition

and automatically mute received data upon LOS. An

on-chip SONET/SDH frame byte and boundary

detector and frame pulse generator offers the ability

recover SONET/SDH framing and to byte align the

receive serial data stream into the 8-bit parallel bus.

APPLICATIONS

•SONET/S DH- based Transmiss ion Systems

•Add/Drop Multiplexers

•Cross Connect Equipment

•ATM and Multi-Service Switches, Routers and

Switch/Routers

•DSLAMS

•SONET/SDH Test Equipment

•DWDM Termination Equipment

FIGURE 1. BLOCK DIAGRAM OF XRT 91 L 32

XRT91L32

Reset

DLOOP

RLOOPS

LOOPTIME

LOSEXT

STS-12/STS-3

ALOOP

DLOSDIS

FRAMEPULSE

OOF

Clock Control

Contro l Bl ock

CDRDIS

CDRREFSEL

CMUFREQSEL

STS-12/STM-4 or STS-3/STM-1

TRANSCEIVER

Loop F il ters

CAP1P

CAP2P

CAP1N

CAP2N

RXDO[7:0]

RXPCLKO

CDR RXIP/N

Div by 8

XRXCLKIP/N

SIPO

(Seria l I nput

Parallel Output)

MUX

PISO

(Par allel I npu t

Serial Output)

DLOOP

RLOOPS

Re-Timer

CMU

TXOP/N

MUX

XOR

TTLREFCLK

REFCLKP/N

CDRAUXREFCLK

MUX

TXPCLK_IO Div by

ENB

TXDI[7:0]

MUX

ALOOP

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REV. 1.0.3

FEATURES

•Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications

•Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1

155.52 Mbps

•Single- ch ip fu ll y in teg ra ted s olu tio n containing par all el -to- se rial c on ver te r, cloc k mu lti pli er uni t (C M U) , s eria l-

to-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary

detection circuit

•Ability to disable and bypass onchip CDR for external based received reference clock recovery thru

Differential LVPECL input pins XRXCLKIP/N

•8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1

mode of operation

•Uses Differentia l LV PECL or Si ngle-Ended LVT TL CMU refe rence clock frequencie s of either 19.44 MHz or

77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations

•Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation

•Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus

•Diagnostics features include LOS monitoring and automatic received data mute upon LOS

•Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode

•Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing

signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized

with the transceiver transmit timing.

•Meets Telcordia, ANSI, Bellcore TR-NWT-000253 and GR-253-CORE, and G.783 ITU-T jitter requirements

•Operates at 3.3V with 3.3V I/O

•Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation

•Package: 10 x 10 x 2.0 mm 100-pin QFP

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

FIGURE 2. 100 QFP PIN OUT OF THE XRT91L32 (TOP VIEW)

XRT91L32

VDD3.3

GND

RXDO0

RXD01

GND

RXDO2

RXDO3

GND

RXDO4

RXDO5

GND

RXDO6

RXDO7

GND

RXPCLKO

RAMEPULSE

VDD3.3

100

RLOOPS

VDD3.3

ALOOP

RESET

LOOPTIME

MUFREQSEL

VDD_PECL

TXOP

TXON

GND

VDD_PECL

DLOSDIS

GND

XRXCLKIP

XRXCLKIN

VDD_PECL

OOF

CDRDIS

RXIP

RXIN

VDD3.3

REFCLKP

REFCLKN

VDD3.3

GND

AGND_RX

AVDD3.3_RX

CAP2P

CAP2N

CAP1N

CAP1P

AVDD3.3_TX

AGND_TX

VDD3.3

TTLREFCLK

GND

VDD3.3

LOSEXT

CDRAUXREFCL

DLOOP

VDD3.3

CDRREFSE

STS12/STS

TXDI0

TXDI1

GND

TXDI2

TXDI3

TXIN4

TXDI5

GND

TXDI6

TXDI7

GND

TXPCLK_IO

VDD

ORDERING INFORMATION

PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT91L32IQ-F 100 Pin QFP -40°C to +85°C

XRT91L32 xr

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

TABLE OF CONTENTS

GENERAL DESCRIPTION.................................................................................................1

APPLICATIONS...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF XRT91L32..................... .. .. .. .. .... ..... .. .. .. .. .... .. .. ..... .. .. .... .. .. .. .. ....... .. .. .. .. .. .. ....... .. .. .. .. .... .. .. ................. 1

FEATURES......................................................................................................................................................2

FIGURE 2. 100 QFP PIN OUT OF THE XRT91L32 (TOP VIEW).......................................................................................................... 3

ORDERING INFORMATION.....................................................................................................................3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

.....................................................................................................................................................................4

HARDWARE CONTROL ....................................................................................................................................4

TRANSMITTER SECTION ..................................................................................................................................6

RECEIVER SECTION........................................................................................................................................8

POWER AND GROUND ....................................................................................................................................9

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................11

1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 11

1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 11

TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 11

1.3 DATA LATENCY ............................................................................................................................................. 11

TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 11

2.0 RECEIVE SECTION .............................................................................................................................12

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 12

FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 12

2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 13

FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM.......................................................................................... 13

TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 13

TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/ST M-1 OPERATION)............................................................... 13

2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14

TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 14

TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE.......................................................................................................... 15

2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS........................................................................................ .. .. 15

FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS............................................................................................................ 15

2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16

FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16

2.5 LOSS OF SIGNAL .......................................................................................................................................... 16

FIGURE 7. LOS DECLARATION CIRCUIT........................................................................................................................................... 16

2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17

2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17

FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ...........................................................................................................................17

2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18

FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 18

2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18

2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19

FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 19

TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 19

TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/S TM -1 O PERATION)........................................................................... 19

TABLE 9: PECL AND TT L R ECEIVE OUTPUTS TIMING SPECIFICATION.............................................................................................. 20

3.0 TRANSMIT SECTION ..........................................................................................................................21

3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 21

FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 21

3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 22

FIGURE 12. TRANSMIT PARALLEL INPUT TIMING.............................................................................................................................. 22

TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 22

TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 22

3.3 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 23

FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 23

3.4 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 23

TABLE 12: CLOCK MULTIPLIER UNIT PERFORMANCE ....................................................................................................................... 23

3.5 LOOP TIMING AND CLOCK CONTROL ...................... ...... ...... ..... ...... ..... ................. ...... ..... ...... ...... .............. 24

TABLE 13: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS ................................................................................................. 24

xr XRT91L32

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

FIGURE 14. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK ....................................................... 25

3.6 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 25

FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK.............................................................................................................. 25

4.0 DIAGNOSTIC FEATURES ...................................................................................................................26

4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 26

FIGURE 16. SERIAL REMOTE LOOPBACK......................................................................................................................................... 26

4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 26

FIGURE 17. DIGITAL LOCAL LOOPBACK........................................................................................................................................... 26

4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 27

FIGURE 18. ANALOG LOCAL LOOPBACK.......................................................................................................................................... 27

4.4 SPLIT LOOPBACK ......................................................................................................................................... 27

FIGURE 19. SPLIT LOOPBACK......................................................................................................................................................... 27

4.5 EYE DIAGRAM ............................................................................................................................................... 28

FIGURE 20. STS-3/ST M -1 EYE DIAGRAM ...................................................................................................................................... 28

FIGURE 21. STS-12/ST M -4 EYE DIAGRAM .................................................................................................................................... 28

4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 29

4.6.1 JITTER TOLERANCE:................................................................................................................................................ 29

FIGURE 22. JITTER TOLERANCE MASK............................................................................................................................................ 29

FIGURE 23. XRT91L32 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS- 1 2 /STM-4........ ...... ................. ................. ...... ........ 30

FIGURE 24. XRT91L32 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS- 3 /STM-1........ ...... ................. ...... ................. .......... 30

4.6.2 JITTER GENERATION................................................................................................................................................ 31

FIGURE 25. XRT91L32 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 622.08 MBPS STS-12/STM4 USING

’1010’ OUTPUT PATTERN................................................................................................................................................. 31

5.0 ELECTRICAL CHARACTERISTICS ...................................................................................................32

ABSOLUTE MAXIMUM RATINGS .... ...... ....... ................... ....... ...... ...... ....... ...... ....... ...... ....... ................... .......32

ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS .........................................................32

POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS....................................................................32

...................................................................................................................................................................32

LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS......................................33

ORDERING INFORMATION ..................................................................................................................34

PACKAGE DIMENSIONS.......................... ..... ..... .............. .... ..... ..... .............. .... ..... ..... ....34

REVISION HISTORY ......................................................................................................................................35

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

PIN DESCRIPTIONS

L32

HARDWARE CONTROL

NAME LEVEL TYPE PIN DESCRIPTION

RESET LVTTL I 4 Remote Serial Loopback

Active "High." When this pin is pulled "High" , the internal state

machines are set to their default state.

"Low" = Normal Operation

"High" = Master Hardware Reset ( minimum 100nS)

STS12/STS3 LVTTL I97 Data Rate Selection

Selects SONET/SDH transmission and reception speed rate

"Low" = STS-3/STM-1 155.52 Mbps

"High" = STS-12/STM-4 622.08 Mbps

CMUFREQSEL LVTTL I 8 Clock Multiplier Unit Reference Frequency Select

This pin is used to select the frequency of the REFCLKP/N or

TTLREFCLK input to the CMU.

"Low" = 77.76 MHz reference clock

"High" = 19.44 MHz reference clock

NOTE: REFCLKP/N or TTLREFCLK input should be generated

from an LVPECL/LVTTL crystal oscillator which has a

frequency accuracy better than 20ppm in order for the

transmitted data rate frequency to have the necessary

accuracy required for SONET systems..

CMU-

FREQSEL STS12/

STS3

REFCLKP/N OR

TTLREFCLK

REFERENCE

FREQUENCY

DATA RATE

0077.76 MHz STS-3/STM-1

155.52 Mbps

0 1 77.76 MHz STS-12/STM-4

622.08 Mbps

1019.44 MHz STS-3/STM-1

155.52 Mbps

1 1 19.44 MHz STS-12/STM-4

622.08 Mbps

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

CDRREFSEL LVTTL I98 Clock and Data Recover Unit Reference Frequency Select

Selects the Cloc k an d D at a Re cov ery U nit refere nc e freq uency

based on the table below.

"Low" = CDR uses CMU’s reference clock

"High" = CDR reference clock from CDRAUXREFCLK

NOTE: CDRAUXREFCLK requires accuracy of 77.76 MHz

+/- 500ppm.

LOOPTIME LVTTL I 5 Loop Timing Mode

When the loop timing mode is activated the external reference

clock to th e input of the Retimer i s replaced with the high -speed

recovered receive clock from the CDR.

"Low" = Disabled

"High" = Loop timing Activated

CDRDIS LVTTL I23 Clock and Data Recovery Unit Disable

Active "High." Disables internal Clock and Data Recovery unit.

Received serial data bypasses the integrated CDR block.

RXINP/N is then sampled on the rising edge of externally

recovered differential clock XRXCLKIP/N coming from the opti-

cal module.

"Low" = Internal CDR unit is Enabled

"High" = Internal CDR unit is Disabled and Bypassed

RLOOPS LVTTL I 1 Serial Remote Loopback

The serial remote loopback mode interconnects the receive

serial data input to the transmit serial data output. If serial

remote l oopback is ena bled, the 8-bit parallel transmit data

input is ignored while the 8-bit parallel receive data output is

maintained.

"Low" = Disabled

"High" = Serial Remote Loopback Mode Enabled

NOTE: DLOOP and RLOOPS can be enabled simultaneously

to achieve a dual lo opb ack dia gnostic feat ure in norm al

operation.

NC No Connect -6,7,13,

14,16,26,

27,32,33,

50,52,57,

61,73,74,

77,78,79,

80,83,90,

NOTE: No connect

NAME LEVEL TYPE PIN DESCRIPTION

CDRREFSEL STS12/

STS3 CDRAUXREFCLK

FREQUENCY DATA RATE

0CDR uses CMU’s reference clock

(see CMUFREQSEL pin)

1077.76 MHz STS-3/STM-1

155.52 Mbps

1177.76 MHz STS-12/STM-4

622.08 Mbps

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

ALOOP LVTTL I 3 Analog Local Loopback

This loopback feature serializes the 8-bit parallel transmit data

input and presents the data to the transmit serial output and in

addition it also internally routes the serialized data back to the

Clock an d Data Reco very block for s eria l to p a r al lel con ve rsi on.

The received seri al data input is ignored.

"Low" = Disabled

"High" = Analog Local Loopback Mode Enabled

DLOOP LVTTL I100 DLOOP Local Loopback

This digital loopback mode interconnects the 8-bit parallel

transmit data input and TXCLK to the 8-bit parallel receive data

output and receive RXCLK respectively while maintaining the

transmit serial data output. If digital loopback is enabled, the

receive serial data input is ignored.

"Low" = Disabled

"High" = Digital Local Loopback Mode Enabled

NOTE: DLOOP and RLOOPS can be enabled simultaneously

to achieve a dual lo opb ac k dia gnostic feat ure in norm al

operation.

TRANSMITTER SECTION

NAME LEVEL TYPE PIN DESCRIPTION

TXDI0

TXDI1

TXDI2

TXDI3

TXDI4

TXDI5

TXDI6

TXDI7

LVTTL I95

Transmit Parallel Data Input

Transmit Parallel Clock Output Operation

The 77.76 Mb ps (STS-12/ST M-4) / 19.44 Mbp s (STS-3/STM-1)

8-bit parallel transmit data should be applied to the transmit

para llel bus an d simu ltaneo usly referenc ed to the risi ng edge of

the TXPCLK_ IO cl oc k out put. The 8 -bit pa rall el in terfa ce is m ul -

tiplexed into the transmit serial output interface with the MSB

first (TXDI[7:0]).

Alternate Transmit Parallel Clock Input Operation

When operating is this mode, TXPCLK_IO is no longer a paral-

lel clock output reference but reverses direction and serves as

the p aralle l trans mit cl ock i nput ref erence for th e PIS O (Paral lel

Input to Se rial Outpu t) blo ck. Th e 77.76 Mbp s (STS-12/STM-4 )

/ 19.44 M bps (STS-3/ST M-1 ) 8-b it parallel tra ns mit da t a s ho uld

be applied to the tra ns mi t p arallel bu s a nd simu lt a neously refe r -

enced to the rising edge of the TXPCLK_IO clock input.

TXOP

TXON LVPECL Diff O10

11 Transmit Serial Data Output

The tran smit serial dat a stream is generated by mu ltiplexing the

8-bit parallel transmit data input into a 622.08 Mbps STS-12/

STM-4 or 155.52 Mbps STS-3/STM-1 seri al data stream.

NAME LEVEL TYPE PIN DESCRIPTION

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

TXPCLK_O LVTTL O82 Transmit Parallel Clock Output (77.76/19.44 MHz)

Transmit Parallel Clock Output Operation

This pin will output a 77 .76 MHz (STS-12/ST M-4) or 19.4 4 MHz

(STS-3/STM-1) clock output reference for the 8-bit parallel

transmit data input TXDI[7:0]. This clock is used by the framer/

mapper device to present the TXDI[7:0] data which the

XRT91L32 will latch on the rising edge of this clock. This

enables the framer/mapper device and the XRT91L32 trans-

ceiv er to be in synchronization .

REFCLKP

REFCLKN LVPECL Diff I29

30 Reference Clock Input (77.76 MHz or 19.44 MHz)

This differential clock input reference is used for the transmit

clock mult ipli er unit (CMU) and clock data recovery (CDR) to

provide the necessary high speed clock reference for this

device. It will accept either a 77. 76 MHz or a 19.44 MHz Differ-

ential LVPECL clock source. Pin CMUFREQSEL determines

the value us ed as the referenc e. See Pin CMUFREQ SEL for

more details. REFCLKP/N inputs are internally biased to 1.65V.

NOTE: In the event that TTLREFCLK LVTTL input is used

instead of these differential inputs for clock reference,

the REFCLKP should be tied to ground.

TTLREFCLK LVTTL I56 Auxillary Reference Clock Input (77.76 MHz or 19.44 MHz)

This LVTTL clock input reference is used for the transmit clock

multiplier unit (CMU) and clock data recovery (CDR) to provide

the ne cess ary hig h spee d cloc k referen ce for thi s devi ce. It w ill

accep t either a 77.7 6 MHz or a 1 9.44 MHz LVTTL clock source.

Pin CMUFREQSEL determines the value used as the refer-

ence. See Pin CMUFREQSEL for more details.

NOTE: In the event that REFCLKP/N differential inputs is used

instead of this LVTTL input for clock reference, the

TTLREFCLK should be tied to ground.

TRANSMITTER SECTION

NAME LEVEL TYPE PIN DESCRIPTION

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

RECEIVER SECTION

NAME LEVEL TYPE PIN DESCRIPTION

RXDO0

RXDO1

RXDO2

RXDO3

RXDO4

RXDO5

RXDO6

RXDO7

LVTTL O35

Receive Parallel Data Output

77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)

8-bit parallel receive data output is updated simultaneously on

the risin g edge of the RXPCLKO ou tput. T he 8-bi t p arallel inter -

face is de-multiplexed from the receive serial data input MSB

first (RXDO[7:0]). The XRT91L32 will output the data on the

rising edge of this clock.

RXIP

RXIN Diff LV PECL I24

25 Receive Serial Data Input

The differential receive serial data stream of 622.08 Mbps

STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to

these input pins.

XRXCLKIP

XRXCLKIN Diff L VPECL I19

20 External Recov ered Re ce ive Clock Input

The differential receive serial data stream of 622.08 Mbps

STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on

the rising edge of this externally recovered differential clock

coming from the optical module. It is used when the internal

CDR unit is disabled and bypassed by the CDRDIS pin.

NOTE: In the event that XRXCLKIP/N differential input pins are

unused, XRXCLKIP should be tied to VCC with a 1k

Ohm pull-up and XRXCLKIN should be tied to Ground

wit h a 1k Ohm pull- down.

RXPCLKO LVTTL O47 Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)

77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)

clo ck output referenc e for the 8-bit parallel receive data output

RXDO[7:0]. The parallel received data output bus will be

updated on the falling edge of this clock.

CDRAUX-

REFCLK LVTTL I51 Clock and Data Recovery Auxillary Reference Clock

77.76 MHz ± 500 ppm auxillary reference clock for the CDR.

NOTE: In the event that CDRAUXREFCLK LVTTL input pin is

unused, CDRAUXREFCLK should be tied to ground.

OOF LVTTL I22 Out of Frame In put Indicator

This level sensitive input pin is used to initiate frame detection

and byte alignment recovery when OOF is declared by the

downstream device. When this pin is held High, FRAME-

PULSE will pul se for a sin gl e RXPC LK O peri od upon t he dete c-

tion of every third frame alignment A2 byte in the incoming

SONET/SDH Frame.

"Low" = Normal Operation

"High" = OOF Indication initiating frame detection and byte

boundary rec ove ry and activ ati ng FRAMEPULSE

FRAMEPULSE LVTTL O48 Sonet Frame Alignment Pulse

This pin will generate a singl e pulse for an RXPCLKO clock

period upon the detection of the third frame alignment A2 byte

whenev er the OOF input p in is held Hig h. The para llel receiv ed

data output bus will then be byte aligned to this newly recov-

ered SONET/SDH frame.

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

POWER AND GROUND

CAP1P

CAP2P Analog -63

66 CDR Non-Invertin g External Fee back Capacitor

C1 = 0.47μF ± 10% tolerance

(Isolate from noise and place close to pin)

CAP1N

CAP2N Analog -64

65 CDR Inverting External Feeback Capacitor

C2 = 0.47μF ± 10% tolerance

(Isolate from noise and place close to pin)

DLOSDIS LVTTL I17 LOS (Los of Signal) Detect Disable

Disables internal LOS monitoring and automati c muting of

RXDO[7:0] upon LOS detection (according to gating shown in

Figure 7.) LOS is declared when a string of 128 consecutive

zeros occur on the line. LOS condition is cleared when the 16

or more pulse transitions is detected for 128 bit period sliding

window.

"Low" = Monitor and Mute received data upon LOS declaration

"High" = Disable internal LOS monitoring (see Figure 7 f or logi c

operation.)

LOSEXT SE-LVPECL I53 LOS or Signal Detect Input from Optical Module

Active "L ow." When ac tiv e, thi s pin c an forc e t he received data

output bus RXDO[7:0] to a logic state of ’0’ per Figure 7.

"Low" = Forced LOS

"High" = Normal Operation

NAME TYPE PIN DESCRIPTION

VDD3.3 PWR 2,28,31,49,54,

58,76,99,81 3.3V CMOS Power Supply

VDD3.3 should be isolated from the analog VDD power supplies.

Use a ferrite bead alo ng with an internal pow er plane sep ara tion.

The VDD3.3 pow e r supply pin s s ho uld hav e b ypass capac itor s to

the nearest ground. For best results, refer to Application notes

about general board lay ou t guide li nes .

AVDD3.3_TX PWR 62 Analog 3.3V Transmitter Power Supply

AVDD3.3_TX should be isolated from the digital power supplies.

For best results, use a ferrite bead along with an internal power

plane separation. The AVDD3.3_TX power supply pins should

have bypass capacitors to the nearest ground.

AVDD3.3_RX PWR 67,,68,69 Analog 3.3V Receiver Power Supply

AVDD3.3_RX should be isolated from the digital power supplies.

For best results, use a ferrite bead along with an internal power

pla ne separation. The AVDD3.3_RX power sup ply pins should

have bypass capacitors to the nearest ground.

VDD_LVPECL PWR 9,15,21 3.3V Input/Output LVPECL Bus Power Supply

These pins require a 3.3V potential voltage for properly biasing

the Differential LVPECL input and output pins.

AGND_TX PWR 59,60 Transmitter Analog Ground for 3.3V Analog Power Supplies

It is recommended that all ground pins of this device be tied

together.

NAME LEVEL TYPE PIN DESCRIPTION

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

AGND_RX PWR 70,71 Receiver Analog Ground for 3.3V Analog Power Supplies

It is recommended that all ground pins of this device be tied

together.

GND GND 12,18,34,37,40,43,46,55,

72,75,84,87,93 Power Supply and Thermal Ground

It is recommended that all ground pins of this device be tied

together.

NAME TYPE PIN DESCRIPTION

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

1.0 FUNCTIONAL DESCRIPTION

The XRT91L32 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-

speed serial inte rface to optical networks. The transceiver converts 8-bit parallel data running at 77.7 6 Mbps

(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622. 08 Mbps or

155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-

serialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte

boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to

provide the front end component of SONET equipment, which includes primarily serial transmit and receive

functions.

1.1 STS-12/STM-4 and STS-3/STM-1 Mode of Operation

Functiona lity of the transceiv er can be c onfigured by using the appropria te signal l evel on the S TS-12/STS-3

pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin

Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."

Therefor e, th e fol lo win g s ec tio ns desc ribe the func ti onality rat her tha n ho w each func tion is co ntrol le d. He nce ,

the hardware Pin and the Register Bit Descriptions focus on device configuration.

1.2 Clock Input Reference for Clock Multiplier (Synthesizer) Unit

The XRT91L32 c an accept both a 19 .44 MHz or a 77 .76 MHz Diffe rential LVP ECL cloc k inp ut at REFCL KP/N

or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed

clocks. The REFCLK P/N or TT LREFCLK input shou ld be gene rated from a n LVPECL /LVTTL c rystal o scilla tor

which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the

necessary accuracy required for SONET systems. The reference clock can be provided with one of two

frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L32 are listed in

Table 1.

1.3 Data Latency

Due to different o perati ng mod es and d ata logic paths through t he devi ce, the re is an a ssoc iated latenc y from

data ingress to data egress. Table 2 specifies the data latency for a typical path.

TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY

TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED)

CMUFREQSEL STS12/STS3 REFCLKP/N OR TTLREFCLK

REFERENCE FREQUENCY DATA RATE

0 0 77.76 MHz STS-3/STM-1

155.52 Mbps

0 1 77.76 MHz STS-12/STM-4

622.08 Mbps

1 0 19.44 MHz STS-3/STM-1

155.52 Mbps

1 1 19.44 MHz STS-12/STM-4

622.08 Mbps

MODE OF

OPERATION DATA PATH CLOCK REFERENCE RANGE OF CLOCK

CYCLES

Thru-mode MSB at RXIP/N to data on RXDO[7:0] Recoved RXIP/N Clock 25 to 35

Serial Remote Loopback MSB at RXIP/N to MSB at TXOP/N Recoved RXIP/N Clock 2 to 4

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.2

2.0 REC EI V E SE CT I O N

The receive section of XRT91L32 include the inputs RXIP/N, followed by the clock and data recovery unit

(CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ)

serial data at 622.08 Mbps or 155.5 2 Mbps through the input int erfaces RXIP /N. The cloc k and data recove ry

unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered

serial data is converted into an 8-bit-wide, 77.76 Mbps or 19.44 Mbps parallel data and presented to the

RXDO[7:0] parallel interface. This parallel interface is designed for Single-Ended LVTTL operation. A divide-

by-8 ver sion of th e high- spee d recov ered cl ock RXPCLK OP/N, is used to sync hronize the transfer o f the 8-bit

RXDO[7:0] data with the receive portion of the framer/mapper device. Upon initialization or loss of signal or

loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock

recove ry phase-loc k ed loop for prope r o perati on . In c er tain app li ca tio ns , the CD R blo ck on the X RT91L32 ca n

be disabled and bypassed by enabling the CDRDIS pin to permit the flexibility of using an externally recovered

receive clock thru the XRXCLKIP/N pins.7

2.1 Receive Serial Input

The receive serial inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an

optical module or an electrical interface. A simplified AC coupling block diagram is shown in Figure 3.(Also,

refer to application note TAN-9132.)

NOTE: Some op tic al mod u le s i nte gr at e A C co up lin g capac i to rs w it hi n th e mo du l e. AC o r DC co upl in g is l arg e ly spe cif ic to

system design and optical module of choice.

FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK

SFP, Optica l Module

RXIP

RXIN Optical Fib e

XRT91L32

STS-12/STM-4

STS-3/STM-1

Transceiver

82 O hm

130 O hm

XRXCLKIP

XRXCLKIN (optional)

1KOhm

Install terminators close to

RXIP and RXIN pins

Tie unused differential input pins

to VCC and GND

Internally

AC co upled

xr XRT91L32

REV. 1.0.2 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

2.2 Recieve Serial Data Input Timing

The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing

specifications below.

TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION)

FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM

TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION)

SYMBOL PARAMETER MIN TYP MAX UNITS

tRXCLK Receive external recovered clock period 1.608 ns

tRX_SU Serial data setup time with respect to XRXCLKIP/N 400 ps

tRX_HD Serial data hold time with respect to XRXCLKIP/N 100 ps

SYMBOL PARAMETER MIN TYP MAX UNITS

tRXCLK Receive exter nal recovered clock period 6.43 ns

tRX_SU Serial data setup time with respect to XRXCLKIP/N 1.5 ns

tRX_HD Serial data hold time with respect to XRXCLKIP/N 1.5 ns

tRXCLK

RXIP

RXIN

XRXCLKIP

XRXCLKIN

tRX_HD

tRX_SU

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.2

2.3 Receive Clock and Data Recovery

The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL

receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either

utilize the transmitter’s CMU reference clock from either REFCLKP/N or TTLREFCLK or it can use

independe nt cl ock sourc e CDRA UXR EFCLK to train a nd mo nit or its c lock rec ov ery P LL . In itial ly u pon s tartup,

the PLL locks to the local reference clock within ±500 ppm. Once this is achieved, the PLL then attempts to

lock o nto th e incoming recei ve data st ream. When ever t he reco vered cl ock fr equency d eviates from th e local

referen ce clock frequen cy by more than approxi mately ±500 ppm , the clock rec overy PLL w ill switch and lo ck

back o nto the l ocal refe rence cl ock. W henever a Loss of Lock or a Lo ss of S ignal event occu rs, the CDR will

continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the

LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be

forced t o a log ic z er o state for the en tir e d urati on that a LO S condition is dete ct ed. This ac ts as a r ec eiv e da ta

mute up on L OS fun ct ion to p re vent r and om noi se fr om b ein g mi sint er preted as va lid i nc omi ng d ata. Whe n th e

LOSEXT becomes inactive and the recovered clock is determined to be within ± 500 ppm accuracy with respect

to the loc al re ference s ourc e and L OS is n o long er dec lared, th e clo ck rec over y PLL wil l swi tch and lock back

onto the incoming receive data stream. Table 5 shows Clock and Data Recovery reference clock settings.

Table 6 specifies the Clock and Data Recovery Unit performance characteristics.

TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS

1Requires frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary

accuracy required for SONET systems.

2CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 500ppm.

CMUFREQSEL CDRREFSEL STS12/

STS3

REFCLKP/N1OR

TTLREFCLK1

FREQUENCY (MHZ)

CDRAUXREFCLK2

FREQUENCY (MHZ)CDR OUTPUT

FREQUENCY (MHZ)

0 0 0 77. 76 MHz not used 155.52

0 0 1 77. 76 MHz not used 622.08

1 0 0 19. 44 MHz not used 155.52

1 0 1 19. 44 MHz not used 622.08

X 1 0 not referenced by CDR 77.76 MHz 155.52

X 1 1 not referenced by CDR 77.76 MHz 622.08

xr XRT91L32

REV. 1.0.2 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE

Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.

1These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms).

2Required to meet SONET output frequency stability requirements.

2.3.1 Internal Clock and Data Recovery Bypass

Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.

Asserting th e CDRDIS "High" disable s the in ternal Cloc k and Da ta Recovery u nit an d the received serial data

bypasses the integrated CD R block. RX INP/N is then sampled on t he rising edg e of the externa lly recove red

differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5

shows the possible internal paths of the recovered clock and data.

NAME PARAMETER MIN TYP MAX UNITS

REFDUTY Reference clock duty cycle 40 60 %

REFJIT Reference clock jitter (rms) with 19.44 MHz refer ence15ps

REFJIT Reference clock jitter (rms) with 77.76 MHz refer ence113 ps

REFTOL Reference clock frequency tolerance2-20 +20 ppm

TOLJIT Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern 0.3 0.4 UI

OCLKFREQ Frequency output 620 624 MHz

OCLKDUTY Clock output duty cycle 40 60 %

FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS

RXIP

RXIN

MUX

CDR

MUX

CDRDIS

Clk

Data

XRXCLKIP

XRXCLKIN

DATA

CLOCK

SIPO

Div by 8 CLOCK

Parallel DATA 8

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.2

2.4 External Receive Loop Filter Capacitors

These external loop filter 0.47μF non-polarized capacitors provide the necessary components to achieve the

required receiver j itter perfor mance. They must be we ll isolate d to prohi bit noise ente ring the CD R block and

should b e placed as close to the p ins as much a s possible. Figure 6 show s the pin co nnections and external

loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.

2.5 Loss Of Signal

XRT91L32 supp orts interna l Loss of Signal dete ction (LOS) an d external LOS de tection. The interna l Loss of

Signal Detector monitors the incoming data stream and if the incoming data stream has no transition

continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed

when the ci rcuit detec ts 16 transitions in a 128 b it period s liding windo w. Pulli ng the corres ponding DL OSDIS

signal to a h igh l evel will di sabl e the inter nal LOS detec tion circuit. The external LOS f uncti on is supp orted by

the LOSEXT input. The Singl e-E nded LVPECL inp ut us ua ll y c ome s from the optic al mod ul e throug h an output

usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the

manufacturer of these devices the polarity of this signal can be either active "Low" or active "High." LOSEXT is

an activ e "Lo w" si gnal r equi ring a l ow lev el to as sert or in voke a forced L OS. The exter nal LOSEXT input pin

and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.)

Whene ver LO S is inte rnally detec ted or an e xternal LOS is asserte d th ru the LOSEXT pin , the X RT91L32 wi ll

automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS

condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being

misinterpreted as valid incoming data.

FIGURE 6. EXTERNAL LOOP FILTERS

FIGURE 7. LOS DECLARATION CIRCUIT

CAP2NCAP1N

0.47uF

non-polarized

CAP2PCAP1P

0.47uF

non-polarized

Pin 66Pin 63 Pin 64 Pin 65

Inte rna l LOS De te c t

DLOSDIS

LOSEXT ( SD )

LO S D eclaration

xr XRT91L32

REV. 1.0.2 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

2.6 SONET Frame Boundary Detection and Byte Alignment Recovery

A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1

(0xF6 Hex ) b yt es foll owe d by thr ee co ns ecuti ve A2 (0x 28 Hex ) byt es . The d etec tor op erate s u nder th e c ontrol

of the OOF (Out of Fram e) signa ls provided from the S ONET F ramer. Detection is enable d when OOF is held

"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing

pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-to-

parallel con verter block uses the located byte boundary to assem ble the incoming data stream into bytes for

output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse

(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern

matching the framing pattern is detected on the incoming data stream. While in the pattern search and

detection s tate an d so lo ng is OO F i s ac tive , the fra me pul se ( FRA ME PUL SE ) output i s activ ate d f or on e byt e

clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/

STM-1) anytime a 48 -bit pattern ma tching th e framing pattern is dete cted on th e incoming data stream. O nce

the SONET F ramer Overhe ad Circuitry ha s verified tha t frame and byt e synchroni zation are co rrect, the OOF

input pin should be de-asserte d by the SONET Framer to disable the XRT91L32 frame search process from

trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L32’s framing pattern

detection is disab led upon the de-a ssertion of OOF inp ut pin fr om the SON ET Fram er, the by te bounda ry will

lock to the detected location and will remain locked to that location found when detection was previously

enabled.

2.7 Receive Serial Input to Parallel Output (SIPO)

During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps

parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L32 is operating in STS-3/

STM-1, the SI PO will conver t the 155.52 Mbps seria l data inp ut to 19 .44 Mbps par allel da ta outpu t. The SI PO

bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is

shown in Figure 8. XRT91L32 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.

FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO

b00b01b02b03

bn0bn1bn2bn3

bn+0bn+1bn+2bn+3

b70b71b72b73

8-bit Parallel LVTTL Output Data

RXDO0

RXDO7

RXDOn+

RXDOnRXIP/N

RXPCLKO

b30b

20b

10b

00b70b

60b

50b

40b33b

23b

13b43b53b63b73

SIPO

77.76 MH z (STS -12 / STM-4) or 19.44 MHz (S TS- 3/STM-1 )

622.08 M bps ST S-12/S TM -4 or

155.52 Mbps STS- 3/S TM-1 s eria l data rat e

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.2

2.8 Receive Parallel Output Interface

The 8-bit Single- E nded LVT TL r unn in g at 77. 76 M bps ( STS -12/S T M-4) o r 19.4 4 M bps (STS -3 /STM-1) parallel

data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered

clock. A simplified block diagram is shown in Figure 9.

2.9 Disable Parallel Receive Data Output Upon LOS

The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS

condition to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping

LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin "low" from the optical module

to force an LOS and mute the parallel receiver outputs as well (while DLOSDIS input is also low, see Figure 7.)

FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK

SONET Framer/ASIC

XRT91L32

STS-12/STM-4

STS-3/STM-1

Transceiver

RXPCLKO

RXDO[7:0]

xr XRT91L32

REV. 1.0.2 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

2.10 Receive Parallel Data Output Timing

The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and

hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows the PECL and TTL output timing

specifications.

FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING

TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)

TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)

SYMBOL PARAMETER MIN TYP MAX UNITS

tRXCLK Receive high-speed serial clock period 1.608 ns

tRXPCLKO Receive parallel data output byte clock period 12.86 ns

tRXDO_VALID Time the data is valid on RXDO[7:0] and FRAMEPULSE

before and after the rising edge of RXPCLKO 4ns

tPULSE_WID Pulse width of frame detection pulse on FRAMEPULSE 12.86 ns

SYMBOL PARAMETER MIN TYP MAX UNITS

tRXCLK Receive high-speed serial clock period 6.43 ns

tRXPCLKO Receive parallel data output byte clock period 51.44 ns

tRXDO_VALID Time the data is valid on RXDO[7:0] and FRAMEPULSE

before and after the rising edge of RXPCLKO 22 ns

tPULSE_WID Pulse width of frame detection pulse on FRAMEPULSE 51.44 ns

tRXCLK

RXPCLKO

RXDO[7:0]

RXIP

RXIN

FRAMEPULSE

tRXDO_VALID

tRXPCLKO

A1 A2 A2A2 A2

tPULSE_WID

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.2

TABLE 9: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION

SYMBOL PARAMETER MIN TYP MAX UNITS

tR_PECL PECL output rise time (20% to 80%) 350 ps

tF_PECL PECL output fall time (80% to 20%) 350 ps

tR_TTL TTL output rise time (10% to 90%) 2ns

tF_TTL TTL output fall time (90% to 10%) 1.5 ns

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

3.0 TRANSMIT SECTION

The tra nsmit secti on of the XRT91L 32 accep ts 8-bit parallel d ata and conve rts it to seria l Differ ential LVPECL

data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL

interface, Parallel-to-Serial Converter , a clock multiplier unit (CMU), a Low V oltage Positive-referenced Emitter-

Coupled Logic (L VPECL) differential line driver, and Loop Timing modes. The LVPECL serial data output rate is

622.08 Mbps for STS-12/STM-4 applications and 155.52 Mbps for STS-3/STM-1 applications. The high

frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In

order to synchronize the data transfer process, the synthesized 622.08 MHz for STS-12/STM-4 or 155.52 MHz

STS-3/STM-1 serial clock output is divided by eight and the 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/

STM-1) clock respectively is presented to the framer/mapper device to be used as its timing source.

3.1 Transmit Parallel Input Interface

The paralle l data from an framer /mappe r devi ce i s pres ented to the XRT91L32 through a n 8-bit Sing le-Ende d

LVT TL parallel bu s interface TXDI[7:0 ]. To directly in terface to the XRT91L32, the SONET Fr amer/ASIC m ust

be sync hronized to t he same tim ing source T XPCLK_IO in presenting data on the parall el bus inte rface. The

data must meet setup and hold times with respect to TXPCLK_IO. This clock output source is used to

synchronize the SONET Framer/ASIC to the XRT91L32. The framer/mapper device should use TXPCLK_IO

as its tim ing s ourc e s o that paral le l data is phase a ligne d with the s erial tr an sm it data. T he da ta is la tch ed int o

a parallel input register on the rising edge of TXPCLK_IO. TXPCLK_IO is derived from a divide-by-8 of the high

speed synthes ized clo ck res ulting in a 77.76/ 1 9.44 MHz Single- Ended LVTTL clo ck ou tput sou rce to be u sed

by the framer/mapper device for parallel bus synchronization. A simplified block diagram of the transmit

parallel bus clock out put system in terface is shown in Figure 11.

FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK

SONET Framer/ASIC

REFCLKP

TXPCLK_IO

TTLREFCLK

TXDI[7:0]

CMUREFSEL

REFCLKN

XRT91L32

STS-12/STM-4

STS-3/STM-1

Transceiver

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

3.2 Transmit Parallel Data Input Timing

When ap plying parall el data input to the tr ansmitt er, the se tup and hold ti mes should be followed as shown in

Figure 12 and Table 10, Table 11.

FIGURE 12. TRANSMIT PARALLEL INPUT TIMING

TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)

TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).

SYMBOL PARAMETER MIN TYP MAX UNITS

tTXPCLK_IO Transmit Clock Output peri od 12.86 ns

tTXDI_SU Transmit data setup time with respect to TXPCLK_IO 1.0 ns

tTXDI_HD Transmit data hold time with respect to TXPCLK_IO11.0 ns

SYMBOL PARAMETER MIN TYP MAX UNITS

tTXPCLK_IO Transmit Clock Output peri od 51.44 ns

tTXDI_SU Transmit data setup time with respect to TXPCLK_IO 1.0 ns

tTXDI_HD Transmit data hold time with respect to TXPCLK_IO11.0 ns

tTXPCLK_IO

TXDI[7:0]

TXPCLK_IO

tTXDI_HD

tTXDI_SU

Transmit Parallel Clock Output

Transmit Parallel

Clock driven by

XRT91L32 Device

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

3.3 Transmit Parallel Input to Serial Outpu t (PISO)

The PISO is used to conve rt 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/S TM-1 or

155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The

PISO bit i nterleaves parall el data input in to a serial bi t stream taking the fi rst bit from TXDI7, then the first bit

from TXDI6, and so on as shown in Figure 13.

3.4 Clock Multiplier Unit (CMU) and Re-Timer

The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-

12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential

LVP ECL inp ut REFC LKP/N acc epts a clock refer ence of 77.76 MHz or 19.44 MH z to synthes ize a high s peed

622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a

Differential LVPE CL clock source is not available, TTLR EFCLK can accept an LVTTL clock signal. The clock

synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK

reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a

frequenc y accur acy better than 20pp m in order for the tr ansmitted d ata rate fre quency t o have the n ecessary

accuracy required for SONET systems. If the TTLREFCLK reference clock is used, the TTLREFCLK

reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are

XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or

TTLREFCLK to ground. Table 1, on page 11 shows the CMU reference clock frequency settings. Table 12

specifies the Clock Multiplier Unit’s requirements for the referenc e clock.

TABLE 12: CLOCK MULTIPLIER UNIT REQUIREMETNS FOR REFERENCE CLOCK

FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO

NAME PARAMETER MIN TYP MAX UNITS

REFDUTY Reference clock duty cycle 40 60 %

REFJIT Reference clock jitter (rms) with 19.44 MHz refer ence15ps

REFJIT Reference clock jitter (rms) with 77.76 MHz refer ence113 ps

REFTOL Reference clock frequency tolerance2-20 +20 ppm

ECLKJIT STS-3/STM-1 Electrical Clock output jitter (rms) with 19.44 MHz reference 1mUIrms

ECLKJIT STS-12/STM-4 Electrical Clock output jitter (rms) with 19.44 MHz reference 5mUIrms

ECLKJIT STS-3/STM-1 Electrical Clock output jitter (rms) with 77.76 MHz reference 2mUIrms

b00b01b02b03b04b05b06b07

bn0bn1bn2bn3bn4bn5bn6bn7

bn+0bn+1bn+2bn+3bn+4bn+5bn+6bn+7

b70b71b72b73b74b75b76b77

8-bi t Pa r alle l LV TTL Inpu t Data

TXDI0

TXDI7

TXDIn+

TXDInTXOP/N

TXPCLK_IO 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)

622.08 Mbps STS-12/STM-4 or

155.52 Mbps STS-3/STM-1 serial data rate

b40b50

b60b70b20

b30

b47b57b67b77b37

PISO

time (0)

b27b

17b

07b10b00

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.

1These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms).

2Required to meet SONET output frequency stability requirements.

3.5 Loop Timing and Clock Control

Two types of loop timing are possible in the XRT91L32.

In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by

assert ing the LO OPTIME sign al to a hig h lev el . Whe n the lo op tim in g mode is activate d, the CMU synt he si ze d

hi-speed r eference clo ck input to the R etimer is repla ced with the hi- speed internal ly recovered receive clo ck

coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the

internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock.

In external loop timing mode, the XRT91L32 allows the user the flexibility of using an externally recovered

receiv e clock for reti ming the high s peed se rial data. Fi rst, the CDR DIS inpu t pin sh ould be set hig h. By d oing

so, the interna l CDR is disabled and by passed and the XRT91L32 will sampl e the incoming high speed serial

data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state,

the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L32 will

sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in

order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the

transmit serial data output stream TXOP/N.

Table 13 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip

CDR or an external recovered clock in loop timing applications is shown in Figure 14.

ECLKJIT STS-12/STM-4 Electrical Clock output jitter (rms) with 77.76 MHz reference 4mUIrms

OCLKFREQ Frequency output 620 624 MHz

OCYCDUTY Clock output duty cycle (’1010’ data pattern) 45 55 %

TABLE 13: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS

CDRDIS LOOPTIME TRANSMIT CLOCK SOURCE RECEIVE CLOCK SOURCE

0 0 Clock Multiplier Unit CDR Enabled.

Clock and Data recovery by internal CDR

0 1 Internal CDR CDR Enabled.

Clock and Data recovery by internal CDR

1 0 Clock Multiplier Unit

CDR Disabled.

Externally recovered Receive Clock from

XRXCLKIP/N

622.08/155.52 Mbps data on RXIP/N sampled at

rising edge of XRXCLKIP/N

1 1 External CDR thru XRXCLKIP/N

CDR Disabled.

Externally recovered Receive Clock from

XRXCLKIP/N

622.08/155.52 Mbps data on RXIP/N sampled at

rising edge of XRXCLKIP/N

NAME PARAMETER MIN TYP MAX UNITS

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

3.6 Transmit Serial Output Control

The 622.0 8 Mb ps STS- 12 /STM -4 or 155.52 Mbps STS -3/S T M-1 tr ans mit s er ia l output is avali abl e o n TXO P /N

pins. The transmit serial output can be AC or DC coupled to an optical module or electrical interface. A

simpli fied block di agram with int ernally AC-coup led SFP is show n in Figure 15. Also, refer to applicatio n note

TAN-9132.)

NOTE: Some optical modules integrate AC coupling capacitors within the module. AC or DC coupling is largely specific to

system design and optical module of choice.

FIGURE 14. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK

FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK

RXIP

RXIN

MUX

CDR

MUX

REFCLKP

REFCLKN

TTLREFCLK

CDRDIS

Div by 8

Clk

Data

XRT91L32

LOOPTIME XRXCLKIP

XRXCLKIN

DATA

PISO

to Retime r

SIPO

Retimer

TXOP

TXON

CLK

RXDO[7:0]

RXPCLKO

DATA

CLK

TXPCLK_IO

VDD

ENB

MUX

Div by

TXDI[7:0]

622.08/

155.52MHz

CMU

SFP, Optical Module

TXOP

TXON Optical Fibe

187 Oh m

Install close to 91L30

Internally AC coup led and

terminated into 100 Ohm

XRT91L32

STS-12/STM-4

STS-3/STM-1

Transceiver

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

4.0 DIAGNOSTIC FEATURES

4.1 Serial Remote Loopback

The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is

activated, the high-speed serial receive data from RXIP/N is presented at the high speed transmit output

TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input

of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to

parallel data and presented at the low-speed receive parallel interface RXDO[7:0]. The recovered receive clock

is also divided b y 8 and p resented at the low-spe ed clo ck output RX PCLKO to sy nchroni ze the tra nsfer of th e

8-bit received parallel data. A simplified block diagram of serial remote loopback is shown in Figure 16.

4.2 Digital Local Loopback

The digital local loopback is activated when the DLOOP signal is set "High." When digital local loopback is

activate d, the h igh-spe ed data fro m the o utput of the parallel to seri al co nver ter is l ooped b ack and presente d

to the hi gh-speed i nput of the receiver serial to parallel con verter. Th e CMU o utput is als o looped back to the

receive section and is used to synchronize the transfer of the data through the receiver. In Digital loopback

mode, the transmit data f rom th e transmit paralle l interface T XDI[7:0] is s erialized and pr esented to the high-

speed transmit output TXOP/N using the high-speed 622.08/155.52 MHz transmit clock generated from the

clock multiplier unit and p resented to t he input of the Reti mer and SIPO . A simpl ified block diagram of digital

loopba ck is shown in Figure 17. Receive Data mute up on LOS, as shown in Figure 7, applie s to Digital Local

Loopback Mode

FIGURE 16. SERIAL REMOTE LOOPBACK

FIGURE 17. DIGITAL LOCAL LOOPBACK

PISO Re-Timer LVPECL

Output Drivers

LVPECL

Input Drivers

CDR

SIPO

x P a ra lle l Ou tp u t

Tx Serial Outpu

Serial Rem ote Loopback

Rx S erial Inpu

PISO Re-Timer LVPECL

Output Drivers

LVPECL

Input Drivers

CDR

SIPO

x Para ll el Output

Tx S erial O utpu

Digital Loopback

Tx Pa r allel Inp u t

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

4.3 Analog Local Loopback

Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the

point where the transmit data is looped back is moved all the way back to the high-speed receive I/O. The

transmit data from the transmit parallel interface TXDI[7:0] is serialized and presented to the high-speed

transmit output TXOP/N using the high-speed 622.08/155.52 MHz transmit clock generated from the clock

multipli er unit. I n additio n, the high- speed transmit d ata TXOP/N is looped bac k to the receive c lock and data

recovery unit, replacing the RXIP/N. The signal is then processed by the CDR, and is sent through the serial to

parallel conv erter and presen ted at the low-spee d receive paral lel interface RXDO [7:0]. ALOOP is invoked by

assert ing the ALO O P pin "H igh ." A sim pli fi ed bl ock dia gr am of parall el r emo te lo opba ck is sho wn in Figure 18.

Receive data mute upon "LOS

4.4 Split Loopback

The serial remote loopback and the digital local loopback can be combined to form a split loopback. The

output of the parallel to serial converter is looped back and p resented t o the high- speed input o f the rece iver

serial to parallel converter. The high-speed serial receive data from RXIP/N is presented at the high speed

transmit output TXOP/N, and the high-speed recovered clock is selected to re-time the high speed transmit

data output. A simplified block diagram of parallel remote loopback is shown in Figure 19.

FIGURE 19. SPLIT LOOPBACK

FIGURE 18. ANALOG LOCAL LOOPBACK

PISO Re-Timer LVPECL

Outp ut Drivers

LVPECL

Input Drivers

CDRSIPO

Tx Parallel Input

x Parallel Output

Tx S erial Outpu

Analog Local Loop back

PISO Re-Timer LVPECL

Outp ut Drivers

LVPECL

Input Drivers

CDR

SIPO

Tx P a ra lle l In pu t

x Parallel Output

Tx S erial Outpu

Split Loopback

Rx Se rial Inpu

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

4.5 Eye Diagram

The XRT91L32 Eye diagram illustrates the transmit serial output signal integrity and quality.

FIGURE 20. STS-3/ST M -1 EYE DIAGRAM

FIGURE 21. STS-12/STM-4 EYE DIAGRAM

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

4.6 SONET Jitter Requirements

SONET equipment jitter requirements are specified for the following three types of jitter . The definitions of each

of these types of jitter are given below. SONET equipment jitter requirements are specified for the following

three types of jitter.

4.6.1 Jitter To le ranc e:

Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input OC-N

equipment interface that causes an equivalent 1dB optical power penalty. OC-1/STS-1, OC-3/STS-3, OC-12

and OC-48 category II SONET interfaces should tolerate, the input jitter applied according to the mask of

Figure 22, with the corresponding parameters specified in the figure.

FIGURE 22. JITTER TOLERANCE MASK

OC-N/STS-N LEVEL

F0 (HZ)

F1 (HZ)

600

F2 (HZ)

300

6000

F3 (HZ)

6.5K

25K

100K

F4 (HZ)

20K

65K

250K

1000K

A1 (UIPP)

0.15

A2 (UIPP)

1.5

A3 (UIPP)

Input

Jitter

Amplitude

(UIpp)

f0f1f2f3f4

slop e= -20dB/decade

slope= -20 dB/decade

Jitter Frequency (Hz)

300

6.5K

25K

65K

250K

0.15

1.5

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

FIGURE 23. XRT91L32 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4

FIGURE 24. XRT91L32 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3 / ST M-1

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

4.6.2 Jitter Generation

Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The

Bellcore and ITU requirement for this type jitter is 0.01UI rms measured with a specific band-pass filter.

For more in formation on these specifi cations re fer to Bellcore TR -NWT-0 00253 sect ions 5.6.2-5 an d GR-253-

CORE secti on 5.6.

Phase noise plot shows the power of the noise with respect to the carrier power. When this curve is integrated

in the frequency band of in terest, the outcome is the noise power. Jitter generation in rms is then derived by

factoring with the appropriate period for the clock cycle.

FIGURE 25. XRT91L32 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 622.08 MBPS

STS-12/STM4 USING ’1010’ OUTPUT PATTERN

Phase Noise Transmit Jitter Generation

(Wide Band ) usi n g HP 8560E

-120

-115

-110

-105

-100

-95

-90

1 10 100 1000 10000 100000

Fre quency (kHz )

dBC/Hz

REF CLK = 19. 44 M Hz

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

5.0 ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without

causin g pe rma nent dama ge. F unc tio na lity at o r abo ve the v al ues li ste d is not imp li ed. Ex po sure to thes e v alu es for

extended periods will severe ly affect device reliability.

Thermal Resistance of QFP Package........ΘjA = 45°C/W Operating Temperature Range ..... ...... ......-40°C to 85°C

Thermal Resistance of QFP Package........ΘjC = 12°C/W Case Temperature under bias..................-55°C to 125°C

ESD Protection (HBM)..........................................>2000V Storage Temperature ...............................-65°C to 150°C

ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS

SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS

VDD3.3 CMOS Digital Power Supply -0.5 6.0 V

VDDLVPECL PECL I/O Power Supply -0.5 6.0 V

AVDD_IO 3.3V Analog I/O and Power Supply -0.5 6.0 V

LVPECL DC logic signal input voltage -0.5 VDDLVPECL +0.5 V

LVTTL DC logic signal input voltage -0.5 5.5 V

LVTTL DC logic signal output voltage -0.5 VDD3.3 +0.5 V

LVPECL Input current -100 100 mA

LVTTL Input current -100 100 mA

POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS

Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified

SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

VDD3.3 Power Supply Voltage 3.135 3.3 3.465 V

AVDD3.3 Transmit Power Supply Voltage (AVDD3.3_TX) 3.135 3.3 3.465 V

AVDD3.3 Receiver Power Supply Voltage (AVDD3.3_RX) 3.135 3.3 3.465 V

VDD

LVPECL PECL I/O Power Supply Voltage 3.135 3.3 3.465 V

IDD-OC3 Total Power Supply Current 200 mA

IDD-OC12 Total Power Supply Current 242 mA

PDD-OC3 Total Power Consumption 660 mW

PDD-OC12 Total Power Consumption 800 mW

xr XRT91L32

REV. 1.0.3 STS-12/STM-4 OR STS-3 /ST M-1 SONET/SDH TRANSCEIVER

LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS

Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified

SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS

VOH LVPECL Output High Voltage VDDLVPECL

- 0.9 V

VOL LVPECL Output Low Voltage 0.7 V

VOCOMM LVPECL Output C om mo n M ode Voltage 1.1 VDDLVPECL

- 1.3 V

VODIFF LVPECL Output Differential Voltage 600 1300 mV Terminate with

50Ω to

VDDLVPECL- 2.0

VIH LVPECL Input High Voltage VDDLVPECL

- 0.9 VDDLVPECL

- 0.3 VFor

Single-Ended

VIL LVPECL Input Low Voltag e 0VDDLVPECL

- 1.72 VFor

Single-Ended

VIDIFF LVPECL Input PECL Differential V oltage 400 1600 mV

VICOMM LVPECL Input PECL Common Mode

Voltage 2.0 V

VOH LVTTL Output High Voltage 2.0 V IOH = -18.0mA

at VOH=2.4V

VOL LVTTL Output Low Voltage 00.8 V IOL = 15.0mA

at VOL=0.4V

VIH LVTTL Input High Voltage 2.0 V

VIL LVTTL Input Low Voltage 00.8 V

IIH LVTTL Input High Current 50 500 μA2.0V<VIN<5.5V

VIN=2.4V typical

IIL LVTTL Input Low Current -500 μA-0.5V<VIN<0.8V

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

PACKAGE DIMENSIONS

ORDERING INFORMATION

PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT91L32IQ-F 100-pin Plastic Quad Flat Pack (14.0 x 20.0 x 2.7 mm3, QFP) -40°C to +85°C

80 51

130

100

eating Plane L

(14 x 20 x 2.7 m m , QFP , 1.6m m form )

Rev. 1.00

(Pin 1 feature is mfger option

)

SYMBOLMINMAXMINMAX

A 0.102 0.134 2.60 3.40

A1 0.010 0.020 0.25 0.50

A2 0.100 0.120 2.55 3.05

B 0.009 0.015 0.22 0.38

C 0.005 0.009 0.13 0.23

D 0.904 0.923 22.95 23.45

D1 0.783 0.791 19.90 20.10

E 0.667 0.687 16.95 17.45

E1 0.547 0.555 13.90 14.10

e 0.0256 BSC 0.65 BSC

L 0.029 0.040 0.73 1.03

α0° 7° 0° 7°

MILLIMETERSINCHES

Note: The control dimension is the millimeter column

1.6mm form

XRT91L32 xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIV E R REV. 1.0.3

NOTICE

EXAR Co rporation r eserve s the right to ma ke chan ges to the products contained in th is publ ication i n order t o

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purpose s and m ay var y de pendin g upon a us er’s s pecif ic appl icati on. W hile the in forma tion i n thi s pub lica tion

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunctio n of the product ca n reasona bly be expecte d to cause fai lure of the life s upport syst em or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporatio n receive s, in writi ng, assuran ces to i ts satisfac tion that: (a) the ris k of inju ry or dam age has

been m inimized; (b) the user as sumes al l such risks ; (c) poten tial liabi lity of EXA R Corporation is adequate ly

protected under the circumstances.

Datasheet November 2006.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

REVISION HISTORY

REVISION # DATE DESCRIPTION

1.0.0 November 2006 XRT91L32 datasheet release version.

1.0.1 11/07/06 correct typo errors

1.0.2 11/08/06 Added Min Reset pulse width of 100nS in pin description, correct typo errors.

1.0.3 06/14/07 Corrected Figure 3 to portray an applic ati on w ith AC-co upl ed SFP

Corrected the serial data bit order in Figure 13

Made pin 81 VDD only

Minor editorial corrections