CK49X-497024 - Cirrus Logic Inc

DS752PP8

High Definition Audio Decoder DSP

Family with Dual 32-bit DSP Engine Technology

CS4970x4 Data Sheet

http://www.cirrus.com

FEATURES

Multi-standard 3 2-bit High Definition Audio Decoding plus

Post-Processing

Supports high-definition audio formats including:

— Dolby D i git a l® Plus

—Dolby

® TrueHD

—DTS-HD

® High Resolution Audio

—DTS-HD

® Master Audio

— DTS Express™

Additional Applications Library

— Dolby D i git a l® EX, Dolby® Pro Logic® IIz, Dolby

Headphone 2®, Dolby® Virtual Speaker 2®, Audistry®

— DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Disc rete 7 .1, DT S-

ES™ Matrix 6.1, DTS Neo:6®, DTS Neural S urr oun d™

—DSD

— MPEG-2 AAC™ LC 5.1

—SRS

® CS2®, SRS T ruVolume™, SRS® TruSurround

HD4™, WOW HD™,

—THX

® Ultra2™, THX® ReEQ™

— Thomson MP3 Surround

— Audyssey 2EQ™ Module

Cirrus Logic’s Applications Library

— Cirrus Original Multi-Channel Surro und 2 (COMS2),

Cirrus Band Xpander™, Cirrus Virtualization Technology,

Cirrus Intelligent Room Calibration 2 (IRC2)

— Crossba r Mixe r, Signal Gen e rat o r

— Advanced Post-Processors including: 7.1 Bass Manager,

Tone Control, 11- Band Parametric EQ, Delay, 2:1/4:1

Decimator, 1:2/1:4 Upsampler

Up to 12 Channels of 32-bit Serial Audio Input

Customer Software Security Keys

16 Ch x 32-bi t P CM O ut w i th Du al 19 2 kHz SPDIF T x

Two SPI™/I2C™ ports

One Parallel Port (144-pin LQFP package only)

Large On-chip X, Y, and Program RAM & ROM

SDRAM and Serial Flash Memory Support

The CS4970x4 DSP family is an enhanced version of the

CS4953x DSP family with higher overall performance. In

addition to all the mainstream audio processing codes in on-

chip ROM that the CS4953x DSP offers, the CS4970x4 device

family also supports the decoding of major high-definition

audio fo rmats . Add iti on al ly, th e CS49 70 x4, a dual-c ore d evice,

performs the high-definition audio decoding on the first core,

leaving the second core av ailable for au dio post-pro cessing and

audio enhancement. The CS4970x4 device supports the most

demanding audio post processing requirements. It provides an

easy upgrade path to systems currently using the CS495xx or

CS4953x device with minor hardware and software changes.

Ordering Information

See page 28 for ordering information.

Coyo t e 32- b it

DSP A

Coyote 32-bit

DSP B

Ext. Mem ory Control ler

S/PDIF X Y P X Y

Serial

Control 1

16 Ch PCM

Audio Out

Serial

Control 2 Parallel

Control GPIO Debug

STC

TMR1

TMR2

PLL

S/PDIF

12 Ch. Audio In /

6 Ch. SACD In

Preliminary Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Table of Contents

1. Documentation Str ategy ...................... ..... ..... .............. .... ..... .............. ..... .... .............. ..... ...............4

2. Overv iew .................... ..... .............. ..... .... .............. ..... .............. ..... .............. .... ..... .............. ..... ..... .....4

2.1 Migrating from the CS495xx(2) to the CS4970x4 ........................................................................................... 6

2.2 Licensing ......................................................................................................................................................... 6

3. Code Ove rlay s ................ ..... .... .............. ..... ..... .............. .... .............. ..... ..... .............. .... ....................6

4. Hardware Functional Desc ription ....... .............. ..... ..... .............. .... ..... .............. ..... .... ..... .......... .....7

4.1 Coyote DSP Core ........................................................................................................................................... 7

4.1.1 DSP Memory ...................................................................................................................................... 7

4.1.2 DMA Controller ................................................................................................................................... 7

4.2 On-chip DSP Peripherals ................................................................................................................................ 7

4.2.1 Digital Audio Input Port (DAI) ............................................................................................................. 7

4.2.2 Digital Audio Output Port (DAO) ........................................................................................................ 8

4.2.3 Serial Control Port 1 & 2 (I2C™ or SPI™) ........................................................................................... 8

4.2.4 Parallel Control Port ........................................................................................................................... 8

4.2.5 External Memory Interface ................................................................................................................. 8

4.2.6 GPIO .................................................................................................................................................. 8

4.2.7 PLL-based Clock Generator ............................................................................................................... 8

4.3 DSP I/O Description ........................................................................................................................................ 8

4.3.1 Multiplexed Pins ................................................................................................................................. 8

4.3.2 Termination Requirements ................................................................................................................. 8

4.3.3 Pads ...................................................................................................................................................9

4.4 Application Code Security ............................................................................................................................... 9

5. Character istic s a nd Speci fi cations . .............. .... ..... .............. ..... .............. .... .............. ..... ..... .... ....10

5.1 Absolute Maximum Ratings .......................................................................................................................... 10

5.2 Recommended Operating Conditions ........................................................................................................... 10

5.3 Digital DC Characteristics ............................................................................................................................. 10

5.4 Power Supply Characteristics ........................................................................................................................11

5.5 Thermal Data (144-Pin LQFP) .......................................................................................................................11

5.6 Thermal Data (128-pin LQFP) .......................................................................................................................11

5.7 Switching Characteristics— RESET# ........................................................................................................... 12

5.8 Switching Characteristics — XTI .................................................................................................................. 12

5.9 Switching Characteristics — Internal Clock .................................................................................................. 13

5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode ............................................................ 13

5.11 Switching Characteristics — Serial Control Port - SPI Master Mode .......................................................... 14

5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode ............................................................ 15

5.13 Switching Characteristics — Serial Control Port - I2C Master Mode .......................................................... 16

5.14 Switching Characteristics — Parallel Control Port - Inte® Slave Mode ...................................................... 17

5.15 Switching Characteristics — Paral lel Control Port - Motorola® Slave Mode .............................................19

5.16 Switching Characteristics — Digital Audio Slave Input Port ....................................................................... 21

5.17 Switching Characteristics — DSD® Serial Input Port ............. .......................................................... .......... 22

5.18 Switching Characteristics — Digital Audio Output Port ............................................................................... 23

5.19 Switching Characteristics — SDRAM Interface .......................................................................................... 24

6. Ordering Informa ti on ........................ .... ..... .............. ..... .... .............. ..... .............. ..... .... ..................28

7. Environmental, Manufacturing, and Handling Informa tion ............................... .... ..... ..... ..... ...28

8. Device Pi n-O ut Diag ram .............. ..... .... .............. ..... .............. ..... .... .............. ..... .............. .............29

8.1 128-Pin LQFP Pin-Out Diagram................................................................................................................... 29

8.2 144-Pin LQFP Pin-Out Diagram.................................................................................................................. 30

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

9. Pack age Me cha n ica l Draw ings ...... ..... .............. ..... .............. .... .............. ..... .............. ..... .......... ....31

9.1 128-Pin LQFP Package Drawing ..................................................................................................................31

9.2 144-Pin LQFP Package Drawing ..................................................................................................................32

10. Revision His tory ................... .............. ..... .............. .... ..... .............. ..... .............. .... ..... ... ................33

List of Figures

Figure 1. RESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 2. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 3. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 4. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 5. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 6. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 12. DSD Serial Audio Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13. Digital Audio Port Output Timing Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 15. External Memory Interface - SDRAM Burst Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 16. External Memory Interface - SDRAM Burst Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 19. 128-Pin LQFP Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20. 144-Pin LQFP Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 21. 128-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 22. 144-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

List of Tables

Table 1. CS4970x4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. CS4970x4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 5. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

1. Documentation Strategy

The CS4970x 4 da ta she et des cr ibe s t he CS4970x4 f amil y of mul ti cha nne l a udi o decoders . Thi s d ocume nt s hould be

used in conjunction with the following documents when evaluating or designing a system around the CS4970x4

family of pr ocessors.

The scope of the CS4970x4 Data Sheet is primarily the hardware specifications of the CS4970x4 family of devices.

This includes hardware functionality, characteristic data, pinout, and packaging information.

The intended aud ien ce for the CS497 0x4 Data Sheet is the sy st em PCB designe r, MCU programmer, and th e qualit y

control engi neer.

2. Overvi ew

The CS4970x4 DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms,

enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a broad

array of digital interface products and audio converters to meet your audio system-level design requirements.

The CS4970x4 is avai lable in 14 4-pi n and 128-pin LQFP packag es. The audi o pro cessing fe atu re s of th e CS4970x4

product family are a superset of audio features available in the CS4953xx product family.

Please refer to Table 2 on page 5 for the speed and firmware features of CS4970x4 product family.

Table 1. CS4970x4 Related Documentation

Document Name Description

CS4970x4 Data Sheet This document

CS4953x4/CS4970x4 System Designer’s Guide

A new consolidated documentation set that includes:

• Detailed system de sign information including

Typical Connection Diagrams, B oot-Procedures, Pin

Descriptions, Etc. Also describes use of DSP

Condenser tool.

• Detailed firmware design information including

signal processing flow diagrams and control API

information

AN288 - C S49 53 xx/CS4 97xxx Firmwa re Us er’s Manual Includes detailed firmware design information

including signal processing flow diagrams and

control API infor mat ion

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Table 2. Device and Firmware Selection Guide

Device Dec ode Pro ces sor

(DSP-A)1Matrix-processor

(DSP-A)1

1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.

Virtualizer-processor

(DSP-B)1Post-processor

(DSP-B1

CS497014

300 MIPS

Stereo PCM

(4:1/2:1 Down-sampling and

1:2/1:4 Up-sampling Options )2

Multi-Chann el PCM

(4:1/2:1 Down-sampling and

1:2/1:4 Up-sampling Options )2

Dolby Digital

MPEG-2 AAC LC 5.1

Dolby Digital Plus

Dolby TrueHD

2. Downsamplin g and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also available as

a separate post-processing module that is described in the application note, AN288PPI.

Dolby PLIIz

SRS Circle Surround II

(Stereo In)

Cirrus Original Multi-Channel

Surrou nd (Effects / Rever b

Processor)

Crossbar (Down-mix / Up-

mix)

(Simultaneous Process)

Dolby Headphone 2

Dolby Virtual Speaker 2

SRS TruVolume

APP

(Advanced Post-processing)

–Tone Control

–Re-EQ

–PEQ (up to 11 Bands)

–Delay

(Speaker to Listening

Position Ali gnm ent

and/or Lip Sync)

–7.1 Bass Manager

–Audio Manager

–4:1/2;1 Down-

sampling2

SRS TruSurround HD4,

WOW HD

CS497004

300 MIPS

CS497024

300 MIPS

Same as CS49014 +

DTS, DTS-ES, DTS96/24

DTS-HD Master Audio

DTS-HD High Resolution Audio

DTS Express

Same as CS49014 +

DTS Neo:6

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

2.1 Migrating from the CS495xx(2) to the CS4970x4

The CS4970x4 was designed to provide an easy upgrade path from the CS495xx & CS4953x. Although 144-pin

versions of the two devices are virtually identical with respect to external system connection, there are some small

differences the hardware designer should be aware of:

• The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx.

• The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx.

• The CS4970x4 adds support for 6-channel DSD input.

• The CS4970x4 adds support for TDM mode on both audio input and output ports.

• The CS4970x4 does not support external SRAM operation.

• The CS4970x4 external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the

CS495xx. Some firmware modules also support a 75 MHz CS4970x4 SDRAM bus speed. Please refer to

AN304 for details.

• The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.

2.2 Licensing

Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the

application notes. Please con tact your local Cirrus Sale s representative for more information.

3. Code Overlays

The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of

overlays. The overlays have been divided into three main groups called Decoders, Matrix-processors, and Post-

processors. All software components are defined in the following list:

•OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,

processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc.

•Decoders - Any Module that i nitially w rites data into th e audio I/O buffers, e.g. AC-3™, DTS, PCM, etc. All

the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data via

I2S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc.

•Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-

processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer

through proces ses like Virtuali zation ( nÖ2 cha nnels) o r Matrix Decodi ng (2Ön channels). Examples are Dolby

ProLogic IIx and DTS Neo:6.

• Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels

(nÖ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that

were eli mina te d. Exa mp le s ar e Do lby Head phone® 2 and Dolby Virtual Spe ake r® 2. Generall y s pea king, thes e

modules reduce the number of valid channels in the audio I/O buffer.

•Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Matrix-Processors.

Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby

Headphone/Virtual Speaker, etc.

The overlay stru cture r educes the ti me req uired to reco nfigur e the DSP whe n a proce ssing c hange i s reque ste d. Each

overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is

selected, the OS, matrix-, and post-processors do not need to be reloaded — only the new decoder (the same is true

for the other overlays).

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

4. Hardware Functional Description

4.1 Coyote DSP Core

The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core is a

high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply

accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data

registers, and 12 index registers.

Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such

as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all

with out t he inte rventi on of the DS P. The D MA e ngine offloads data move instru ction s from the DS P core , le aving

more MIPS available for signal processing instructions.

CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to the

CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio decoder and

post-processor modules which are available from Cirrus Logic.

The CS4970x4 is sui table for Audio Decoder, Audio Post- proces sor, Audio Encoder, DVD Audio/Video Player, and

Digital Broadcast Decoder appl icatio ns.

4.1.1 DSP Memory

Each DSP cor e has it s own on-c hip dat a and pr ogram RAM and ROM and does not requi re exte rnal memor y for a ny

of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and

THX Ultra2. However, if the end-system design requires support of the new high-definition audio formats, external

SDRAM will be needed to support Dolby TrueHD and DTS-HD Master Audio.

The memory maps for the DSP s are as follows. All memory sizes are com posed of 32-bit words.

4.1.2 DMA Controller

The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own

arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the

peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment

controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting

PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and

internally converted to PCM befo re proc ess in g. Addit ionally support is provi de d for audi o dat a i nput to t he DSP vi a

the DAI from an HDMI receiver.

Table 3. CS4970x4 DSP Memory Sizes

Memory

Type DSP A DSP B

X 16k SRAM, 32k ROM 10k SRAM, 8k ROM

Y 24k SRAM, 32k ROM 16k SRAM, 16k ROM

P 8k SRAM, 32k ROM 8k SRAM, 24k ROM

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock

domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads

the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be

sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates

from 32 kHz to 192 kHz. Each por t can be configured as an inde pend ent cloc k domai n in sl ave mode, or th e rat i o of

the two clocks can be set to eve n multi pl es of each ot her in maste r mode. The two port s can also be ganged together

into a si ngle c lock doma in. Each por t has on e seri al aud io pin tha t can b e confi gured a s a 192 k Hz SPDIF trans mitte r

(data with embedded clock on a single line).

4.2.3 Serial Contr ol Port 1 & 2 (I2C™ or SPI™)

There are t wo on-c hip ser ial co ntrol port s that are cap able of oper ating as master or slav e in eit her I 2C or SPI modes.

SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50

MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults

to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control.

4.2.4 Parallel Control Port

The CS4970x4 parallel port supports both Motorola® and Inte l® interfaces. It can be used for both control and data

delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package.

4.2.5 External Memory Int erface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.

4.2.6 GPIO

Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an

input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low,

or active-high.

4.2.7 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the

DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the

DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference frequency

and can be switched to use the PLL output after overlays have been loaded and configured, either through master

boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is

provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3 DSP I/O Description

4.3.1 Multipl exed Pins

Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4

System Des i gner’s G uide.

4.3.2 Termination Requirements

Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4 System

Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper

operation.

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed

explanation of termination requirements for each communication mode select pin can be found in the CS4970x4

System Designer’s Guide.

4.3.3 Pads

The CS4970x4 I/O operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The externa l pr ogr am code may be encryp ted by the programmer to pr ot ect any i nte ll ec tual prope rt y it may cont ai n.

A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5. Characteristics and Specifications

Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet

typical para meters are measured und er the following conditio ns: T = 25 °C, CL = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V,

GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)

Caution: Operation at or beyon d these limits may result in perman ent damage to the d evice. Normal operation is not guaran teed at

these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltag e s with resp ect to 0 V)

Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.)

Parameter Symbol Min Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

–0.3

2.0

3.6

0.3

Input pin current, any pin except supplies Iin -+/- 10mA

Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V

Input voltage on I/O pins Vinio -0.3 5.0 V

Storage temperature Tstg –65 150 °C

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

1.71

3.13

1.8

3.3

1.89

3.46

Ambient operating temperature Commercial Grade (CQZ/CVZ) TA0 +25 + 70

°C

Parameter Symbol Min Typ Max Unit

High-level input vol ta ge VIH 2.0 - - V

Low-level input voltage, except XTI VIL --0.8V

Low-level input voltage, XTI VILXTI --0.6V

Input Hysteresis Vhys 0.4 V

High-level output voltage (IO = -4mA), except XTI,

SDRAM pins VOH VDDIO * 0.9 - - V

Low-level output voltag e (IO = 4mA), except XTI,

SDRAM pins VOL - - VDDIO * 0.1 V

SDRAM High-level output voltage (IO = -8mA) VOH VDDIO * 0.9 - - V

SDRAM Low-lev el output voltage (IO = 8mA) VOL - - VDDIO * 0.1 V

Input leakage current (all digit al pins with internal pull-

up resistors disabled) IIN --5μA

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.4 Power Supply Characteristics

(Measurements performed und e r ope rati ng cond itions.)

5.5 Thermal Data (144-Pin LQFP)

5.6 Thermal Data (128-pin LQFP)

Notes: 1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top and bottom

layers.

2.Four -layer boar d is sp ecified as a 7 6 mm X 11 4 mm, 1. 6 mm thick FR-4 ma terial with 1-o z cop per coverin g 2 0% of the

top and bottom layers and 0.5-oz copper covering 90% of the internal power plane and ground plane layers.

3.To calculate the die temperature for a given power dissipation

Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]

4.To calculate the case temperature for a given power dissipation

Τc = Τj - [ (Power Dissipation in Watts) * ψjt ]

Input leakage current (all digit al pins with internal pull-

up resistors enabled, and XTI) IIN-PU --70μA

Parameter Min Typ Max Unit

Power supply curr ent:

Core and I/O operating: VDD1

PLL op erating: VDDA

With external memory and most ports operating: VDDIO

1.Dependent on application firmware and DSP clock speed.

500

3.5

120

Parameter Symbol Min Typ Max Unit

Thermal Resistance (Junction to Ambient) Two-layer Board1

Four-layer Board2

θja -

-48

40 -

°C / Watt

Thermal Resistance (Junction to To p of Package)

Two-layer Board1

Four-layer Board2

ψjt -

-.39

.33 -

°C / Watt

Parameter Symbol Min Typ Max Unit

Thermal Resistance (Junction to Ambient) Two-layer Board1

Four-layer Board2

θja -

-53

44 -

°C / Watt

Thermal Resistance (Junction to To p of Package)

Two-layer Board1

Four-layer Board2

ψjt -

-.45

.39 -

°C / Watt

Parameter Symbol Min Typ Max Unit

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.7 Switching Characte ristics— RESE T#

Figure 1. RESET# Timing

5.8 Switching Characteristics — XTI

Figu re 2. XTI Timing

Parameter Symbol Min Max Unit

RESET# minimum pulse width low Trstl 1-μs

All bidirectional pins high-Z after RESET# low Trst2z -100ns

Configuration pins setup before RESET# high Trstsu 50 - ns

Configurati on pins h old after RESET# high Trsthld 20 - ns

Parameter Symbol Min Max Unit

External Crystal operating frequency1

1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz.

Fxtal 12.288 24.576 MHz

XTI period Tclki 41 81.4 ns

XTI high time Tclkih 16.4 - ns

XTI low time Tclkil 16.4 - ns

External Crystal Load Capacitance (parallel re so nant)2

2. CL refers to the total load capacitance as spe cified by the crystal manufacturer. Crystals which requir e a CL outsi de

this range should be avoided. The crystal oscillator circuit design sh ould follow the crystal man ufactu r er’s

recommendation for load capacitor selection.

CL10 18 pF

External Crystal Equivalent Series Re sistance ESR 50 Ω

RESET#

Trst2z

Trstl

Trstsu Trsthld

HS[3:0]

All Bidirectional

Pins

tclkih tclkil

Tclki

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.9 Switching Characte ristics — Inter n al Clock

5.10 Swi tching Characteristics — Serial Control Port - SPI Slave Mode

Parameter Symbol Min Max Unit

Internal DCLK frequency1

CS497004-CQZ

CS497004-CQZR

CS497024-CVZ

CS497024-CVZR

CS497024-CVZ

CS497024-CVZR

1.After in itia l p ow er- on re se t, Fdclk = Fxtal. After init ial kick st art c om m and s, the PLL is locked to m ax F dclk and re ma ins

locked until the next power-on reset.

Fdclk Fxtal 150 MHz

Internal DCLK period1

CS497004-CQZ

CS497004-CQZR

CS497024-CVZ

CS497024-CVZR

CS497024-CVZ

CS497024-CVZR

DCLKP 6.7 1/Fxtal

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application. Flow control

using the SCP_BSY# pin should be implemented to prevent over fl ow of the input d ata buffer.At b oot th e

maximum speed is Fxtal/3.

fspisck -25MHz

SCP_CS# falling to SCP_CLK rising tspicss 24 - ns

SCP_CLK low time tspickl 20 - ns

SCP_CLK high time tspickh 20 - ns

Setup time SC P_MOSI input tspidsu 5-ns

Hold time SC P_MOSI input tspidh 5-ns

SCP_CLK low to SCP_MISO output valid tspidov -11ns

SCP_CLK falling to SCP_IRQ# rising tspiirqh -20ns

SCP_CS# ris in g to SCP_IRQ# falling tspiirql 0ns

SCP_CLK low to SCP_CS# rising tspicsh 24 - ns

SCP_CS# rising to SCP_MISO output high-Z tspicsdz -20 ns

SCP_CLK rising to SCP_BSY# falling tspicbsyl -3

*DCLKP+20 ns

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 3. Serial Control Port - SPI Slave Mode Timing

5.11 Sw itching Characte ristics — Serial Control Port - SPI Master Mode

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1, 2

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the

actual maximum speed of the communication port may be limited by the firmware application.

2. See Section 5.8.

3. SCP_CLK P ERI O D r efers t o t he per i od o f SC P _CLK as bei ng used in a given appl ication. It do es not refer to a tested

parameter.

fspisck -F

xtal/2 MHz

SCP_CS# falling to SCP_CLK rising 3tspicss -11*DCLKP +

(SCP_CLK PERIO D )/2 -ns

SCP_CLK low time tspickl 18 - ns

SCP_CLK high time tspickh 18 - ns

Setup time SC P_MISO input tspidsu 11 - ns

Hold time SC P_ MIS O inpu t tspidh 5-ns

SCP_CLK low to SCP_MOSI output vali d tspidov -11ns

SCP_CL K low to SCP_CS # falling tspicsl 7-ns

SCP_CLK low to SCP_CS# rising tspicsh -11*DCLKP +

(SCP_CLK PERIO D )/2 -ns

Bus free time between active SCP_CS# tspicsx 3*DCLKP - ns

SCP_CLK falling to SCP_MOSI output high-Z tspidz -20ns

SCP_BSY#

CP_CS#

SCP_CLK

SCP_MOSI

SCP_MISO

SCP_IRQ#

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspibsyl

tspiirql

tspiirqh

fspisck

tspicsdz

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 4. Serial Control Port - SPI Master Mode Timing

5.12 Swi tching Characteristics — Ser ial Cont rol Port - I2C Slave Mode

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application. Flow control

using the SCP_BSY# pin s hould be implemen ted to prevent overflow of the input data buffer.

fiicck - 400 kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_CLK high time tiicckh 1.25 - µs

SCP_SCK rising to SCP_SDA rising or falling for START

or STOP condition tiicckcmd 1.25 µs

START cond ition to SCP_ CLK falling tiicstscl 1.25 - µs

SCP_CLK fal ling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SC P_SDA input valid to SCP_CLK ris ing tiicsu 100 ns

Hold time SC P_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

SCP_CLK falling to SCP_IRQ# rising tiicirqh -3

*DCLKP + 40 ns

NAK condition to SCP_IRQ# low tiicirql 3*DCLKP + 20 ns

SCP_CLK rising to SCB_BSY# low tiicbsyl -3

*DCLKP + 20 ns

EE_CS#

SCP_CLK

CP_MISO

CP_MOSI

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspicsx

fspisck

tspidz

tspicsl

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 5. Serial Control Port - I2C Slave Mode Timing

5.13 Swi tching Characteristics — Ser ial Cont rol Port - I2C Master Mode

Parameter Symbol Min Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

fiicck - 400 kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_CLK high time tiicckh 1.25 - µs

SCP_SC K r isi ng t o S CP_SD A r ising o r fal ling for S TART or STOP

condition tiicckcmd 1.25 µs

START cond ition to SCP_ CLK falling tiicstscl 1.25 - µs

SCP_CLK fal ling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SC P_SDA input valid to SCP_CLK ris ing tiicsu 100 ns

Hold time SC P_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -36ns

CP_BSY#

SCP_CLK

SCP_SDA

SCP_IRQ#

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

tiicirqh tiicirql

ACK

MSB

tiicstp

tiiccbsyl

tiicdov tiicb

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 6. Serial Control Port - I2C Master Mode Timing

5.14 Swi tching Characteristics — Parallel Control Port - Intel® Slave Mode

Parameter Symbol Min Typical Max Unit

Address setup before PCP_CS# and PCP_RD# low or PCP_CS#

and PCP_ WR# low tias 5-ns

Address hold time after PCP_CS# and PCP_RD# low or PCP_CS#

and PCP_ WR# high tiah 5-ns

Read

Delay b e tween PCP_RD# then PCP_CS# low or PCP_CS# then

PCP_ RD # low ticdr 0-ns

Data valid after PCP_CS# and PCP_RD# low tidd -18ns

PCP_CS# and PCP_RD# low for read tirpw 24 - ns

Data ho ld time after PCP_CS# or PCP_RD# h i gh tidhr 8-ns

Dat a high-Z after PCP_C S # or PCP_RD# high tidis -18ns

PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for

next read1tird 30 - ns

PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for

next write1tirdtw 30 - ns

PCP_RD# rising to PCP_IRQ# rising tirdirqhl -12ns

Write

Delay between PCP_WR# then PCP_CS# low or PCP_CS# then

PCP_WR# low ticdw 0-ns

Data setup before PCP_CS# or PCP_WR# high tidsu 8-ns

PCP_CS# and PC P_WR# low for write tiwpw 24 - ns

Data hold after PCP_CS# or PCP_WR# high tidhw 8-ns

PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for

next read1tiwtrd 30 - ns

PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for

next write1tiwd 30 - ns

PCP_WR# rising to PCP_BSY# falling tiwrbsyl -2*DCLKP + 20-ns

CP_CLK

CP_SDA

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

ACK

MSB

tiicstp

tiicdov tiicb

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 7. Parallel Control Port - Intel® Slave Mode R e ad Cycl e

Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle

1. The system designer should be aware that the actual maximum speed of the communication port may be limited

by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent

overflow ing the inpu t data buf fer. CS4953x4/CS4970x4 System Designer ’s Guide shoul d be consult ed for the

firmware speed limitations.

CP_A[3:0]

PCP_D[7:0] tias

ticdr

tiah

tidd

tirpw

tidhr

tidis

tird tirdtw

PCP_CS#

PCP_WR#

PCP_RD#

PCP_IRQ# tirdirqh

LSP MSP

tias

ticdw

tiah

tiwpw

tidhw

tiwd tiwtrd

tidsu

tiwrbsyl

CP_D[7:0]

PCP_CS#

PCP_WR#

PCP_RD#

PCP_A[3:0]

PCP_BSY#

LSP MSP

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode

Parameter Symbol Min Max Unit

Address setup before PCP_CS# and PCP_DS# low tmas 5-ns

Address hold time after PCP_CS# and PCP_DS# low tmah 5-ns

Read

Delay between PCP_DS# then PCP_CS# low or PCP_CS# then

PCP_DS# low tmcdr 0-ns

Data valid after PCP_CS# and PCP_DS# low with PCP_R/W#

high tmdd -19ns

PCP_CS# and PCP_DS# low for read tmrpw 24 - ns

Data hold time after PCP_CS# or PCP_DS# high after read tmdhr 8-ns

Dat a high-Z af t er PCP_CS# or PCP_DS# high after read tmdis -18ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

next read1

1. The system des igner shou ld be aware that the actual maximu m speed o f th e communicat ion p ort may be limi ted by

the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent

overflow ing the inpu t data buf fer. CS4953x4/CS4970x4 System Designer’s Guide s hou l d be consulte d for the

firmware speed limitations.

tmrd 30 - ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

next write1tmrdtw 30 - ns

PCP_RW# rising to PCP_ IRQ# falling tmrwirqh -12ns

Write

Delay between PCP_DS# then PCP_CS# low or PCP_CS# then

PCP_DS# low tmcdw 0-ns

Data setu p before PCP_CS# or PC P_DS# high tmdsu 8-ns

PCP_CS# and PCP_DS# low for write tmwpw 24 - ns

PCP_R/W# setup before PCP_CS# AND PCP_DS# low tmrwsu 24 - ns

PCP_R/W# hold time after PCP_CS# or PCP_DS# high tmrwhld 8-ns

Data hold after PCP_CS# or PCP_DS# high tmdhw 8-ns

PCP_CS # or PCP_ DS # hi gh t o PC P _ CS # and PCP _DS # l ow wit h

PCP_R/W# high for next read1tmwtrd 30 - ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

next write1tmwd 30 - ns

PCP_RW# rising to PCP_BSY# falling tmrwbsyl - 2*DCLKP + 20 - ns

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing

Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing

tmas

tmcdr

tmah

tmdd

tmrpw

tmdhr

tmdis

tmrd tmrdtw

tmrwsu tmrwhld

PCP_A[3:0]

CP_AD[7:0]

PCP_CS#

PCP_WR#

PCP_DS#

PCP_IRQ# tmrwirqh

LSP MSP

tmas

tmdsu tmdhw

tmwd tmwtrd

tmwpw

tmcdw

tmrwsu

tmrwhld

mah

PCP_A[3:0]

CP_AD[7:0]

PCP_CS#

PCP_WR#

PCP_DS#

PCP_IRQ# tmrwirql

LSP MSP

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.16 Swi tching Characteristics — Digital Audio Slave Input Port

Figure 11. Digital Audio Input (DAI) Port Timing Diagram

Parameter Symbol Min Max Unit

DAI_SCLK period Tdaiclkp 40 - ns

DAI_SCLK du ty cycle - 45 55 %

Setup time DAI_ DATAn tdaidsu 10 - ns

Hold time DAI_D ATAn tdaidh 5-ns

DAI_SCLK

AI_DATAn

tdaidh

tdaidsu

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.17 Switching Character istics — DSD® Serial Input Port

Figure 12. DSD Serial Audio Input Timing

Parameter Symbol Min Typ Max Unit

DSD_SCL K Pul se Width Low tsclkl 78 - - ns

DSD_SCL K Pul se Width High tsclkh 78 - - ns

DSD_SCLK F requency (64x Over sampled) - 1.024 - 3.2 MHz

DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs 20 - - ns

DSD_SCLK rising to DSD_ A or DSD_B hold time tsdh 20 - - ns

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

5.18 Swi tching Characteristics — Digital Audio Output Port

Figure 13. Digital Audio Port Output Timing Master Mode

Parameter Symbol Min Max Unit

DAO_MCLK period Tdaomclk 40 - ns

DAO_MCLK duty cycle - 45 55 %

DAO_SCLK period for Master or Slave mode1

1. Master mode timing specifications are characterized, not production tested.

Tdaosclk 40 - ns

DAO_SCLK duty cycle for Master or Slave mode1-4060%

Master Mode (Output A1 Mode)1,2

2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is

divided to produce DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input tdaomsck -19ns

DAO_SCLK delay from DAO _LRCLK transition, respectively3tdaomlrts -8ns

DAO_LRCLK delay from DAO_SCLK transition , respectively3

3. This timing par ameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the

point at which the data is valid.

tdaomstlr -8ns

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK tran sition3tdaomdv -10ns

Slave Mode (Output A0 Mode)4

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK tran sition3tdaosdv -15ns

DAO_LRCLK delay from DAO_SCLK transition , respectively3tdaosstlr -30ns

DAO_SCLK delay from DAO _LRCLK transition, respectively3tdaoslrts -15ns

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomlclk

tdaomsck

tdaomdv

tdaomlrts

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomclk

tdaomsck

tdaomstlr

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 14. Digital Audio Output Timing, Sla ve Mode (Relationship LRCL K to SCLK)

5.19 Switching Characteristics — SDRAM Interface

Refer to Figure 15 through Figure 18.

(SD_CLKOUT = SD_CLKIN)

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaosstlr

tdaosclk

AO_SCLK

AO_LRCLK

tdaoslrts

tdaosd

tdaosclk

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

Parameter Symbol Min Typical Max Unit

SD_CLKIN high time tsdclkh 2.3 - ns

SD_CLKIN low tim e tsdclkl 2.3 - ns

SD_CLKOUT rise/fall time tsdclkrf -1ns

SD_CLKOUT Frequency 150 MHz

SD_CLKOUT duty cycle - 45 55 %

SD_CLKOUT rising edge to signal valid tsdcmdv -3.8ns

Signal hold from SD_CLKOUT rising edge tsdcmdh 1.1 - ns

SD_CLKOUT rising edge to SD_D QMn valid tsddqv -3.8-ns

SD_DQMn hold from SD_CLKOUT rising edge tsddqh 1.38 - ns

SD_DATA valid setup to SD_CLKIN rising edge tsddsu 1.3 - ns

SD_DATA valid hold to SD_CLKIN rising edge tsddh 1.38 - ns

SD_CLKOUT rising edge to ADDRn valid tsdav -3.8-ns

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 15. External Memory Interface - SDRAM Burst Read Cycle

Figure 16. External Memory Interface - SDRAM Burst Write Cycle

D_CLKOUT

SD_CS#

SD_RAS#

SD_CAS#

SD_WE#

SD_DQMn

SD_An

SD_Dn

tsddsu

tsdclkrf

tsdcmdv

tsdav

tsddqv

tsdcmdh

tsddh

tsddqh

CAS=2 LSP0 MSP0 LSP3 MSP3

SD_CLKIN

tsdclkl tsdclkh

00 11

LSP1 MSP1 LSP2 MSP2

D_CLKOUT

SD_CS#

SD_RAS#

SD_CAS#

SD_WE#

tsdcmdv tsdcmdh

SD_Dn LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3

SD_An

SD_DQMn

tsddqh

00 11

tsddqv

tsdav

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle

D_CLKOUT

SD_CS#

SD_RAS#

SD_CAS#

SD_WE#

SD_DQMn

SD_An

SD_Dn

tsdcmdv tsdcmdh

tsdcmdv

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle

D_CLKOUT

SD_CS#

SD_RAS#

SD_CAS#

SD_WE#

SD_DQMn

SD_An

SD_Dn

OPCODE

tsdcmdv tsdcmdh

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

6. Ordering Informatio n

The CS4970x4 family part number is described as follows:

CS497NNI-XYZ

where

NN - Product Number Variant

I - ROM ID Number

X - Product Grade

Y - Package Type

Z - Lead (Pb) Free

Note: Please contact the factory for availability of the -D (automotive grade) package.

7. Environmental, Manufacturin g, and Handling Information

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Ordering Information

Part No. Grade Temp. Range Container Package

CS4970 04- CQ Z Commercial 0 to +70 °C Tray 144-pin LQFP

CS4970 04-C QZR Commerci al 0 to +70 °C Reel

CS4970 14- CV Z Commercial 0 to +70 °C Tray 128-pin LQFP

CS47014-C V ZR Commercial 0 to +70 °C Reel

CS4970 24- CV Z Commercial 0 to +70 °C Tray 128-pin LQFP

CS4970 24-C VZR Commerci al 0 to +70 °C Reel

Table 5. Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS497004-CQZ 260 °C 3 7 Days

CS497004-CQZR 260 °C 3 7 Days

CS497014-CVZ 260 °C 3 7 Days

CS47014-CVZR 260 °C 3 7 Days

CS497024-CVZ 260 °C 3 7 Days

CS497024-CVZR 260 °C 3 7 Days

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

8. Device Pin-Out Diagr am

8.1 128-Pin LQFP Pin-Out Diagram

Figure 19. 128-Pin LQFP Pin-Out Diagram

GPIO2

GPIO1

GPIO0, EE_CS#

XTO

VDD7

GND7

VDDIO7

XTI

GNDIO7

GNDA

PLL_REF_RES

VDDA (3.3V)

VDD8

GND8

GPIO13, DAI1_DATA2, TM2, DSD2

GPIO14, DAI1_DATA3, TM3, DSD3

DAI1_DATA0, TM0, DSD0

GPIO12, DAI1_DATA1, TM1, DSD1

GPIO6, PCP_CS#, SCP2_CS#

GPIO38, PCP_WR# / DS#, SCP2_CLK

VDD6

GND6

GPIO10, PCP_A2 / A10, SCP2_MOSI

GPIO8, PCP_IRQ #, SCP2_IRQ#

GPIO37, SCP1_BSY#, PCP_BSY

VDDIO6

GPIO11, PCP_A3, AS#, SCP2_MISO / SDA

GNDIO6

GPOI9, SCP1_IRQ#

GPIO34, SCP1__MISO / SDA

GPIO33, SCP1_MOSI

GPIO35, SCP1_CLK

VDD5

VDDIO5

GND5

GNDIO5

SD_CAS#

SD_RAS#

SD_A3, EXT_A3

SD_A2, EXT_A2

SD_A1, EXT_A1

SD_A0, EXT_A0

SD_A10, EXT_A10

SD_A11, EXT_A1

VDD4

GND4

SD_CS#

SD_A4, EXT_A4

SD_A5, EXT_A5

SD_A6, EXT_A6

SD_A7, EXT_A7

SD_A8, EXT_A8

SD_CLKEN

SD_A9, EXT_A9

VDDIO4

GNDIO4

SD_CLKOUT

SD_CLKIN

SD_D10, EXT_D1

SD_D11, EXT_D1

SD_D12, EXT_D1

VDD3

GND3

SD_D13, EXT_D1

SD_D14, EXT_D1

SD_D15, EXT_D1

SD_DQM1

SD_D7, EXT_D7

SD_D6, EXT_D6

VDDIO3

GNDIO3

SD_D5, EXT_D5

SD_DQM0

SD_D4, EXT_D4

SD_D3, EXT_D3

SD_D2, EXT_D2

PIO17, DAO1_DATA3 / XMT A

GPIO15, DAO1_DATA1, HS1

DAO1_DATA0, HS0

DAO1_LRCLK

DAI1_LRCLK, DSD4

DAO_MCLK

GPIO20, DAO2_DATA2

DAI1_SCLK, DSD_CLK

VDD1

GND1

DAO1_SCLK

GPIO16, DAO1_DATA2, HS2

GPIO23,

DAO2_LRCLK RESET#

VDDIO1

GPIO22, DAO2_SCLK

GNDIO1

GPIO18, DAO2_DATA0, HS3

GPIO19, DAO2_DATA1, HS4

VDD2

GND2

GPIO 26, DAO2_DATA 3 / X MTB

VDDIO2

GNDIO2

SD_WE#

SD_D0, EXT_D0

SD_D1, EXT_D1

SD_D8, EXT_D8

SD_D9, EXT_D9

SD_A12, EXT_A1

SD_BA1, EXT_A14

SD_BA0, EXT_A13

GP IO 7, S CP1_ CS #, IOWA IT

VDDIO8

GNDIO8

EXT_A15

EXT_A16

EXT_A17

EXT_A18

EXT_A19

EXT_CS1#

EXT_OE#

EXT_WE#

GPIO3, DDAC

TEST

DBDA

DBCK

XTAL_OUT

GPIO43, BDI_CLK, DAI2_SCLK

PIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#

BDI_DA TA, DAI2_DATA, DSD5

EXT_CS2#

125

120

115

110

105

100

CS497xx4

128-Pin LQFP

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

8.2 144-Pin LQFP Pin-Out Diagram

Figure 20. 144-Pin LQFP Pin-Out Diagram

GPIO11, PCP _A3 , AS#, SCP2 _ M ISO / SDA

SD_A11, EXT_A1

GPIO26

GPIO21, DAO2_DATA3 / XMTB

SD_A12, EXT_A1

PIO 42 , BD I_RE Q# , D AI2 _ LRCLK, PCP _IRQ# / B S Y #

113

116

119

122

126

129

130

133

136

139

109

110

115

120

125

135

140

144

CS497xx4

144-Pin LQ FP

GPIO25, EE_CS#

GPIO24

GPIO31

SD_D7, EXT_D7

SD_D6, EXT_D6

SD_D5, EXT_D5

SD_DQM0

SD_D4, EXT_D4

SD_D3, EXT_D3

SD_D2 , EXT _ D 2

PIO17, DAO1_DATA3 / XMTA

GPIO15, DAO1_DATA1, HS1

DAO1_DATA0, HS0

DAO1_LRCLK

DAO_MCLK

GPIO20, DAO2_DATA2

VDD1

GND1

DAO1_SCLK

GPIO16, DAO1_DATA2, HS2

GPIO23, DAO2_LRCLK

VDDIO1

GPIO22, DAO2_SCLK

GNDIO1

GPIO18, DAO2_DATA0, HS3

GPIO19, DAO2_DATA1, HS4

VDD2

GND2

VDDIO2

GNDIO2

GPIO28, DDAC

GPIO29, XM TA_IN

TEST

DBDA

DBCK

SD _A 3, EXT _A 3

SD _A 2, EXT _A 2

SD _A 1, EXT _A 1

SD _A 0, EXT _A 0

VDD4

GND4

SD _A 4, EXT _A 4

SD _A 5, EXT _A 5

SD _A 6, EXT _A 6

SD _A 7, EXT _A 7

SD _A 8, EXT _A 8

SD_CLKEN

SD _A 9, EXT _A 9

VDDIO4

GNDIO4

SD_CLKOUT

SD_CLKIN

SD _D 10, EX T_D 1

SD _D 11, EX T_D 1

SD _D 12, EX T_D 1

VDD3

GND3

SD _D 13, EX T_D 1

SD _D 14, EX T_D 1

SD _D 15, EX T_D 1

SD_DQM1

VDDIO3

GNDIO3

SD _D 0, EXT _D 0

SD _D 1, EXT _D 1

SD _D 8, EXT _D 8

SD _D 9, EXT _D 9

EXT_CS2#

EXT_WE#

GPIO39, PCP_CS#, SCP2_CS#

GPIO38, PCP_WR# / DS#, SCP2_CLK

VDD6

GPIO40, PC P_R D# / RW#

GND6

GPIO10, PCP _A2 / A10, SCP2_ M OSI

GPIO41, PC P_IR Q #, SCP2 _ IRQ#

GPIO3 7, SC P 1_BSY#, PCP_B SY#

VDDIO6

GNDIO6

GPOI36, SCP1_IRQ#

GPIO34, SC P1__MISO / SDA

GPIO33, SCP 1_ M OS I

GPIO35, SCP 1_ CL K

VDD5

VDDIO5

GND5

GNDIO5

SD_CAS#

SD_RAS#

SD_A10, EXT_A10

SD_CS#

RESET#

SD_WE#

SD_BA1, EXT_A14

SD_BA0, EXT_A13

GPIO32, SC P1_ C S# , IOWAI T

EXT_A15

EXT_A16

EXT_A17

EXT_A18

EXT_A19

EXT_CS1#

EXT_OE#

GPIO30, XMTB _ IN

101

100

105

108

GPIO1, PCP_AD1 / D1

GPIO0, PCP_AD0 / D0

XTO

VDD7

GND7

VDDIO7

XTI

GNDIO7

GNDA

PLL_REF_RES

VDDA (3.3V)

VDD8

GND8

G PIO 1 3, DAI1_ D A TA2, T M 2, D S D 2

GPIO14, DAI1_DATA3, TM3, DSD3

DAI1_DATA0, TM0, DSD0

GPIO 12, DA I1_D A T A 1, TM 1, DSD 1

G PIO2 , P CP _ AD2 / D2

GPIO3, PCP_AD3 / D3

GPIO4, PCP_AD4 / D4

GPIO5, PCP_AD5 / D5

GPIO6, PCP_AD6 / D6

GPIO7, PCP_AD7 / D7

GPIO9, PCP_A1 / A9

DAI1_LRCLK, DSD4

DAI1_SCLK, DSD_CLK

VDDIO8

GNDIO8

GPIO8, PCP_A0 / A8

GPIO27

XTAL_OUT

GPIO43, BDI_CLK, DAI2_SCLK

BDI_DATA, DAI2_DATA, DSD5

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

9. Package Mechanical Drawings

9.1 128-Pin LQFP Package Drawing

Figure 21. 128-Pin LQFP Package Drawing

∝

Table 6. 128-Pin LQFP Package Characteristics

DIM MILLIMETERS INCHES

MIN NOM MAX MIN NOM MAX

A --- --- 1.60 --- --- .063”

A1 0.05 --- 0.15 .002” --- .006”

b 0.17 0.22 0.27 .007” .009” .011”

D 22.00 BSC .866”

D1 20.00 BSC .787”

E 16.00 BSC .630”

E1 14.00 BSC .551”

e 0.50 BSC .020”

q 0° 3.5 7° 0° 3.5 7°

L 0.45 0.60 0.75 .018” .024” .030”

L1 1.00 REF .039” REF

TOLERANCES OF FORM AND POSITION

ddd 0.08 .003”

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

9.2 144-Pin LQFP Package Drawing

Figure 22. 144-Pin LQFP Package Drawing

D1D

Notes:

Controll ing dimension is millimeter.

Dimensioning and tolerancing per

ASME Y14.5M-1994.

SEATING PLANE

ddd B

Table 7. 144-Pin LQFP Package Characteristics

DIM MILLIMETERS INCHES

MIN NOM MAX MIN NOM MAX

A --- --- 1.60 --- --- .063”

A1 0.05 --- 0.15 .002” --- .006”

b 0.17 0.22 0.27 .007” .009” .011”

D 22.00 BSC .866”

D1 20.00 BSC .787”

E 22.00 BSC .866”

E1 20.00 BSC .787”

e 0.50 BSC .020”

q 0° --- 7° 0° --- 7°

L 0.45 0.60 0.75 .018” .024” .030”

L1 1.00 REF .039” REF

TOLERANCES OF FORM AND POSITION

ddd 0.08 .003”

CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

10. Revision History

Revision Date Changes

A1 FEB 2007 Advance Release.

PP1 MAY 2007 Removed Advanced Product watermark, corrected logo, and added “Preliminary

Product Information” on first page and modified legal information to reflect

Preliminary Product status.

PP2 JULY 2007 Added notice about status of DTS-HD license on page 1 and 7.

PP3 OCT 2007

Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode

SPI. This applies to both SPI ports. Removed DTS-HD license notice inserted in

version PP2. The license for the DTS-HD decoder is now in place.

Updated Pin Assignments in 144-Pin LQFP Pin-Out Diagram, removing EE_CS

from Pin 7 and adding EE_CS to Pin 25.

PP4 December 20, 2007

Updated DAO timing specifications and timing diagrams. Changed product

naming conventions in Table 4 and Table 5. Changed references to CS4970x4

Hardware User’s Manual to CS4970x4 System Designer’s Guide. Changed

references to CS4970x4 Fi rmwar e User’s Manual to CS4970x4 System Designer ’s

Guide

PP5 May 28, 2008 Added 128-Pin LQFP Pin-Out and Package drawings. Changed part numbering in

Section 6.and Section 7. Added device and firmware selection guide in Table 2.

PP6 August 4, 2008

Added typical crystal frequency values in Table Footnote 1 and the Max and Min

values of Fxtal in Section 5.8. Removed DSD Phase Modulat ion Mode from

Section 5.17. Removed reference to MCLK in Secti on 5.17. Redefined Master

mode clock speed for SCP_CLK in Section 5.11. Redefined DC leakage

characterization data in Section 5.3, correcting units of measurement. Modified

Footnote 1 under Section 5.10. Chang ed produc t family numbering from

CS497xx to CS4970x4. Corrected product listings in table under Section 5.9

“Switching Characteristics — Internal Clock” on page 13.

PP7 September 30, 2008 Removed references to External Parallel Flash / SRAM Interface.

PP8 November 6, 2009

Updated the feature descriptions on the f ir st pa ge of this data sheet. Removed

references to UART port. Removed references to 11.2896, 18.432, and 27 MHz

frequency clocks in Note 1 in Section 5.8 “Switching Characteristics — XTI” on

page 12 and the Min and Max External Crystal Oper ating Frequency v alues in that

same section. Added Section 5.6 “Thermal Data (128-pin LQFP)” on page 11 .

Updated Figure 9 and Figure 10. Updated Section 5.17 “Switching

Characteristics — DSD“ Serial Input Port” on page 22. Upda ted Figure 15 and

Figure 16. In Section 5.3, the parameter, “Input leakage current (all digital pins

with internal pull- up resistors enabled, and XTI)”, Max value changes from 50

mA to 70 mA. In Section 5.13, the parameter SCP_CLK low to SCP_SDA out

valid with symbol “tiicdov” Max value changes from 18 ns to 36 ns. Added

CS497014 to Section 6. “Ordering Information” on page 28 and to Section 7.

“Environm ental, Manu factur ing, and Ha ndling I nformat ion” on p age 28 . Updated

Table 2, “Device and Firmware Selection Guide,” on page 5.

CS4970 x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

Contacting Ci rru s Logic Sup port

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to

www.cirrus.com

IMPORTANT NOTICE

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is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest versio n of relevant information to verify, before placing

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