2 x 2 W, Filterless, Stereo, Class-D Audio Amplifier with ALC and I2C SSM2380 FEATURES Filterless, stereo, Class-D amplifier with - modulation 2 W into 4 load and 1.4 W into 8 load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) Highly configurable I2C interface for gain adjust, automatic level control (ALC), and ultralow EMI emissions mode MODE pin can disable I2C interface for more traditional stereo amplifier configuration Stereo-to-mono mixer option via I2C control 93% efficiency at 5.0 V, 1.4 W into 8 speaker Signal-to-noise ratio (SNR): >100 dB Single-supply operation from 2.5 V to 5.5 V Ultralow shutdown current: 20 nA Short-circuit and thermal protection Pop-and-click suppression Available in 16-ball, 2.0 mm x 2.0 mm WLCSP APPLICATIONS Mobile phones MP3 players Portable electronics GENERAL DESCRIPTION The SSM2380 is a fully integrated, high efficiency, stereo, Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V supply. It is capable of delivering 2 W of continuous output power with <1% THD + N driving a 4 load from a 5.0 V supply. The SSM2380 features a highly flexible I2C interface with many useful settings. Using the I2C control interface, the gain of the SSM2380 can be selected from 1 dB to 24 dB (plus mute) in 47 steps with no external components. Other features accessed from the I2C interface include independent left/right channel shutdown, variable ultralow EMI emission control mode, automatic level control (ALC) for high quality speaker protection, and stereo-to-mono mixing operation. The SSM2380 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The modulation continues to provide high efficiency even at low output power. The SSM2380 operates with 93% efficiency at 1.4 W into 8 or with 85% efficiency at 2 W into 4 from a 5.0 V supply and has an SNR of >100 dB. Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. An added benefit of spread-spectrum - modulation is that no synchronization (SYNC) is needed when using multiple Class-D amplifiers. For applications that require long speaker cables (>10 cm), the SSM2380 includes a user-selectable ultralow EMI emissions mode that eliminates the need for EMI filters at the Class-D outputs. The SSM2380 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin or through an optional independent channel soft shutdown via I2C. The device also includes pop-and-click suppression circuitry. This suppression circuitry minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. The fully differential inputs of the SSM2380 provide excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. The SSM2380 is specified over the commercial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 16-ball, 2 mm x 2 mm wafer level chip scale package (WLCSP). Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010-2011 Analog Devices, Inc. All rights reserved. SSM2380 TABLE OF CONTENTS Features .............................................................................................. 1 Mixer Mode................................................................................. 18 Applications....................................................................................... 1 Applications Information .............................................................. 19 General Description ......................................................................... 1 Layout .......................................................................................... 19 Revision History ............................................................................... 2 Input Capacitor Selection.......................................................... 19 Functional Block Diagram .............................................................. 3 Power Supply Decoupling ......................................................... 20 Specifications..................................................................................... 4 Typical Application Circuits ......................................................... 21 2 I C Timing Characteristics.......................................................... 5 I2C Interface .................................................................................... 24 Absolute Maximum Ratings............................................................ 6 Register Map ................................................................................... 25 Thermal Resistance ...................................................................... 6 Register Map Details ...................................................................... 26 ESD Caution.................................................................................. 6 Register R0: Left Channel Gain Control, Address 0x00........ 26 Pin Configuration and Function Descriptions............................. 7 Register R1: Right Channel Gain Control, Address 0x01..... 26 Typical Performance Characteristics ............................................. 8 Register R2: Mode Control, Address 0x02.............................. 27 Theory of Operation ...................................................................... 14 Register R3: ALC Control 1, Address 0x03............................. 27 Overview...................................................................................... 14 Register R4: ALC Control 2, Address 0x04............................. 28 Pop-and-Click Suppression....................................................... 14 Register R5: Shutdown, Address 0x05..................................... 29 Output Modulation Description .............................................. 14 Register R6: Error, Address 0x06.............................................. 29 Operating Modes........................................................................ 15 Register R7: Error Clear, Address 0x07 ................................... 29 ALC Mode Operation ................................................................ 15 Register R8: Reset, Address 0x08 ............................................. 29 Gain Select Mode Operation .................................................... 16 Outline Dimensions ....................................................................... 30 2 I C Control Mode Operation.................................................... 16 Ordering Guide .......................................................................... 30 Automatic Level Control (ALC)............................................... 16 REVISION HISTORY 2/11--Rev. 0 to Rev. A Changes to Setting the ALC Threshold Voltage Section........... 15 10/10--Revision 0: Initial Version Rev. A | Page 2 of 32 SSM2380 FUNCTIONAL BLOCK DIAGRAM 10F VDD 2.5V TO 5.5V 0.1F SSM2380 22nF RIGHT IN+ VDD OUTR+ INR+ - MODULATOR INR- RIGHT IN- VDD FET DRIVER OUTR- 22nF SCK SDA MODE GAIN CONTROL (+ALC) I2C 22nF LEFT IN+ INL+ INTERNAL OSCILLATOR EMI CONTROL EDGE SD EMISSION CONTROL SHUTDOWN OUTL+ - - MODULATOR MODULATOR INL- LEFT IN- BIAS FET DRIVER OUTL- 22nF GND ALCTH 08752-001 GAIN1 GAIN0 GND GAIN = 6dB, 12dB, 18dB, OR 24dB Figure 1. Rev. A | Page 3 of 32 SSM2380 SPECIFICATIONS VDD = 5.0 V, TA = 25C, RL = 8 +33 H, gain = 6 dB, I2C control mode, unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Efficiency Total Harmonic Distortion Plus Noise Symbol PO THD + N Test Conditions/Comments 1 f = 1 kHz, 20 kHz bandwidth RL = 8 , THD = 1%, VDD = 5.0 V RL = 8 , THD = 1%, VDD = 3.6 V RL = 8 , THD = 10%, VDD = 5.0 V RL = 8 , THD = 10%, VDD = 3.6 V RL = 4 , THD = 1%, VDD = 5.0 V RL = 4 , THD = 1%, VDD = 3.6 V RL = 4 , THD = 10%, VDD = 5.0 V RL = 4 , THD = 10%, VDD = 3.6 V PO = 1.4 W into 8 , VDD = 5.0 V Normal, low EMI mode Ultralow EMI mode PO = 1 W into 8 , f = 1 kHz, VDD = 5.0 V Min PO = 0.5 W into 8 , f = 1 kHz, VDD = 3.6 V Input Common-Mode Voltage Range Common-Mode Rejection Ratio Channel Separation Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio VCM = 2.5 V 100 mV at 217 Hz, output referred PO = 100 mW, f = 1 kHz VDD PSRR PSRRGSM 2.5 70 1 Supply Current, Stereo ISY Shutdown Current ISD Gain GAINx = I2C control mode VIH VIL tWU tSD ZOUT NOISE PERFORMANCE Output Voltage Noise en Signal-to-Noise Ratio 1 SNR 93 91 0.005 % % % VDD - 1.0 55 78 325 2.0 Gain = 6 dB Unit W W W W W W W W 0.005 CMRRGSM XTALK fSW VOOS Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, dc input floating VRIPPLE = 100 mV at 217 Hz, inputs ac-grounded, CIN = 0.1 F VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V VIN = 0 V, RL = 8 + 33 H, VDD = 5.0 V VIN = 0 V, RL = 8 + 33 H, VDD = 3.6 V VIN = 0 V, RL = 8 + 33 H, VDD = 2.5 V SD = GND Max 1.43 0.73 1.8 0.92 2.581 1.3 3.21 1.62 1.0 VCM GAIN CONTROL Closed-Loop Gain SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance Typ % V dB dB kHz mV 85 60 5.5 V dB dB 6.8 6.0 5.8 7.0 6.1 5.5 20 mA mA mA mA mA mA nA 24 1.35 dB SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND 7 5 >100 V V ms s k VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac-grounded, gain = 6 dB, A-weighted PO = 1.4 W, RL = 8 , gain = 6 dB PO = 1.4 W, RL = 8 , gain = 24 dB 30 V rms 100 90 dB dB 0.35 Although the SSM2380 has good quality above 2 W, continuous output power beyond 2 W must be avoided due to device packaging limitations. Rev. A | Page 4 of 32 SSM2380 I2C TIMING CHARACTERISTICS Table 2. Parameter tSCS tSCH tPH tPL fSCK tDS tDH tRT tFT tHCS tMIN 600 600 600 1.3 0 100 Limit tMAX Unit ns ns ns s kHz ns ns ns ns ns 526 900 300 300 600 Description Start condition setup time Start condition hold time SCK pulse width high SCK pulse width low SCK frequency Data setup time Data hold time SDA and SCK rise time SDA and SCK fall time Stop condition setup time Timing Diagram tSCH tHCS SDA tDS tSCS tPH SCK tRT tDH 2 Figure 2. I C Timing Rev. A | Page 5 of 32 tFT 08752-002 tPL SSM2380 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 6V VDD VDD 4 kV -65C to +150C -40C to +85C -65C to +165C 300C Table 4. Thermal Resistance Package Type 16-Lead, 2.0 mm x 2.0 mm WLCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 32 PCB 2S2P JA 57 JB 14 Unit C/W SSM2380 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 A OUTL+ VDD VDD OUTR+ B OUTL- GND GND OUTR- C SD MODE SCK EDGE GAIN0 SDA ALCTH GAIN1 D INL+ INL- INR- INR+ TOP VIEW (BALL SIDE DOWN) Not to Scale 08752-003 BALL A1 INDICATOR Figure 3. Pin Configuration (Bottom View) Table 5. Pin Function Descriptions Pin No. A1 A2, A3 A4 B1 B2, B3 B4 C1 C2 C3 Mnemonic OUTL+ VDD OUTR+ OUTL- GND OUTR- SD MODE SCK/EDGE/GAIN0 C4 SDA/ALCTH/GAIN1 D1 D2 D3 D4 INL+ INL- INR- INR+ Description Noninverting Output for Left Channel. Power Supply for Output Amplifiers. Noninverting Output for Right Channel. Inverting Output for Left Channel. Ground for Output Amplifiers. Inverting Output for Right Channel. Shutdown Input. Active low digital input. Three-Mode Interface Control Pin. 2-Wire I2C Control Interface Clock Input (SCK). MODE is connected to GND. Low Emissions Mode Enable Pin (EDGE). MODE is floating. Gain Select Pin, LSB (GAIN0). MODE is connected to VDD. 2-Wire I2C Control Interface Data Input/Output (SDA). MODE is connected to GND. Variable Threshold Voltage for ALC (ALCTH). MODE is floating. Gain Select Pin, MSB (GAIN1). MODE is connected to VDD. Noninverting Input for Left Channel. Inverting Input for Left Channel. Inverting Input for Right Channel. Noninverting Input for Right Channel. Rev. A | Page 7 of 32 SSM2380 TYPICAL PERFORMANCE CHARACTERISTICS EDGE pin = GND, unless otherwise noted. 100 RL = 8 + 33H GAIN = 6dB VDD = 2.5V 1 VDD = 3.6V 0.1 VDD = 5V 1 VDD = 3.6V 0.1 VDD = 5V 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 08752-020 0.001 100 VDD = 2.5V 0.1 VDD = 5V 0.01 10 VDD = 2.5V 1 VDD = 3.6V 0.1 VDD = 5V 0.01 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 08752-022 0.001 0.0001 1 RL = 4 + 15H GAIN = 24dB 10 THD + N (%) VDD = 3.6V 0.1 Figure 7. THD + N vs. Output Power into 8 , Gain = 24 dB RL = 4 + 15H GAIN = 6dB 1 0.01 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 8 , Gain = 6 dB 10 0.001 08752-021 0.01 0.001 0.0001 THD + N (%) VDD = 2.5V 10 0.01 100 RL = 8 + 33H GAIN = 24dB 0.001 0.01 0.1 1 10 OUTPUT POWER (W) Figure 5. THD + N vs. Output Power into 4 , Gain = 6 dB 08752-023 THD + N (%) 10 THD + N (%) 100 Figure 8. THD + N vs. Output Power into 4 , Gain = 24 dB 100 100 VDD = 5V RL = 8 + 33H 10 GAIN = 6dB VDD = 5V RL = 8 + 33H GAIN = 24dB 10 THD + N (%) 1W 0.1 0.5W 1 1W 0.1 0.01 0.5W 0.01 0.001 100 1k 10k 100k FREQUENCY (Hz) Figure 6. THD + N vs. Frequency, VDD = 5 V, RL = 8 , Gain = 6 dB 0.001 10 0.25W 100 1k 10k 100k FREQUENCY (Hz) Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 8 , Gain = 24 dB Rev. A | Page 8 of 32 08752-025 0.0001 10 0.25W 08752-024 THD + N (%) 1 SSM2380 100 100 VDD = 5V RL = 4 + 15H GAIN = 6dB 10 1 THD + N (%) THD + N (%) 10 VDD = 5V RL = 4 + 15H GAIN = 24dB 2W 0.1 1 2W 0.1 1W 1W 0.01 0.01 100 1k 10k 100k FREQUENCY (Hz) 0.001 10 08752-026 1 1 THD + N (%) 0.5W 0.1 VDD = 3.6V RL = 8 + 33H GAIN = 24dB 0.5W 0.1 0.25W 0.25W 0.01 0.01 0.125W 0.125W 1k 10k 100k 0.001 10 08752-028 100 FREQUENCY (Hz) 1k 10k 100k Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 , Gain = 24 dB 100 VDD = 3.6V RL = 4 + 15H GAIN = 6dB 10 10 1 1 THD + N (%) THD + N (%) 100 FREQUENCY (Hz) Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 , Gain = 6 dB 1W 0.1 VDD = 3.6V RL = 4 + 15H GAIN = 24dB 1W 0.1 0.5W 0.5W 0.01 0.01 0.25W 0.25W 100 1k 10k 100k FREQUENCY (Hz) 08752-030 0.001 10 100k 08752-029 THD + N (%) 100 VDD = 3.6V RL = 8 + 33H GAIN = 6dB 10 100 10k Figure 13. THD + N vs. Frequency, VDD = 5 V, RL = 4 , Gain = 24 dB 10 0.001 10 1k FREQUENCY (Hz) Figure 10. THD + N vs. Frequency, VDD = 5 V, RL = 4 , Gain = 6 dB 100 100 Figure 12. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 , Gain = 6 dB 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 08752-031 0.001 10 08752-027 0.5W 0.5W Figure 15. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 , Gain = 24 dB Rev. A | Page 9 of 32 SSM2380 100 100 VDD = 2.5V RL = 8 + 33H GAIN = 6dB 10 10 1 THD + N (%) 1 0.25W 0.1 0.25W 0.1 0.125W 0.125W 0.01 0.01 0.0625W 0.0625W 100 1k 10k 100k FREQUENCY (Hz) 0.001 10 08752-032 0.001 10 1k 10k 100k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 , Gain = 6 dB 100 100 08752-033 THD + N (%) VDD = 2.5V RL = 8 + 33H GAIN = 24dB Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 , Gain = 24 dB 100 VDD = 2.5V RL = 4 + 15H GAIN = 6dB 10 VDD = 2.5V RL = 4 + 15H GAIN = 24dB 10 0.5W 1 0.1 0.25W 0.1 0.01 0.25W 0.01 100 1k 10k 100k FREQUENCY (Hz) 08752-034 0.001 10 Figure 17. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 , Gain = 6 dB 7.0 BOTH CHANNELS GAIN = 6dB 10k 100k BOTH CHANNELS GAIN = 24dB 6.5 6.5 RL = 4 + 15H 6.0 RL = 8 + 33H 5.5 5.0 NO LOAD RL = 4 + 15H 6.0 RL = 8 + 33H 5.5 5.0 NO LOAD 4.5 4.5 4.0 2.5 1k Figure 20. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 , Gain = 24 dB 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 4.0 2.5 08752-036 SUPPLY CURRENT (mA) 7.0 100 FREQUENCY (Hz) SUPPLY CURRENT (mA) 7.5 0.001 10 08752-035 0.125W 0.125W Figure 18. Supply Current vs. Supply Voltage, Gain = 6 dB 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 Figure 21. Supply Current vs. Supply Voltage, Gain = 24 dB Rev. A | Page 10 of 32 08752-037 THD + N (%) 1 THD + N (%) 0.5W SSM2380 2.0 2.0 1.4 1.4 THD + N = 10% 1.0 0.8 THD + N = 1% 0.6 0.2 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 Figure 25. Maximum Output Power vs. Supply Voltage, RL = 8 , Gain = 24 dB 3.5 3.5 f = 1kHz RL = 4 + 15H GAIN = 6dB 3.0 3.0 2.0 OUTPUT POWER (W) 2.5 THD + N = 10% 1.5 THD + N = 1% 1.0 f = 1kHz RL = 4 + 15H GAIN = 24dB 2.5 2.0 THD + N = 10% 1.5 THD + N = 1% 1.0 0.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 0 2.5 08752-040 0 2.5 Figure 23. Maximum Output Power vs. Supply Voltage, RL = 4 , Gain = 6 dB 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 08752-041 0.5 Figure 26. Maximum Output Power vs. Supply Voltage, RL = 4 , Gain = 24 dB 100 100 VDD = 2.5V 90 90 RL = 4 + 15H 80 VDD = 3.6V 60 RL = 8 + 33H 70 EFFICIENCY (%) 70 VDD = 5V 50 40 60 30 20 10 10 0.6 0.8 1.0 1.2 OUTPUT POWER (W) 1.4 1.6 1.8 0 08752-042 0.4 Figure 24. Efficiency vs. Output Power into 8 VDD = 5V 40 20 0.2 VDD = 3.6V 50 30 0 VDD = 2.5V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT POWER (W) Figure 27. Efficiency vs. Output Power into 4 Rev. A | Page 11 of 32 08752-043 80 0 THD + N = 1% 0.6 0.2 Figure 22. Maximum Output Power vs. Supply Voltage, RL = 8 , Gain = 6 dB OUTPUT POWER (W) 0.8 0.4 3.0 THD + N = 10% 1.0 0.4 0 2.5 EFFICIENCY (%) 1.2 08752-039 OUTPUT POWER (W) 1.2 f = 1kHz 1.8 RL = 8 + 33H GAIN = 24dB 1.6 08752-038 OUTPUT POWER (W) f = 1kHz 1.8 RL = 8 + 33H GAIN = 6dB 1.6 SSM2380 0.8 1.6 BOTH CHANNELS RL = 8 + 33H GAIN = 6dB 0.7 0.5 VDD = 3.6V VDD = 2.5V 0.3 0.4 0.1 0.2 0.5 1.0 1.5 2.0 2.5 OUTPUT POWER (W) 3.0 3.5 VDD = 2.5V 0.6 0.2 0 VDD = 3.6V 0.8 0 0 0 -10 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) 0 -50 -60 -80 -80 -90 -90 -100 10 -100 10 10k 100k FREQUENCY (Hz) Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency VDD = 5V VRIPPLE = 500mV rms -20 RL = 8 + 33H -60 LEFT TO RIGHT -80 RIGHT TO LEFT -120 100 1k 10k FREQUENCY (Hz) 100k 08752-046 CROSSTALK (dB) -40 -140 10 100 1k 10k 100k FREQUENCY (Hz) Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency 0 -100 6 -60 -70 1k 5 -50 -70 100 2 3 4 OUTPUT POWER (W) Figure 31. Supply Current vs. Output Power into 4 08752-047 CMRR (dB) Figure 28. Supply Current vs. Output Power into 8 1 Figure 30. Crosstalk vs. Frequency Rev. A | Page 12 of 32 08752-048 0.4 VDD = 5V 1.0 08752-045 SUPPLY CURRENT (A) 1.2 VDD = 5V 08752-044 SUPPLY CURRENT (A) 0.6 0 BOTH CHANNELS RL = 4 + 15H GAIN = 6dB 1.4 SSM2380 6 6 5 OUTPUT 5 OUTPUT 3 3 VOLTAGE (V) 4 2 1 2 1 0 0 -1 -1 -2 -2 0 2 4 6 8 10 12 14 TIME (ms) 16 18 20 -2 -160 -120 -80 -40 0 40 80 120 TIME (s) Figure 33. Turn-On Response Figure 34. Turn-Off Response Rev. A | Page 13 of 32 160 200 240 08752-050 SD INPUT 08752-049 VOLTAGE (V) SD INPUT 4 SSM2380 THEORY OF OPERATION The SSM2380 stereo, Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external component count, conserving board space and, thus, reducing system cost. The SSM2380 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2380 uses - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. * * * * - modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing EMI emissions that might otherwise be radiated by speakers and long cable traces. The SSM2380 does not require external EMI filtering for twisted speaker cable lengths shorter than 10 cm. If longer speaker cables are used, the SSM2380 has an emission suppression mode that allows significantly longer speaker cable. Due to the inherent spread-spectrum nature of - modulation, the need for modulator synchronization is eliminated for designs that incorporate multiple SSM2380 amplifiers. 2 Using the I C control interface, the gain of the SSM2380 can be selected from 1 dB to 24 dB (plus mute) in 47 steps with no external components and fixed input impedance. Other features accessed from the I2C interface include the following: * * * * Independent left/right channel shutdown Variable ultralow EMI emission control mode Automatic level control (ALC) for high quality speaker protection Stereo-to-mono mixing operation The SSM2380 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. OUTPUT MODULATION DESCRIPTION The SSM2380 uses three-level, - output modulation. Each output can swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. Due to the constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse (OUTx+ and OUTx-) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 35 depicts three-level, - output modulation with and without input stimulus. OUTPUT = 0V OUT+ 0V +5V OUT- 0V +5V VOUT 0V -5V OUTPUT > 0V OUT+ 0V +5V VOUT 0V OUTPUT < 0V OUT+ 0V 0V VOUT Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients may be generated when the amplifier system changes its operating mode. For example, the following may be sources of audible transients: system power-up and power-down, mute and unmute, input source change, and sample rate change. Rev. A | Page 14 of 32 +5V 0V +5V OUT- POP-AND-CLICK SUPPRESSION +5V 0V +5V OUT- The SSM2380 also offers protection circuits for overcurrent and overtemperature protection. +5V -5V Figure 35. Three-Level, - Output Modulation With and Without Input Stimulus 08752-004 OVERVIEW SSM2380 The SSM2380 has three unique operating modes, controlled by the MODE pin. When MODE (Ball C2) is connected to GND, the SSM2380 operates in I2C control mode; Ball C3 and Ball C4 function as SCK and SDA for the I2C input. In I2C control mode, the user has full control of all internal registers of the SSM2380 (see Table 11). Maximum output power is derived from VTH using the following equation: POUT (Limit x VDD ) / 100 2 = R SP where RSP is the speaker impedance. When MODE (Ball C2) is connected to VDD, the SSM2380 operates in gain select mode; Ball C3 and Ball C4 function as the gain select pins, GAIN0 and GAIN1. All ALC and emission control features are disabled in gain select mode, and the user can set the gain to 6 dB, 12 dB, 18 dB, or 24 dB only. 95 OUTPUT VOLTAGE LIMIT (%) 90 When MODE (Ball C2) is not connected (floating), the SSM2380 operates in ALC mode; Ball C3 and Ball C4 function as EDGE and ALCTH. In ALC mode, the default gain is 18 dB. The user can enable or disable the emission control (EMI) feature by connecting EDGE (Ball C3) to VDD or GND. In addition to emission control, the ALC is activated. The user must connect a resistor from ALCTH (Ball C4) to GND. This resistor allows the user to limit the output level to any setting from 45% to 90% of VDD. 85 80 75 70 65 60 55 50 45 100 Table 6. MODE Pin Selection Guide SSM2380 Ball Ball C2 (MODE) Ball C3 High (connected to VDD) GAIN0 Low (connected to GND) SCK Open (floating) EDGE 2 TYPICAL CONDITION INTERNAL RESISTOR - 20% INTERNAL RESISTOR + 20% 1k 10k RESISTOR () 100k 1M 08752-005 OPERATING MODES Figure 36. Output Voltage Limit (VTH) vs. RTH Ball C4 GAIN1 SDA ALCTH Operating Mode Gain select mode I2C control mode ALC mode ALC MODE OPERATION When MODE is not connected (floating), the SSM2380 is in ALC mode, disabling the I2C interface. In ALC mode, the user has control of only two functions: setting the ALC threshold voltage and activating or deactivating the emission limiting circuitry. Setting the ALC Threshold Voltage To set the ALC threshold voltage, connect ALCTH (Ball C4) to GND with a series resistor. Figure 36 shows the relationship between the RTH resistor setting and the output voltage limit as a percentage of the supply rail. To calculate the resistor value, use the following equations: Limit (%) = 100 x (REXT + 53)/(2.2 x REXT + 58) k REXT = (53 - 58 x Limit/100)/(2.2 x (Limit/100 - 1))% For example, to set an 80% limit, REXT = (53 - 58 x 80/100)/(2.2 x (80/100 - 1) k In ALC mode, the attack, hold, and release times associated with ALC operation are at fixed levels, as indicated in Table 7. Table 7. Attack, Hold, and Release Times for ALC Mode Time Attack Time Hold Time Release Time Duration 256 s (per 0.5 dB step) 90 ms to 120 ms (nonadjustable) 128 ms (per 0.5 dB step) Activating or Deactivating the Emission Limiting Circuitry To activate or deactivate the emission limiting circuitry, connect EDGE (Ball C3) to GND or to VDD. When EDGE is connected to GND, the SSM2380 is in normal operating mode, deactivating the emission limiting function. The device operates with maximum efficiency and noise level performance in this setting. The user can also pass FCC Class B emission testing with 10 cm twisted pair speaker wire for loudspeaker connection. If longer speaker wire is desired, connect the EDGE pin to VDD to activate the emission limiting circuitry. The trade-off is slightly lower efficiency and noise performance. The penalty for using the emission control circuitry is far less than the decreased performance observed when using a ferrite bead based EMI filter for emission limiting purposes. Therefore, 8.7 k is required. Rev. A | Page 15 of 32 SSM2380 Table 8. Gain Settings in Gain Select Mode GAIN0 (Ball C3) GND VDD GND VDD GAIN1 (Ball C4) GND GND VDD VDD Gain Setting (dB) 6 12 18 24 5.6 5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 INPUT GAIN = 6dB GAIN = 12dB GAIN = 18dB GAIN = 24dB 1.6 1.2 0.8 0.4 0 2 I C CONTROL MODE OPERATION When MODE is connected to GND, the SSM2380 operates in I2C control mode, enabling Ball C3 and Ball C4 to act as SCK and SDA for the I2C input. In I2C control mode, the user has full control of all features of the SSM2380 (see Table 11). * * * * Gain control: 48-step, left/right independent control (ALC is off) ALC control (limiter/compressor): configurable attack and release times; configurable threshold voltage (16 level settings, 64% to 96% of VDD); optional fixed-power mode (does not track rail) Output stage: active emissions edge rate control (four settings) Mixer: option to send left channel input to both left and right channel outputs or to send right channel input to both outputs AUTOMATIC LEVEL CONTROL (ALC) Automatic level control (ALC) is a function that automatically adjusts amplifier gain to generate the desired output amplitude with reference to a particular input stimulus. The primary use for the ALC is to protect an audio power amplifier or speaker load from the damaging effects of clipping or current overloading. This is accomplished by limiting the output amplitude of the amplifier upon reaching a preset threshold voltage. Another benefit of the ALC is that it makes sound sources with a wide dynamic range more intelligible by boosting low level signals, while in turn limiting very high level signals. 0 20 40 60 80 100 120 TIME (ms) 140 160 180 200 08752-006 When MODE is connected to VDD, the SSM2380 is in gain select mode, disabling the I2C interface. The ALC and emission limiting functions are also disabled. Ball C3 and Ball C4 function as the gain select pins, GAIN0 and GAIN1. Table 8 shows the user-selectable gain settings for the SSM2380. Figure 37 shows the input vs. output and gain characteristics of the ALC that is implemented in the SSM2380. OUTPUT VOLTAGE LEVEL (V) GAIN SELECT MODE OPERATION Figure 37. Input vs. Output and Gain Characteristics When the input level is small and below the ALC threshold value, the gain of the amplifier stays at the preset gain setting. When the input exceeds the ALC threshold value, the ALC gradually reduces the gain from the preset gain setting down to 1 dB. ALC Compression and Limiting Modes The ALC implemented on the SSM2380 has two operation modes: compression and limiting. When the ALC is triggered for medium-level input signals, the ALC is in compression mode. In this mode, an increase of the output signal is one-third the increase of the input signal. For example, if the input signal increases by 3 dB, the ALC reduces the amplifier gain by 2 dB and thus the output signal increases by only 1 dB. As the input signal becomes very large, the ALC transitions to limiting mode. In this mode, the output stays at a given threshold level, VTH, even if the input signal grows larger. As an example of limiting mode operation, when a large input signal increases by 3 dB, the ALC reduces the amplifier gain by 3 dB and thus the output increases by 0 dB. When the amplifier gain is reduced to 1 dB, the ALC cannot reduce the gain further, and the output increases again. This is because the total range of the ALC operation has bottomed out due to extreme input voltage at high gain. To avoid potential speaker damage, the maximum input amplitude should not be large enough to exceed the maximum attenuation (to a level of 1 dB) of the limiting mode. Before activating the ALC by setting the ALC_EN bit (Bit 7 in Register R4), the user has full control of the left and right channel PGA gain (programmable in Register R0 and Register R1). After the ALC is activated (ALC_EN = 1), the user has no control over the gain settings in Register R0 and Register R1; the left channel PGA gain is locked into the device and controls the gain for both the left and right channels. To change the gain, the user must reset the ALC_EN bit to 0 and then load the new gain settings. Rev. A | Page 16 of 32 SSM2380 3.5 When the amplifier input signal exceeds a preset threshold, the ALC reduces amplifier gain rapidly until the output voltage settles to a target level. This target level is maintained for a certain period. If the input voltage does not exceed the threshold again, the ALC increases the gain gradually. 3.0 The attack time is the time taken to reduce the gain from maximum to minimum. The hold time is the time that the reduced gain is maintained. The release time is the time taken to increase the gain from minimum to maximum. These times are shown in Table 9. 2.5 2.0 1.5 1.0 00 (LIMITER MODE) 01 (COMPRESSION MODE 1) 10 (COMPRESSION MODE 2) 11 (COMPRESSION MODE 3) 3.6V x 0.77 = 2.772V 0.5 0 0 Table 9. Attack, Hold, and Release Times for I2C Control Mode Time Attack Time Hold Time Release Time 0.2 0.3 0.4 0.5 0.6 0.7 INPUT VOLTAGE (V) 0.8 0.9 1.0 Figure 39. Adjustable Compression Settings, VDD = 3.6 V, ALC Threshold Level = 77% 4.5 4.0 The attack time and release time can be adjusted using the I2C interface. The hold time cannot be adjusted. 3.5 OUTPUT VOLTAGE (V) 1 Duration 32 s to 4 ms (per 0.5 dB step) 90 ms to 120 ms 4 ms to 512 ms (per 0.5 dB step) 0.1 Soft-Knee Compression Often performed using sophisticated DSP algorithms, soft-knee compression provides maximum sound quality with effective speaker protection. Instead of using a fixed compression setting prior to limiting, the SSM2380 allows for a much more subtle transition into limiting mode, preserving the original sound quality of the source audio. Figure 38 to Figure 40 show the various soft-knee compression settings. If desired, compression can be disabled. When compression is disabled, the part operates in limiter-only mode. 3.0 2.5 2.0 1.5 00 (LIMITER MODE) 01 (COMPRESSION MODE 1) 10 (COMPRESSION MODE 2) 11 (COMPRESSION MODE 3) 5.0V x 0.77 = 3.85V 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 INPUT VOLTAGE (V) 1.6 1.8 2.0 08752-019 1 08752-018 OUTPUT VOLTAGE (V) Attack Time, Hold Time, and Release Time Figure 40. Adjustable Compression Setting, VDD = 5.0 V, ALC Threshold Level = 77% 2.5 ALC Soft Transition The ALC operation of the SSM2380 incorporates techniques to reduce the audible artifacts associated with gain change transitions. First, the gain is changed in small increments of 0.5 dB. In addition to this small step size, the rate of gain change is reduced, proportional to the attack time setting. This feature drastically reduces and virtually eliminates the presence of zipper noise and other artifacts associated with gain transitions during ALC operation. Figure 41 shows the soft transition operation. 1.5 1.0 00 (LIMITER MODE) 01 (COMPRESSION MODE 1) 10 (COMPRESSION MODE 2) 11 (COMPRESSION MODE 3) 2.5V x 0.77 = 1.925V 0.5 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 INPUT VOLTAGE (V) 0.40 0.45 0.50 NORMAL TRANSITION 08752-007 0.5dB Figure 38. Adjustable Compression Settings, VDD = 2.5 V, ALC Threshold Level = 77% SOFT TRANSITION (32s TO 256s) 0.5dB 08752-008 OUTPUT VOLTAGE (V) 2.0 Figure 41. Soft Transition Rev. A | Page 17 of 32 SSM2380 MIXER MODE When the ALC is active, the following options are acceptable: When I2C control mode is activated, the user can send left channel input to both left and right channel outputs or send right channel input to both outputs. This is achieved by selecting Register R2, Bit 0 or Bit 1. * * * Left output = left input; right output = right input Left output = left input; right output = left input Left output = right input; right output = right input To use the following options, the ALC must be disabled: Using Mixer Mode with the ALC If the ALC is enabled and the user also wishes to use the mixer operation, follow the guidelines in this section. Left channel gain controls the ALC; therefore, sending left channel input to the left and right channel outputs poses no problem for the ALC. However, to source the right channel input to the left and right channel outputs when using the ALC, the user must first load the left channel gain (Register R0, Bit 7). * * * With the ALC disabled, the user can also use the full mixer capability; that is, if the user wishes to mix the right and left inputs for both the right and left outputs, the ALC must be disabled. If the user needs both the mixing and ALC functions, the left or right channel must be muted to avoid problems. Rev. A | Page 18 of 32 Left output = left input + right input; right output = right input Left output = left input; right output = left input + right input Left output = left input + right input; right output = left input + right input SSM2380 APPLICATIONS INFORMATION LAYOUT Table 10. Input Impedance for I2C Control Mode As output power increases, care must be taken to lay out printed circuit board (PCB) traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. LGAIN[5:0], RGAIN[5:0] 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 100000 011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 000000 Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layout isolates critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be directly beneath the analog power plane, and, similarly, the digital ground plane should be directly beneath the digital power plane. There should be no overlap between analog and digital ground planes or between analog and digital power planes. INPUT CAPACITOR SELECTION The SSM2380 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If highpass filtering is needed at the input, the input capacitor and the input resistor of the SSM2380 form a high-pass filter whose corner frequency is determined by the following equation: fC = 1/(2 x RIN x CIN) The input capacitor can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset of the amplifier and the dc PSRR performance. In I2C control mode, the input impedance changes depending on the gain setting from Register R0 and Register R1 (LGAIN[5:0] and RGAIN[5:0] bits). Table 10 shows the RIN value for each PGA gain setting. Rev. A | Page 19 of 32 Gain (dB) 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 RIN (k) 7.3 7.7 8.1 8.5 9.0 9.5 10.0 10.5 11.1 11.7 12.3 12.9 13.6 14.3 15.0 15.8 16.6 17.4 18.3 19.2 20.1 21.1 22.1 23.1 24.2 25.3 26.4 27.6 28.8 30.0 31.3 32.6 34.0 35.3 36.7 38.1 39.6 41.1 42.6 44.1 45.6 47.1 48.7 50.3 51.8 53.4 55.0 SSM2380 POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency is typically 325 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply inputs must be decoupled with a good quality, low ESL, low ESR capacitor, usually of approximately 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 F capacitor as close as possible to the VDD pins of the device. Placing the decoupling capacitors as close as possible to the SSM2380 helps to maintain efficient performance. Rev. A | Page 20 of 32 SSM2380 TYPICAL APPLICATION CIRCUITS GAIN INL MODULATOR OUTL MODULATOR OUTR GAIN INR 08752-011 ALC Figure 42. SSM2380 Mixer Operation Block Diagram VDD B1 MPZ1608S121A C26 10F OUT_L+ C27 L INPUT + L INPUT- C22 R14 0.22F C23 R15 0 D1 D2 0 A3 GND INL+ OUTL+ INL- OUTL- 0.22F C33 510pF GND VDD VDD A2 0.1F A1 B2 MPZ1608S121A B1 0.22F C25 R16 R17 0 D4 D3 0 INR+ OUTR+ INR- OUTR- B3 MPZ1608S121A A4 MODE C35 510pF SDA GND GND SD SCK C2 C4 H7 HDR1X2 GND C3 GND B4 MPZ1608S121A B3 C1 STDN OUT_R+ B4 0.22F B2 C36 510pF OUT_R- GND I2C[0..1] SDA SCK 08752-012 I2CVDD R20 2.5k R21 2.5k Figure 43. SSM2380 Typical Schematic, I2C Control Mode 10F VDD 2.5V TO 5.5V 0.1F SSM2380 22nF RIGHT IN+ VDD OUTR+ - MODULATOR INR- RIGHT IN- VDD INR+ FET DRIVER OUTR- 22nF SCK SDA MODE = GND I2C 22nF LEFT IN+ INL+ BIAS INTERNAL OSCILLATOR EMI CONTROL SD SHUTDOWN OUTL+ - - MODULATOR MODULATOR INL- LEFT IN- GAIN CONTROL (+ALC) FET DRIVER OUTL- 22nF GND GND 08752-013 R INPUT- C24 OUT_L- U8 SSM2380 R INPUT + H6 HDR1X2 C34 510pF I2C OPERATION (MODE PIN = GND) Figure 44. SSM2380 I2C Control Mode Configuration (MODE Pin = GND) Rev. A | Page 21 of 32 SSM2380 VDD B1 MPZ1608S121A C26 10F OUT_L+ C27 L INPUT + L INPUT- C22 D1 0.22F C23 D2 C33 510pF A3 GND GND VDD VDD A2 0.1F INL+ OUTL+ INL- OUTL- 0.22F A1 B2 MPZ1608S121A B1 R INPUT - OUT_L- U8 SSM2380 R INPUT + H6 HDR1X2 C34 510pF C24 D4 0.22F C25 D3 INR+ OUTR+ INR- OUTR- B3 MPZ1608S121A A4 C35 510pF 0.22F MODE SD B2 GND GND EDGE ALCTH C2 C3 GND C4 B4 MPZ1608S121A B3 C1 STDN OUT_R+ B4 H7 HDR1X2 C36 510pF OUT_R- FLOAT GND EMI CTRL ALC THRESHOLD RESISTOR 08752-014 R20 12k GND Figure 45. SSM2380 Typical Schematic, ALC Mode 10F VDD 2.5V TO 5.5V 0.1F SSM2380 22nF RIGHT IN+ VDD OUTR+ - MODULATOR INR- RIGHT IN- VDD INR+ FET DRIVER OUTR- 22nF I2 C DISABLED MODE = OPEN 22nF LEFT IN+ 18dB GAIN (+ALC) BIAS EMI CONTROL EDGE SD INL+ EMISSION CONTROL SHUTDOWN OUTL+ - - MODULATOR MODULATOR INL- LEFT IN- INTERNAL OSCILLATOR FET DRIVER OUTL- 22nF GND ALCTH 08752-015 ALC OPERATION (MODE PIN = OPEN) GND RTH Figure 46. SSM2380 ALC Mode Configuration (MODE Pin = Open (Floating)) Rev. A | Page 22 of 32 SSM2380 VDD B1 MPZ1608S121A C26 10F OUT_L+ C27 C33 510pF GND A3 A2 0.1F L INPUT + L INPUT- C22 0.22F C23 R14 0 R15 0 D1 D2 VDD VDD GND INL+ OUTL+ OUTL- INL- 0.22F A1 B2 MPZ1608S121A B1 R INPUT - C34 510pF OUT_L- U8 SSM2380 R INPUT + H6 HDR1X2 C24 R16 0.22F C25 0 R17 D4 D3 0 OUTR+ INR+ OUTR- INR- B3 MPZ1608S121A A4 0.22F C35 510pF I2CVDD MODE GAIN1 B2 GND GND SD GAIN0 C2 C4 GND C3 B4 MPZ1608S121A B3 C1 STDN OUT_R+ B4 H7 HDR1X2 C36 510pF OUT_R- GND 08752-016 GAIN SELECT G1 GAIN SELECT G0 Figure 47. SSM2380 Typical Schematic, Gain Select Mode 10F VDD 2.5V TO 5.5V 0.1F SSM2380 22nF RIGHT IN+ VDD OUTR+ - MODULATOR INR- RIGHT IN- VDD INR+ FET DRIVER OUTR- 22nF I2 C DISABLED MODE = VDD GAIN CONTROL BIAS INTERNAL OSCILLATOR EMI CONTROL SD 22nF LEFT IN+ INL+ LEFT IN- OUTL+ - - MODULATOR MODULATOR INL- SHUTDOWN FET DRIVER OUTL- 22nF GND GAIN = 6dB, 12dB, 18dB, OR 24dB 08752-017 GAIN1 GAIN0 GND GAIN OPERATION (MODE PIN = VDD) Figure 48. SSM2380 Gain Select Mode Configuration (MODE Pin = VDD) Rev. A | Page 23 of 32 SSM2380 I2C INTERFACE The I2C interface provides access to the user-selectable control registers and operates with a 2-wire interface. SDA generates the serial control data-word, and SCK clocks the serial data. The I2C bus address (Bits[A7:A1]) is 0x31 (01100010 for write and 01100011 for read). Bit A0 is the designated read/write bit. Each control register consists of 16 bits, MSB first. Bits[B15:B9] are the register map address, and Bits[B8:B0] are the register data for the associated register map. SCK S START 1 TO 7 8 9 ADDR R/W ACK 8 1 TO 7 SUBADDRESS 9 1 TO 7 ACK DATA 8 9 P ACK STOP 08752-009 SDA Figure 49. SSM2380 2-Wire I2C Generalized Clocking Diagram WRITE SEQUENCE S A7 ... A1 A0 A(S) B15 ... B9 B8 A(S) B7 ... B0 A(S) P 0 DEVICE ADDRESS READ SEQUENCE S A7 ... A1 REGISTER ADDRESS A0 A(S) B15 ... B9 REGISTER DATA 0 A(S) S A7 ... A1 0 DEVICE ADDRESS A0 A(S) B7 ... B0 A(M) 0 ... 0 B8 A(M) P 1 REGISTER ADDRESS DEVICE ADDRESS 08752-010 S = START BIT. P = STOP BIT. A0 = I2C R/W BIT. A(S) = ACKNOWLEDGE BY SLAVE. A(M) = ACKNOWLEDGE BY MASTER. A(M) = ACKNOWLEDGE BY MASTER (INVERSION). REGISTER DATA (SLAVE DRIVE) Figure 50. I2C Write and Read Sequences Rev. A | Page 24 of 32 SSM2380 REGISTER MAP Table 11. Register Map Reg R0 Address 0x00 R1 0x01 R2 R3 R4 R5 R6 R7 R8 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Name Left channel gain control Right channel gain control Mode control ALC Control 1 ALC Control 2 Shutdown Error Error clear Reset Bit 7 LTOR Bit 6 LMUTE RTOL RMUTE 0 0 ALC_EN 0 0 0 0 0 0 0 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 LGAIN[5:0] Bit 1 Bit 0 RGAIN[5:0] EDGE[1:0] RTIME[2:0] COMP[1:0] ALC_VFIX 0 0 0 0 0 0 0 0 Rev. A | Page 25 of 32 OCREC 0 OCR 0 0 OTREC R2L LTIME[2:0] ALCLV[3:0] 0 STDNR OCL OTW 0 0 0 0 Default 00100010 00100010 L2R STDNL OTP 0 0 00001100 00101011 01001011 00000011 00000000 00000000 00000000 SSM2380 REGISTER MAP DETAILS REGISTER R0: LEFT CHANNEL GAIN CONTROL, ADDRESS 0x00 Bit 7 LTOR Bit 6 LMUTE Bit 5 Bit 4 Bit 3 Bit 2 LGAIN[5:0] Bit 1 Bit 0 Table 12. Left Channel Gain Control Register Bit Descriptions Bits 7 Bit Name LTOR 6 LMUTE [5:0] LGAIN[5:0] Description Left-to-right channel gain data load control. 0 = disable simultaneous loading of left channel gain data to left and right channel registers (default). 1 = enable simultaneous loading of left channel gain data to left and right channel registers. Left channel input mute. 0 = disable mute (default). 1 = enable mute on left channel amplifier. Left channel gain control. Each step represents a 0.5 dB increase in gain. For ALC operation, these bits control the gain setting for both the left and right channels. If the ALC_EN bit in Register R4 is set to 1, these bits cannot be changed. Setting Gain 000000 1 dB ... ... 100010 18 dB (default) ... ... 101101 23.5 dB 101110 to 111111 24 dB REGISTER R1: RIGHT CHANNEL GAIN CONTROL, ADDRESS 0x01 Bit 7 RTOL Bit 6 RMUTE Bit 5 Bit 4 Bit 3 Bit 2 RGAIN[5:0] Bit 1 Bit 0 Table 13. Right Channel Gain Control Register Bit Descriptions Bits 7 Bit Name RTOL 6 RMUTE [5:0] RGAIN[5:0] Description Right-to-left channel gain data load control. 0 = disable simultaneous loading of right channel gain data to left and right channel registers (default). 1 = enable simultaneous loading of right channel gain data to left and right channel registers. Right channel input mute. 0 = disable mute (default). 1 = enable mute on right channel amplifier. Right channel gain control. Each step represents a 0.5 dB increase in gain. If the ALC_EN bit in Register R4 is set to 1, these bits cannot be changed. Setting Gain 000000 1 dB ... ... 100010 18 dB (default) ... ... 101101 23.5 dB 101110 to 111111 24 dB Rev. A | Page 26 of 32 SSM2380 REGISTER R2: MODE CONTROL, ADDRESS 0x02 Bit 7 0 Bit 6 0 Bit 5 EDGE[1:0] Bit 4 Bit 3 OCREC Bit 2 OTREC Bit 1 R2L Bit 0 L2R Table 14. Mode Control Register Bit Descriptions Bits [5:4] Bit Name EDGE[1:0] 3 OCREC 2 OTREC 1 R2L 0 L2R Description Edge rate control. Setting Rate Control 00 Normal mode (default) 01 Slow edge 10 Slow edge (VDD > 3.0 V recommended) 11 Slow edge (VDD > 4.0 V recommended) Overcurrent autorecovery enable. 0 = disabled. 1 = enabled (default). Overtemperature autorecovery enable. 0 = disabled. 1 = enabled (default). Right channel signal mix enable (send right channel input to left and right channel outputs). 0 = mix disabled (default). 1 = mix enabled. Left channel signal mix enable (send left channel input to left and right channel outputs). 0 = mix disabled (default). 1 = mix enabled. REGISTER R3: ALC CONTROL 1, ADDRESS 0x03 Bit 7 0 Bit 6 0 Bit 5 Bit 4 RTIME[2:0] Bit 3 Table 15. ALC Control 1 Register Bit Descriptions Bits [5:3] Bit Name RTIME[2:0] [2:0] LTIME[2:0] Description Release time setting (0.5 dB step). Setting Release Time 000 4 ms/step (6 dB/48 ms) 001 8 ms/step 010 16 ms/step 011 32 ms/step 100 64 ms/step 101 128 ms/step (default) 110 256 ms/step 111 512 ms/step Attack time setting (0.5 dB step). Setting Attack Time 000 32 s/step (6 dB/384 s) 001 64 s/step 010 128 s/step 011 256 s/step (default) 100 512 s/step 101 1 ms/step 110 2 ms/step 111 4 ms/step Rev. A | Page 27 of 32 Bit 2 Bit 1 LTIME[2:0] Bit 0 SSM2380 REGISTER R4: ALC CONTROL 2, ADDRESS 0x04 Bit 7 ALC_EN Bit 6 Bit 5 COMP[1:0] Bit 4 ALC_VFIX Bit 3 Bit 2 Bit 1 ALCLV[3:0] Bit 0 Table 16. ALC Control 2 Register Bit Descriptions Bits 7 Bit Name ALC_EN [6:5] COMP[1:0] 4 ALC_VFIX [3:0] ALCLV[3:0] Description ALC enable (gain setting loaded to ALC control). 0 = disabled (default). 1 = enabled. Compressor setting. Setting Compression 00 Limiter mode (1:) 01 Compression Mode 1 (1:4 to 1:) 10 Compression Mode 2 (1:1.7 to 1:4 to 1:) (default) 11 Compression Mode 3 (1:2 to 1:2.5 to 1:) ALC threshold mode setting. 0 = supply tracking (default). 1 = fixed power. ALC threshold level setting. See Table 17 for a complete list of the settings (default value is 1011). Table 17. ALC Threshold Level Settings ALCLV[3:0] Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Supply Tracking Mode (ALC_VFIX = 0) % of VDD 96 93 90 88 85 83 80 78 76 74 72 70 69 67 66 64 Voltage Limit (V) 4.36 4.25 4.13 4.01 3.89 3.77 3.65 3.54 3.42 3.30 3.18 3.06 2.95 2.83 2.71 2.59 Fixed Power Mode (ALC_VFIX = 1) Power, 8 Load (W) Power, 4 Load (W) 1.19 2.38 1.13 2.25 1.06 2.13 1.0 2.01 0.95 1.89 0.89 1.78 0.83 1.67 0.78 1.56 0.73 1.46 0.68 1.36 0.63 1.27 0.59 1.17 0.54 1.09 0.50 1.00 0.46 0.92 0.42 0.84 Rev. A | Page 28 of 32 SSM2380 REGISTER R5: SHUTDOWN, ADDRESS 0x05 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 STDNR Bit 0 STDNL Bit 3 OCR Bit 2 OCL Bit 1 OTW Bit 0 OTP Bit 1 0 Bit 0 0 Bit 1 0 Bit 0 0 Table 18. Shutdown Register Bit Descriptions Bits 1 Bit Name STDNR 0 STDNL Description Right channel shutdown control. 0 = power up right channel. 1 = power down right channel (default). Left channel shutdown control. 0 = power up left channel. 1 = power down left channel (default). REGISTER R6: ERROR, ADDRESS 0x06 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Table 19. Error Register Bit Descriptions (Read-Only Register) Bits 3 Bit Name OCR 2 OCL 1 OTW 0 OTP Description Overcurrent error bit, right channel. 0 = no error detected (default). 1 = error state flagged (if OCREC bit in the mode control register is set to 1). Overcurrent error bit, left channel. 0 = no error detected (default). 1 = error state flagged (if OCREC bit in the mode control register is set to 1). Overtemperature warning bit. 0 = no error detected (default). 1 = warning state flagged (if OTREC bit in the mode control register is set to 1). Overtemperature error bit. 0 = no error detected (default). 1 = error state flagged (if OTREC bit in the mode control register is set to 1). REGISTER R7: ERROR CLEAR, ADDRESS 0x07 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Table 20. Error Clear Register Bit Descriptions Bits [7:0] Bit Name Error clear Description Recovery from error condition. Used when autorecovery is disabled. REGISTER R8: RESET, ADDRESS 0x08 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Table 21. Reset Register Bit Descriptions Bits [7:0] Bit Name Reset Description Clear all registers to their default values. Used when autorecovery is disabled. Rev. A | Page 29 of 32 SSM2380 OUTLINE DIMENSIONS 0.640 0.595 0.550 2.000 1.960 SQ 1.920 SEATING PLANE 4 3 2 1 A BALL 1 IDENTIFIER 0.340 0.320 0.300 B 0.50 REF C D 0.05 MAX COPLANARITY BOTTOM VIEW (BALL SIDE UP) 0.270 0.240 0.210 102609-B 0.345 0.330 0.315 TOP VIEW (BALL SIDE DOWN) Figure 51. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 SSM2380CBZ-REEL SSM2380CBZ-REEL7 EVAL-SSM2380Z 1 Temperature Range -40C to +85C -40C to +85C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 30 of 32 Package Option CB-16-3 CB-16-3 SSM2380 NOTES Rev. A | Page 31 of 32 SSM2380 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08752-0-2/11(A) Rev. A | Page 32 of 32