SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 FEATURES * * * * * * * * * * * Members of the Texas Instruments WidebusTM Family Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) SN54LVTH162373 . . . WD PACKAGE SN74LVTH162373 . . . DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE DESCRIPTION/ORDERING INFORMATION The 'LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ORDERING INFORMATION PACKAGE (1) TA Tube of 25 SSOP - DL Reel of 1000 -40C to 85C TSSOP - DGG Reel of 2000 VFBGA - GQL -55C to 125C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING SN74LVTH162373DL 74LVTH162373DLG4 SN74LVTH162373DLR LVTH162373 74LVTH162373DLRG4 SN74LVTH162373DGGR 74LVTH162373DGGRE4 LVTH162373 SN74LVTH162373KR VFBGA - ZQL (Pb-free) Reel of 1000 CFP - WD Tube 74LVTH162373ZQLR SNJ54LVTH162373WD LL2373 SNJ54LVTH162373WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1993-2006, Texas Instruments Incorporated SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. TERMINAL ASSIGNMENTS (1) GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E 1 2 3 4 5 6 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 F J 2Q7 2Q8 GND GND 2D8 2D7 G K 2OE NC NC NC NC 2LE H J K (1) NC - No internal connection FUNCTION TABLE (each 8-bit section) INPUTS 2 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Submit Documentation Feedback SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1 2OE 48 2LE C1 1D1 47 2 1D 24 25 C1 1Q1 2D1 36 13 1D To Seven Other Channels 2Q1 To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages. Absolute Maximum Ratings (1) over recommended operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 7 V -0.5 7 V -0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 -50 mA JA Package thermal impedance (4) Tstg (1) (2) (3) (4) mA 30 mA -50 mA DGG package 70 DL package 63 GQL/ZQL package 42 Storage temperature range -65 V 30 150 C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) SN54LVTH162373 SN74LVTH162373 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage range VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 VI Input voltage 5.5 5.5 V IOH High-level output current -12 -12 mA IOL Low-level output current 12 12 mA t/v Input transition rise or fall rate 10 10 ns/V t/VCC Power-up ramp rate 200 TA Operating free-air temperature -55 (1) 2 Outputs enabled 2 V -40 V s/V 200 125 V 85 C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54LVTH162373 SN74LVTH162373 MIN TYP (1) MIN TYP (1) MAX VIK VCC = 2.7 V, II = -18 mA VOH VCC = 3 V, IOH = -12 mA VOL VCC = 3 V, IOL = 12 mA 0.8 0.8 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 VI = VCC or GND 1 1 1 1 -5 -5 Control inputs VCC = 3.6 V, II Data inputs Ioff VCC = 3.6 V VCC = 0, 2 2 VI = VCC VI = 0 VI = 2 V V (2), 75 75 -75 -75 UNIT V V 100 VI = 0.8 V Data inputs VCC = 3.6 -1.2 VI or VO = 0 to 4.5 V VCC = 3 V II(hold) -1.2 MAX V A A A 500 -750 VI = 0 to 3.6 V 5 5 A -5 -5 A VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care 100 (3) 100 A IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care 100 (3) 100 A VCC = 3.6 V, IO = 0, VI = VCC or GND 0.19 0.19 ICC IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V IOZPU Outputs high Outputs low Outputs disabled 5 5 0.19 0.19 0.2 0.2 mA ICC (4) VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 3 3 pF Co VO = 3 V or 0 9 9 pF (1) (2) (3) (4) mA All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. On products compliant to MIL-PRF-38535, this parameter is not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Timing Requirements over operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH162373 VCC = 3.3 V 0.3 V MIN 4 tw Pulse duration, LE high tsu Setup time, data before LE th Hold time, data after LE MAX SN74LVTH162373 VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX 3 3 3 3 ns 1.3 0.6 1 0.6 ns 1 1.1 1 1.1 ns Submit Documentation Feedback SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH162373 PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ (1) FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q VCC = 3.3 V 0.3 V SN74LVTH162373 VCC = 3.3 V 0.3 V VCC = 2.7 V VCC = 2.7 V UNIT MAX MIN TYP (1) MAX 5 5.7 1.9 3.1 4.6 5.1 1.8 4.4 4.8 1.9 2.8 4 4.3 2.1 5.4 6.2 2.2 3.4 5.1 5.8 2.1 4.9 4.7 2.2 3.2 4.6 4.3 1.7 5.6 7 1.8 3.2 5.4 6.6 1.7 5.3 5.9 1.8 3.2 4.9 5.5 2.3 6.3 6.6 2.4 3.8 5.4 5.7 1 7.4 6.4 2.2 3.5 5.1 5 MIN MAX 1.8 MIN tsk(LH) 0.5 tsk(HL) 0.5 MIN MAX ns ns ns ns ns All typical values are at VCC = 3.3 V, TA = 25C. Submit Documentation Feedback 5 SN54LVTH162373,, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCBS261M - JULY 1993 - REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION 6V 500 W From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 W TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Input 1.5 V 1.5 V 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPLZ tPZL 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 2.7 V Output Control 1.5 V VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-9763801QXA ACTIVE CFP WD 48 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9763801QX A SNJ54LVTH16237 3WD 5962-9763801VXA ACTIVE CFP WD 48 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9763801VX A SNV54LVTH16237 3WD 74LVTH162373DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 74LVTH162373DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 74LVTH162373DLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 74LVTH162373DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 74LVTH162373ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 LL2373 SN74LVTH162373DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 SN74LVTH162373DL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 SN74LVTH162373DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH162373 SN74LVTH162373KR OBSOLETE BGA MICROSTAR JUNIOR GQL 56 TBD Call TI Call TI -40 to 85 LL2373 SNJ54LVTH162373WD ACTIVE CFP WD 48 TBD A42 N / A for Pkg Type -55 to 125 5962-9763801QX A SNJ54LVTH16237 3WD 1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVTH162373, SN54LVTH162373-SP, SN74LVTH162373 : * Catalog: SN74LVTH162373, SN54LVTH162373 * Enhanced Product: SN74LVTH162373-EP, SN74LVTH162373-EP * Military: SN54LVTH162373 * Space: SN54LVTH162373-SP NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74LVTH162373ZQLR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SN74LVTH162373DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74LVTH162373DLR SSOP Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVTH162373ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74LVTH162373DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVTH162373DLR SSOP DL 48 1000 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MCFP010B - JANUARY 1995 - REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA GDFP1-F56 and JEDEC MO -146AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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