5962-88764043A - Analog Devices, Inc.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

MOS High Speed

4- & 8-Channel 8-Bit ADCs

AD7824/AD7828

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2000

FUNCTIONAL BLOCK DIAGRAM

RDY CS RD

INT

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

THREE

STATE

DRIVERS

4-BIT

FLASH

ADC

(4LSB)

REF

(+)

TIMING AND CONTROL

CIRCUITRY

ADDRESS

LATCH

DECODE

AIN 1

AIN 4

AIN 8

MUX*

*AD7824 – 4-CHANNEL MUX

**AD7828 – 8-CHANNEL MUX

A2 – AD7828 ONLY

A0 A1 A2**

REF

(+)

REF

(–)

4-BIT

FLASH

ADC

(4MSB)

4-BIT

DAC

FEATURES

4- or 8-Analog Input Channels

Built-In Track/Hold Function

10 kHz Signal Handling on Each Channel

Fast Microprocessor Interface

Single 5 V Supply

Low Power: 50 mW

Fast Conversion Rate, 2.5 s/Channel

Tight Error Specification: 1/2 LSB

GENERAL DESCRIPTION

The AD7824 and AD7828 are high-speed, multichannel, 8-bit

ADCs with a choice of 4 (AD7824) or 8 (AD7828) multiplexed

analog inputs. A half-flash conversion technique gives a fast

conversion rate of 2.5 µs per channel and the parts have a built-

in track/hold function capable of digitizing full-scale signals of

10 kHz (157 mV/µs slew rate) on all channels. The AD7824 and

AD7828 operate from a single 5 V supply and have an analog

input range of 0 V to 5 V, using an external 5 V reference.

Microprocessor interfacing of the parts is simple, using standard

Chip Select (CS) and Read (RD) signals to initiate the conver-

sion and read the data from the three-state data outputs. The

half-flash conversion technique means that there is no need to

generate a clock signal for the ADC. The AD7824 and AD7828

can be interfaced easily to most popular microprocessors.

The AD7824 and AD7828 are fabricated in an advanced, all

ion-implanted, linear-compatible CMOS process (LC

MOS)

and have low power dissipation of 40 mW (typ). The AD7824

is available in a 0.3" wide, 24-lead “skinny” DIP, while the

AD7828 is available in a 0.6" wide, 28-lead DIP and in 28-

terminal surface mount packages.

PRODUCT HIGHLIGHTS

1. 4- or 8-channel input multiplexer gives cost-effective space-

saving multichannel ADC system.

2. Fast conversion rate of 2.5 µs/channel features a per channel

sampling frequency of 100 kHz for the AD7824 or 50 kHz

for the AD7828.

3. Built-in track-hold function allows handling of 4- or 8-

channels up to 10 kHz bandwidth (157 mV/µs slew rate).

4. Tight total unadjusted error spec and channel-to-channel

matching eliminate the need for user trims.

5. Single 5 V supply simplifies system power requirements.

6. Fast, easy-to-use digital interface allows connection to most

popular microprocessors with minimal external components.

No clock signal is required for the ADC.

REV. D

–2–

AD7824/AD7828–SPECIFICATIONS

(VDD = 5 V, VREF(+) = 5 V, VREF(–) = GND = O V unless otherwise

noted. All specifications TMIN to TMAX unless otherwise noted. Specifications apply for Mode 0.)

Parameter K Version

L Version B, T Versions C, U Versions Unit Conditions/Comments

ACCURACY

Resolution 8 8 8 8 Bits

Total Unadjusted Error

±1±1/2 ±1±1/2 LSB max

Minimum Resolution for which

No Missing Codes Are Guaranteed 8 8 8 8 Bits

Channel-to-Channel Mismatch ±1/4 ±1/4 ±1/4 ±1/4 LSB max

REFERENCE INPUT

Input Resistance 1.0/4.0 1.0/4.0 1.0/4.0 1.0/4.0 kΩ min/kΩ max

REF

(+) Input Voltage Range V

REF

(–)/ V

REF

(–)/ V

REF

(–)/ V

REF

(–)/ V min/V max

REF

(–) Input Voltage Range GND/ GND/ GND/ GND/ V min/V max

REF

(+) V

REF

(+) V

REF

(+) V

REF

(+)

ANALOG INPUT

Input Voltage Range V

REF

(–)/ V

REF

(–)/ V

REF

(–)/ V

REF

(– )/ V min/V max

REF

(+) V

REF

(+) V

REF

(+) V

REF

(+)

Input Leakage Current ±3±3±3±3µA max Analog Input Any Channel

Input Capacitance

45 45 45 45 pF typ 0 V to 5 V

LOGIC INPUTS

RD, CS, A0, A1 & A2

INH

2.4 2.4 2.4 2.4 V min

INL

0.8 0.8 0.8 0.8 V max

INH

111 1 µA max

INL

–1 –1 –1 –1 µA max

Input Capacitance

8 8 8 8 pF max Typically 5 pF

LOGIC OUTPUTS

DB0–DB7 & INT

4.0 4.0 4.0 4.0 V min I

SOURCE

= 360 µA

0.4 0.4 0.4 0.4 V max I

SINK

= 1.6 mA

OUT

(DB0–DB7) ±3±3±3±3µA max Floating State Leakage

Output Capacitance

8 8 8 8 pF max Typically 5 pF

RDY

OL4

0.4 0.4 0.4 0.4 V max I

SINK

= 2.6 mA

OUT

±3±3±3±3µA max Floating State Leakage

Output Capacitance 8 8 8 8 pF max Typically 5 pF

SLEW RATE, TRACKING

0.7 0.7 0.7 0.7 V/µs typ

0.157 0.157 0.157 0.157 V/µs max

POWER SUPPLY

5 5 5 5 Volts ±5% for Specified

Performance

DD5

16 16 20 20 mA max CS = RD = 2.4 V

Power Dissipation 50 50 50 50 mW typ

80 80 100 100 mW max

Power Supply Sensitivity ±1/4 ±1/4 ±1/4 ±1/4 LSB max ±1/16 LSB typ

= 5 V ± 5%

NOTES

Temperature ranges are as follows: K, L Versions; 0°C to 70°C

B, C Versions; –40°C to +85°C

T, U Versions; –55°C to +125°C

Total Unadjusted Error includes offset, full-scale and linearity errors.

Sample tested at 25°C by Product Assurance to ensure compliance.

RDY is an open drain output.

See Typical Performance Characteristics.

Specifications subject to change without notice.

AD7824/AD7828

REV. D –3–

TIMING CHARACTERISTICS

(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V unless otherwise noted)

Limit at Limit at

Limit at 25CT

MIN

, T

MAX

MIN

, T

MAX

Parameter (All Grades) (K, L, B, C Grades) (T, U Grades) Unit Conditions/Comments

CSS

0 0 0 ns min CS to RD Setup Time

CSH

0 0 0 ns min CS to RD Hold Time

0 0 0 ns min Multiplexer Address Setup Time

30 35 40 ns min Multiplexer Address Hold Time

RDY2

40 60 60 ns max CS to RDY Delay. Pull-Up

Resistor 5 kΩ.

CRD

2.0 2.4 2.8 µs max Conversion Time, Mode 0

ACC13

85 110 120 ns max Data Access Time after RD

ACC23

50 60 70 ns max Data Access Time after INT, Mode 0

lNTH2

40 65 70 ns typ RD to INT Delay

75 100 100 ns max

DH4

60 70 70 ns max Data Hold Time

500 500 600 ns min Delay Time between Conversions

60 80 80 ns min Read Pulsewidth, Mode 1

600 500 400 ns max

NOTES

Sample tested at 25°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10 % to 90% of 5 V) and timed from a voltage level of 1.6 V.

= 50 pF.

Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

Specifications subject to change without notice.

Test Circuits

Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test

AD7824/AD7828

REV. D

–4–

Operating Temperature Range

Commercial (K, L Versions) . . . . . . . . . . . . . . 0°C to 70°C

Industrial (B, C Versions) . . . . . . . . . . . . . –25°C to +85°C

Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C

Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

= 25°C unless otherwise noted)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

Digital Input Voltage to GND

(RD, CS, A0, A1 & A2) . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

Digital Output Voltage to GND

(DB0, DB7, RDY & INT) . . . . . . . . . . –0.3 V, V

+ 0.3 V

REF

(+) to GND . . . . . . . . . . . . . . . . . . V

REF

(–), V

+ 0.3 V

REF

(–) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

REF

(+)

Analog Input (Any Channel) . . . . . . . . . . –0.3 V, V

+ 0.3 V

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP/SOIC/SSOP

PLCC

LCCC

ORDERING GUIDE

Total

Temperature Unadjusted Package

Model Range Error (LSBs) Option

AD7824KN 0°C to 70°C±1 N-24

AD7824LN 0°C to 70°C±1/2 N-24

AD7824KR 0°C to 70°C±1 R-24

AD7824BQ –40°C to +85°C±1 Q-24

AD7824CQ –40°C to +85°C±1/2 Q-24

AD7824TQ*–55°C to +125°C±1 Q-24

AD7824UQ*–55°C to +125°C±1/2 Q-24

AD7828KN 0°C to 70°C±1 N-28

AD7828LN 0°C to 70°C±1/2 N-28

AD7828KP 0°C to 70°C±1 P-28A

AD7828LP 0°C to 70°C±1/2 P-28A

AD7828BQ –40°C to +85°C±1 Q-28

AD7828CQ –40°C to +85°C±1/2 Q-28

AD7828BR –40°C to +85°C +1 R-28

AD7828BRS –40°C to +85°C +1 RS-28

AD7828TQ*–55°C to +125°C±1 Q-28

AD7828UQ*–55°C to +125°C±1/2 Q-28

AD7828TE*–55°C to +125°C±1 E-28A

AD7828UE*–55°C to +125°C±1/2 E-28A

*Available to /883B processing only. Contact our local sales office for military

data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing

#5692-88764.

WARNING!

ESD SENSITIVE DEVICE

Typical Performance Characteristics–AD7824/AD7828

REV. D –5–

TPC 1. Conversion Time vs. Temperature

TPC 2. Accuracy vs. V

REF

= V

REF

(+) – V

REF

(–)]

TPC 3. Signal-Noise Ratio vs. Input Frequency

TPC 4. Power Supply Current vs. Temperature

(Not Including Reference Ladder)

TPC 5. Accuracy vs. t

TPC 6. Output Current vs. Temperature

AD7824/AD7828

REV. D

–6–

OPERATIONAL DIAGRAM

The AD7824 is a 4-channel 8-bit A/D converter and the

AD7828 is an 8-channel 8-bit A/D converter. Operational dia-

grams for both of these devices are shown in Figures 3 and 4.

The addition of just a 5 V reference allows the devices to

perform the analog-to-digital function.

Figure 3. AD7824 Operational Diagram

Figure 4. AD7828 Operational Diagram

CIRCUIT INFORMATION

BASIC DESCRIPTION

The AD7824/AD7828 uses a half-flash conversion technique

whereby two 4-bit flash A/D converters are used to achieve an

8-bit result. Each 4-bit flash ADC contains 15 comparators

which compare the unknown input to a reference ladder to get

a 4-bit result. For a full 8-bit reading to be realized, the upper

4-bit flash, the most significant (MS) flash, performs a conver-

sion to provide the 4 most significant data bits. An internal

DAC, driven by the 4 MSBs, then recreates an analog approxi-

mation of the input voltage. This analog result is subtracted

from the input, and the difference is converted by the lower

flash ADC, the least significant (LS) flash, to provide the 4 least

significant bits of the output data.

APPLYING THE AD7824/AD7828

REFERENCE AND INPUT

The two reference inputs on the AD7824/AD7828 are fully dif-

ferential and define the zero to full-scale input range of the A/D

converter. As a result, the span of the analog input voltage for

all channels can easily be varied. By reducing the reference

span, V

REF

(+) – V

REF

(–), to less than 5 V the sensitivity of the

converter can be increased (e.g., if V

REF

= 2 V then 1 LSB =

7.8 mV). The input/reference arrangement also facilitates ratio-

metric operation.

This reference flexibility also allows the input channel voltage

span to be offset from zero. The voltage at V

REF

(–) sets the

input level for all channels which produces a digital output of

all zeroes. Therefore, although the analog inputs are not them-

selves differential, they have nearly differential-input capability

in most measurement applications because of the reference

design. Figures 5 to 7 show some of the configurations that are

possible.

Figure 5. Power Supply as Reference

Figure 6. External Reference Using the AD580, Full-Scale

Input is 2.5 V

Figure 7. Input Not Referenced to GND

AD7824/AD7828

REV. D –7–

INPUT CURRENT

Due to the novel conversion techniques employed by the AD7824/

AD7828, the analog input behaves somewhat differently than in

conventional devices. The ADC’s sampled-data comparators

take varying amounts of input current depending on which cycle

the conversion is in.

The equivalent input circuit of the AD7824/AD7828 is shown

in Figure 8. When a conversion starts (CS and RD going low),

all input switches close, and the selected input channel is con-

nected to the most significant and least significant comparators.

Therefore, the analog input is connected to thirty-one 1 pF

input capacitors at the same time.

Figure 8. AD7824/AD7828 Equivalent Input Circuit

The input capacitors must charge to the input voltage through

the on resistance of the analog switches (about 3 kΩ to 6 kΩ). In

addition, about 14 pF of input stray capacitance must be charged.

The analog input for any channel can be modelled as an RC

network as shown in Figure 9. As R

increases, it takes longer

for the input capacitance to charge.

Figure 9. RC Network Model

The time for which the input comparators track the analog input

is approximately 1 µs at the start of conversion. Because of input

transients on the analog inputs, it is recommended that a source

impedance of not greater than 100 ohms be connected to the

analog inputs. The output impedance of an op amp is equal to

the open loop output impedance divided by the loop gain at the

frequency of interest. It is important that the amplifier driving

the AD7824/AD7828 analog inputs have sufficient loop gain at the

input signal frequency as to make the output impedance low.

Suitable op amps for driving the AD7824/AD7828 are the

AD544 or AD644.

INHERENT SAMPLE-HOLD

A major benefit of the AD7824’s and AD7828’s analog input

structure is its ability to measure a variety of high-speed signals

without the help of an external sample-and-hold. In a conven-

tional SAR type converter, regardless of its speed, the input

must remain stable to at least 1/2 LSB throughout the conver-

sion process if rated accuracy is to be maintained. Consequently,

for many high-speed signals, this signal must be externally

sampled and held stationary during the conversion. The

AD7824/AD7828 input comparators, by nature of their

input switching inherently accomplish this sample-and-hold

function. Although the conversion time for AD7824/AD7828

is 2 µs, the time for which any selected analog input must be

1/2 LSB stable is much smaller. The AD7824/AD7828 tracks

the selected input channel for approximately 1 µs after conver-

sion start. The value of the analog input at that instant (1 µs from

conversion start) is the measured value. This value is then used

in the least significant flash to generate the lower 4-bits of data.

SINUSOIDAL INPUTS

The AD7824/AD7828 can measure input signals with slew rates

as high as 157 mV/µs to the rated specifications. This means that

the analog input frequency can be up to 10 kHz without the aid

of an external sample and hold. Furthermore, the AD7828 can

measure eight 10 kHz signals without a sample and hold. The

Nyquist criterion requires that the sampling rate be twice the

input frequency (i.e., 2 × 10 kHz). This requires an ideal anti-

aliasing filter with an infinite roll-off. To ease the problem of

antialiasing filter design, the sampling rate is usually much greater

than the Nyquist criterion. The maximum sampling rate (F

MAX

)

for the AD7824/AD7828 can be calculated as follows:

MAX

tCRD +tP

MAX

2E–6+0.5E–6

= 400 kHz

CRD

= AD7824/AD7828 Conversion Time

= Minimum Delay Between Conversion

This permits a maximum sampling rate of 50 kHz for each of

the 8 channels when using the AD7828 and 100 kHz for each of

the 4 channels when using the AD7824.

AD7824/AD7828

REV. D

–8–

UNIPOLAR OPERATION

The analog input range for any channel of the AD7824/ AD7828

is 0 V to 5 V as shown in the unipolar operational diagram of Fig-

ure 10. Figure 11 shows the designed code transitions which

occur midway between successive integer LSB values (i.e.,

1/2 LSB, 3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is

Natural Binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.

Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation

Figure 11. Ideal Input/Output Transfer Characteristic for

Unipolar 0 V to 5 V Operation

BIPOLAR OPERATION

The circuit of Figure 12 is designed for bipolar operation. An

AD544 op-amp conditions the signal input (V

) so that only

positive voltages appear at AIN 1. The closed loop transfer

function of the op amp for the resistor values shown is given

below:

AIN 1 = (2.5 – 0.625 V

) Volts

The analog input range is ±4 V and the LSB size is 31.25 mV.

The output code is complementary offset binary. The ideal

input/output characteristic is shown in Figure 13.

Figure 12. AD7824/AD7828 Bipolar

4 V Operation

Figure 13. Ideal Input/Output Transfer Characteristic for

4 V Operation

TIMING AND CONTROL

The AD7824/AD7828 has two digital inputs for timing and

control. These are Chip Select (CS) and Read (RD). A READ

operation brings CS and RD low which starts a conversion on

the channel selected by the multiplexer address inputs (see

Table I). There are two modes of operation as outlined by the

timing diagrams of Figures 14 and 15. Mode 0 is designed for

microprocessors which can be driven into a WAIT state. A

READ operation (i.e., CS and RD are taken low) starts a con-

version and data is read when conversion is complete. Mode l

does not require microprocessor WAIT states. A READ operation

initiates a conversion and reads the previous conversion results.

Table I. Truth Table for Input Channel Selection

AD7824 AD7828

A1 A0 A2 A1 A0 Channel

00 000 AIN 1

01 001 AIN 2

10 010 AIN 3

11 011 AIN 4

100 AIN 5

101 AIN 6

110 AIN 7

111 AIN 8

AD7824/AD7828

REV. D –9–

MODE 0

Figure 14 shows the timing diagram for Mode 0 operation. This

mode can only be used for microprocessors which have a WAIT

state facility, whereby a READ instruction cycle can be extended to

accommodate slow memory devices. A READ operation brings

CS and RD low which starts a conversion. The analog multiplexer

address inputs must remain valid while CS and RD are low.

The data bus (DB7–DB0) remains in the three-state condition

until conversion is complete. There are two converter status

outputs on the AD7824/AD7828, interrupt (INT) and ready

(RDY) which can be used to drive the microprocessor READY/

WAIT input. The RDY is an open drain output (no internal

pull-up device) which goes low on the falling edge of CS and

goes high impedance at the end of conversion, when the 8-bit

conversion result appears on the data outputs. If the RDY status

is not required, then the external pull-up resistor can be omitted

and the RDY output tied to GND. The INT goes low when

conversion is complete and returns high on the rising edge of

CS or RD.

MODE 1

Mode 1 operation is designed for applications where the micro-

processor is not forced into a WAIT state. A READ operation

takes CS and RD low which triggers a conversion (see Figure

15). The multiplexer address inputs are latched on the rising

edge of RD. Data from the previous conversion is read from the

three-state data outputs (DB7–DB0). This data may be disre-

garded if not required. Note, the RDY output (open drain out-

put) does not provide any status information in this mode and

must be connected to GND. At the end of conversion INT

goes low. A second READ operation is required to access the

new conversion result. This READ operation latches a new

address into the multiplexer inputs and starts another conversion.

INT returns high at the end of the second READ operation,

when CS or RD returns high. A delay of 2.5 µs must be allowed

between READ operations.

Figure 14. Mode 0 Timing Diagram

Figure 15. Mode 1 Timing Diagram

AD7824/AD7828

REV. D

–10–

MICROPROCESSOR INTERFACING

The AD7824/AD7828 is designed to interface to microproces-

sors as Read Only Memory (ROM). Analog channel selection,

conversion start and data read operations are controlled by CS,

RD and the channel address inputs. These signals are common

to all memory peripheral devices.

Z80 MICROPROCESSOR

Figure 16 shows a typical AD7824/AD7828–Z80 interface. The

AD7824/AD7828 is operating in Mode 0. Assume the ADC is

assigned a memory block starting at address C000. The follow-

ing LOAD instruction to any of the addresses listed in Table II

will start a conversion of the selected channel and read the con-

version result.

LD B, (C000)

At the beginning of the instruction cycle when the ADC ad-

dress is selected, RDY asserts the WAIT input, so that the Z80

is forced into a WAIT state. At the end of conversion RDY

returns high and the conversion result is placed in the B register

of the microprocessor.

Figure 16. AD7824/AD7828–Z80 lnterface

Table II. Address Channel Selection

AD7824 AD7828

Address Channel Channel

C000 1 1

C001 2 2

C002 3 3

C003 4 4

C004 5

C005 6

C006 7

C007 8

MC68000 MICROPROCESSOR

Figure 17 shows a MC68000 interface. The AD7824/AD7828

is operating in Mode 0. Assume the ADC is again assigned a

memory block starting at address C000. A MOVE instruction

to any of the addresses in Table II starts a conversion and reads

the conversion result.

MOVE•B $C000,D0

Once conversion has begun, the MC68000 inserts WAIT states,

until INT goes low asserting DTACK at the end of conversion.

The microprocessor then places the conversion results in the

D0 register.

Figure 17. AD7824/AD7828–MC68000 Interface

TMS32010 MICROCOMPUTER

A TMS32010 interface is shown in Figure 18. The AD7824/

AD7828 is operating in Mode 1 (i.e., no µP WAIT states). The

ADC is mapped at a port address. The following I/O instruction

starts a conversion and reads the previous conversion result into

the accumulator.

IN, A PA (PA = PORT ADDRESS)

The port address (000 to 111) selects the analog channel to be

converted. When conversion is complete a second I/O instruc-

tion (IN, A PA) reads the up-to-date data into the accumulator

and starts another conversion. A delay of 2.5 µs must be allowed

between conversions.

Figure 18. AD7824/AD7828–TMS32010 Interface

AD7824/AD7828

REV. D –11–

BANDPASS

FILTER 1

BANDPASS

FILTER 2

BANDPASS

FILTER 7

BANDPASS

FILTER 8

AMP

SPEECH

INPUT

AIN 1

AIN 2

AIN 7

AIN 8

VDD

VREF(–)

VREF(+)

+5V

GND

+5V

DB7

DB0

DATA

AD7828

Figure 19. Speech Analysis Using Real-Time Filtering

VDD

GND

+5V

CS RD

AIN 1

AIN 2

AIN 3

AIN 4

VREF(+)

VREF(–)

AD7824

INT

DB7

DB0

DB7

DB0

VOUT A

AGND

DGND

VOUT B

VOUT C

VOUT D

AD7226

VSS

VDD

+15V

VO1

VO2

VO3

VO4

SAMPLE

PULSE

VREF

+10V

Figure 20. 4-Channel Fast Infinite Sample-and-Hold

24-Lead Plastic DIP (N-24)

112

PIN 1

1.228 (31.19)

1.226 (31.14)

0.260  0.001

(6.61  0.03)

0.130 (3.30)

0.128 (3.25)

SEATING

PLANE

0.07 (1.78)

0.05 (1.27)

0.02 (0.5)

0.016 (0.41)

0.11 (2.79)

0.09 (2.28)

0.011 (0.28)

0.009 (0.23)

0.32 (8.128)

0.30 (7.62)

15

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN/LEAD PLATED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

24-Lead Cerdip (Q-24)

112

PIN 1

0.295

(7.493)

MAX

1.290 (32.77) MAX

15°

0°

0.320 (8.128)

0.290 (7.366)

0.012 (0.305)

0.008 (0.203)

TYP

0.180

(4.572)

MAX

SEATING

PLANE

0.225

(5.715)

MAX

0.110 (2.794)

0.090 (2.286)

TYP

0.021 (0.533)

0.015 (0.381)

TYP

0.065 (1.651)

0.055 (1.397)

0.125

(3.175)

MIN

0.070 (1.778)

0.020 (0.508)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

CERDIP LEADS WILL BE EITHER TIN/LEAD PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Small Outline Package (R-24)

0.0125 (0.32)

0.0091 (0.23)

8

0

0.0291 (0.74)

0.0098 (0.25) 45

0.0500 (1.27)

0.0157 (0.40)

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.0500

(1.27)

BSC

24 13

121

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

0.6141 (15.60)

0.5985 (15.20)

28-Lead Plastic DIP (N-28)

0.012 (0.305)

0.008 (0.203)

0.606 (15.4)

0.594 (15.09)

15

0

114

PIN 1

0.55 (13.97)

0.53 (13.47)

1.45 (36.83)

1.44 (36.58)

SEATING

PLANE

0.16 (4.07)

0.15 (3.56)

0.2

(5.08)

MAX

0.02 (0.508)

0.015 (0.381)

0.175 (4.45)

0.12 (3.05)

0.065 (1.66)

0.045 (1.15)

0.105 (2.67)

0.095 (2.42)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN/LEAD PLATED

IN ACCORDANCE WITH MIL-M-38510 RE

UIREMENTS

NOTE

Analog Devices reserves the right to ship either cerdip (Q-24, Q-28)

or ceramic (D-24A, D-28) hermetic packages.

AD7824/AD7828

REV. D

–12–

28-Lead Cerdip (Q-28)

114

0.525 (13.33)

0.515 (13.08)

PIN 1

1.490 (37.84) MAX

15°

0°

0.62 (15.74)

0.59 (14.93)

0.012 (0.305)

0.008 (0.203)

0.18

(4.57)

MAX

SEATING

PLANE

0.22

(5.59)

MAX

0.11 (2.79)

0.099 (2.28)

0.02 (0.5)

0.016 (0.406)

0.06 (1.52)

0.05 (1.27)

GLASS SEALANT

0.125

(3.175)

MIN

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

28-Lead Small Outline Package (R-28)

0.0125 (0.32)

0.0091 (0.23)

8

0

0.0291 (0.74)

0.0098 (0.25) 45

0.0500 (1.27)

0.0157 (0.40)

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.0500

(1.27)

BSC

28 15

141

0.7125 (18.10)

0.6969 (17.70)

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

28-Lead Shrink Small Outline Package (RS-28)

0.009 (0.229)

0.005 (0.127)

0.03 (0.762)

0.022 (0.558)

8°

0°

0.008 (0.203)

0.002 (0.050)

0.07 (1.79)

0.066 (1.67)

0.078 (1.98)

0.068 (1.73)

0.015 (0.38)

0.010 (0.25) SEATING

PLANE

0.0256

(0.65)

BSC

0.311 (7.9)

0.301 (7.64)

0.212 (5.38)

0.205 (5.21)

28 15

141

0.407 (10.34)

0.397 (10.08)

PIN 1

28-Terminal LCCC (E-28A)

BOTTOM

VIEW

19 25

0.028 (0.71)

0.022 (0.56)

0.055 (1.40)

0.045 (1.14)

0.020  45

(0.51  45)

REF

0.075 (1.91)

REF

0.050  0.005

(1.27  0.13) NO. 1 PIN

INDEX

0.040  45

(1.02  45)

REF 3 PLCS

0.458 (11.63)

0.442 (11.23)

0.100 (2.54)

0.064 (1.63)

THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS

APPLIES TO ALL FOUR SIDES

ALL TERMINALS ARE GOLD PLATED

NOTE

Analog Devices reserves the right to ship either cerdip (Q-24, Q-28)

or ceramic ( D-24A, D-28) hermetic packages.

C01323c–0–8/00 (rev. D)

PRINTED IN U.S.A.

28-Leaded PLCC (P-28A)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.495 (12.57)

0.485 (12.32)SQ

0.456 (11.582)

0.450 (11.430)

0.050  0.005)

(1.27  0.13)

0.021 (0.533)

0.013 (0.331)

0.430 (10.5)

0.390 (9.9)

0.032 (0.812)

0.026 (0.661)

0.180 (4.51)

0.165 (4.20)

0.120 (3.04)

0.090 (2.29)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Package/Price Information

For detailed packaging information, please select the Datasheets button.

High Speed , 8-Channel, 8-Bit CMOS ADC

Model Status Package

Description Pin

Count Temperature

Range Price*

(100-499)

5962-8876403XX PRODUCTION CERDIP GLASS SEAL 28 MILITARY $64.68

5962-88764043A PRODUCTION CER. LEADLESS CHIP

CARRIER 28 MILITARY $161.04

5962-8876404XX PRODUCTION CERDIP GLASS SEAL 28 MILITARY $80.52

AD7828BCHIPS PRODUCTION NO CONVERSION DATA

FROM COS - COMMERCIAL $10.95

AD7828BQ PRODUCTION CERDIP GLASS SEAL 28 INDUSTRIAL $19.75

AD7828BR PRODUCTION STD S.O. PKG (SOIC) 28 INDUSTRIAL $10.96

AD7828BR-REEL PRODUCTION STD S.O. PKG (SOIC) 28 INDUSTRIAL -

AD7828CQ PRODUCTION CERDIP GLASS SEAL 28 INDUSTRIAL $25.25

AD7828KN PRODUCTION PLASTIC/EPOXY DIP 28 COMMERCIAL $10.95

AD7828KP PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL $12.50

AD7828KP-REEL PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL -

AD7828LN PRODUCTION PLASTIC/EPOXY DIP 28 COMMERCIAL $14.95

AD7828LP PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL $17.00

AD7828LP-REEL PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL -

AD7828LRS PRE-RELEASE SHRINK SO PACKAGE 28 COMMERCIAL $10.95

AD7828LRS-REEL PRODUCTION SHRINK SO PACKAGE 28 COMMERCIAL -

* This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit the

stated volume. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing. View

Pricing and Availability (currently available to North American customers) for further information.

Analog Products -- AD7828

file:///F|/cpl_new_images/AD7828.html [7/17/2001 4:35:42 PM]

Package/Price Information

For detailed packaging information, please select the Datasheets button.

High Speed , 8-Channel, 8-Bit CMOS ADC

Model Status Package

Description Pin

Count Temperature

Range Price*

(100-499)

5962-8876403XX PRODUCTION CERDIP GLASS SEAL 28 MILITARY $64.68

5962-88764043A PRODUCTION CER. LEADLESS CHIP

CARRIER 28 MILITARY $161.04

5962-8876404XX PRODUCTION CERDIP GLASS SEAL 28 MILITARY $80.52

AD7828BCHIPS PRODUCTION NO CONVERSION DATA

FROM COS - COMMERCIAL $10.95

AD7828BQ PRODUCTION CERDIP GLASS SEAL 28 INDUSTRIAL $19.75

AD7828BR PRODUCTION STD S.O. PKG (SOIC) 28 INDUSTRIAL $10.96

AD7828BR-REEL PRODUCTION STD S.O. PKG (SOIC) 28 INDUSTRIAL -

AD7828CQ PRODUCTION CERDIP GLASS SEAL 28 INDUSTRIAL $25.25

AD7828KN PRODUCTION PLASTIC/EPOXY DIP 28 COMMERCIAL $10.95

AD7828KP PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL $12.50

AD7828KP-REEL PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL -

AD7828LN PRODUCTION PLASTIC/EPOXY DIP 28 COMMERCIAL $14.95

AD7828LP PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL $17.00

AD7828LP-REEL PRODUCTION PLASTIC LEAD CHIP

CARRIER 28 COMMERCIAL -

AD7828LRS PRE-RELEASE SHRINK SO PACKAGE 28 COMMERCIAL $10.95

AD7828LRS-REEL PRODUCTION SHRINK SO PACKAGE 28 COMMERCIAL -

* This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit the

stated volume. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing. View

Pricing and Availability (currently available to North American customers) for further information.

Analog Products -- AD7828

file:///F|/cpl_new_images/AD7828.html [7/17/2001 4:35:42 PM]