V23816-N1018-L312 - Infineon Technologies

Fiber Optics MAY 2001

V23816-N1018-C312/L312(*)

3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder

OC-48 SONET/SDH Short Reac h (SR) up to 2 km

Preliminary

FEATURES

• Compliant with existing stand ards

• Compact integrated transponder unit with

– FP laser diode transmitter

– InGaAs PIN ph otodiode receiver

– Pigtailed optical connections

– Integrated Mux, Demux and Clock Recovery

• Class 1 FDA and IEC laser s afety compliant

• Single +3.3 V power supply

• OC-48 optical transmit and receive at 2488.32 Mbit/s

• 4-line LVDS differe ntial interface at 622. 08 Mbit/s

• Exte rnal c ontr o l for laser shutoff

• Loss of optical signal and Loss of synch indicators (RX)

• Loss of lock indicator for TX high speed clock

•Laser bias monitor

• RX power monitor output

• Loopback operating modes

• 155.520 MHz LVPECL input TX reference clock

• 2.8 W Typical Power Consumption

• TX Fault output indicator

ABSOLUTE MAXIMUM RATINGS

Oper at ion b e y ond t hes e rat ing s ma y ca use perma ne nt dam age

to the transponder.

Supply Voltage (V CC)....................................................0 to 4.0 V

LVDS Input Levels..........................................................0 to VCC

LVPECL Input Level ...................................................... 0 to VCC

LVTTL Input Level........................................................0 to 5.5 V

LVDS Output Source Current............................................. 5 mA

LVPECL Output Sourc e Cur r en t...................... ...... ..... ...... 24 mA

LVTTL Output Source Current ........................................... 1 mA

Operating Ambient Temperature................................0 to 70 oC

Storage Ambient Temperature ............................... –40 to 85 °C

Static Discharge Volt age, All Pins................................... 1000 V

(*) Orderi ng Infor m a tion

Dimensions in mm [inches] V23816-N1018-L312

Connector type Fiber length Part number

SC 24.1 ±0.8 “ V23816-N1018-C312

LC 24.1 ±0.8 “ V23816-N1018-L312

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

DESCRIPTION

The Infine on single mode SONET/SDH t ransponder is compli-

ant with the Bellcore GR-253, ITU-T G.957, and ITU-T G.958

specifications. The transmitter section consists of a multiplexer

(Mux), laser driver , F abry Perot (FP) laser diode and pigtail single

mode fiber with LC/PC or SC/PC 0 ° termination. The receiver

section consists of a multimode fiber pigtail with LC/PC or SC/

PC termination, a packaged PIN photodiode and preamplifier,

postamplifier, clock and data recovery (CDR), and a demulti-

plexer (Demux). The Mux and Demux functions are integrated

together onto a single Transceiver IC. The 622.08 MHz parallel

data int er f ace fre es t he us er fr om the c onc erns of pc b la y ou t at

2.5 Gb/s. The pluggable connector blind mates easily to the

customer pcb, and all ows the trans ponder to be removed prior

to any solder reflow or washing of the users pcb.

The transponder operates from a single +3.3 V power supply.

The electrical interface is via a 60 pin pluggable connec tor. The

transmit and receive electrical signals each consist of 4 parallel

differential LVDS data, and a differentia l LVDS clock. The trans-

mit input data and clock lines, and the receive output data and

clock lines, are al l internal l y biased a nd te rmi n a te d. All line s are

DC coupled to the interface connector.

The transponder is designed to transmit an d re ceive serial OC-

48 (2488.32 Mb/s) data over standard non-dispersion-shifted

single mode fiber at a wavelength of 1310 nm.

Transmitter (Mux Section)

Please refer to the transponder block diagram.

The transmitter accepts a 4 bit wide parallel in put data word,

TXD A T AP/N[3:0], at a 622.08 Mb/s data rate. The TX input clock,

TXCLKP/N, is synchronous with the incoming data, at a fre-

quency of 622.08 MHz. This clock is used to load the data into a

4-bit latch. Th e data is read in on the rising edge of the positive

input clock. (See TX Input Timing Diagram).

A reference input clock, REFCLKP/N, at 155.52 MHz, is sup-

plied as a reference inpu t to the high speed Clock Synthes izer.

The high speed output of the clock synthesizer will clock the

Timing Generator and the Parallel-to-Serial Converter. The Paral-

lel-to-Serial Conv erter will output the retimed data as a serial bit

stream, TSDP/N, at 2488.32 Mb/s data rate. Bit 3 of the

TXDATAP/N parallel input word is the MSB, and is transmitted

first in the data stream. Bit 0, the LSB, is transmitted last.

The output of the high speed Clock Synthesizer, which is inter-

nally set to 2488.32 MHz, is tapped off the Timing Generator,

and is divided to 622.08 MHz. This output (PCLKP/N) is

intended to be used as a reference clock for TX upstream logic.

The PHASE_INITP/N input signal is used to realign the internal

timing of the Timing Generator by resetting and centering the

FIFO in the Transceiver IC. The realignment will occur on the ris-

ing ed ge of PHASE_INITP, which must be held high for at least

10 ns.

The PHASE_ERRP/ N output will pulse high during each clock

cycle when there is a potential set-up & hold timing violation

between the internal byte clock and the TXCLKP/N input, indi-

cating that PHASE_INITP/N must be strobed.

If the R ef erence Cloc k input, REFCLKP/N, i s derived fro m and is

synchronous with the TX Byte Clock, TXCLKP/N, then there

should never be any short setup and hold times between the

two timing domains, and the FIFO should never need to be

recentered. However, if the REFCLKP/N input is, for instance,

produced by a free running oscillator, then such potential viola-

tions may e xist. When FIFO realignment occurs, up to 10 bytes

of data will be lost. Automatic FIFO realignment can be enabled

by simply connecting the PHA SE_ERRP/N output directly to th e

PHAS EINITP/N input. T he us er can also take the PHA S E_E RRP/

N outp ut, pr oce ss it a nd send a sig nal to the PHA SE_ INI TP/N in

such a way that idle bytes are lost during the realignment pro-

cess.

The TX Clock Synthesizer section provides a lock alarm output

signal, TXLOCK, which indicates if the clock synthesizer is prop-

erly phase locked.

Transmitter (Electro-Optical Section)

T h e s eri a l d a ta ou t put , TSD P/N , of t he Transcei ver IC is in p ut t o

a las er d riv er IC. The la ser driv e r p ro vid es b ot h bia s an d mod ula -

tion to a laser diode. The laser bias current is controlled by a

closed-loop circuit, which regula tes the output average power

of the lase r o v er co ndit ions of t emp era t ur e an d ag in g. The Mon -

itor PIN diode, which is mechanically built into the laser, pro-

vides a feedback signal to the laser driver, and prevents the

lase r power from exceeding the factory preset opera ting limits.

The laser driver includes an eye saf ety feat ure that will automat-

ically shut off power to the laser if a fault con dition occurs

which causes excessively high laser bias current or excessively

high average output pow er. Such a fault will be indicated on the

TX_FAULT output . The faul t can be cleared by cycling DC

power, or by strobing the RESET_L input.

The M ux and Laser Driver can be r eset with the RESE T_L input.

During the time that RESET_L is held active, there will be no

optical output from the transmitter. The RESET_L input will

clear any fault indication that has occu rred on the T X_FAULT

output.

The laser can be switched off at any time with the

LASER_DISABLE input.

The TX_BIASMON outp ut is provided as an alarm to indicate if

the laser bias current is outside of the normal operating range.

This output can be used to monitor the aging of the laser.

The laser diode is a Fabry-Perot type, which, due to the cavity

nature of its design, will emit li ght at several longitudinal wave-

lengths, or modes centered about 1310 nm. This type of laser is

suitable f or the short reach tr ansmission ov er single-mode fiber

that this transponder is intended for. The laser has a single-

mode f iber pi gtail, whic h is t erminat ed in a n LC/PC o r SC/PC 0 °

optical connector.

Receiver (Electro-Optical Section)

Th e input light to the RX is coupled from the transmission fiber

into a PIN/Preamp assembly on the transponder. The PIN/

P rea mp c ontai ns a mu lti-mo de f ib er pi gtai l, wh ic h i s t ermin at ed

in an LC/PC or SC/PC 0 ° optical connector. The multi-mode

fiber pigtail has a larger core diameter (50 µ m) than the single-

mode transmission fiber (9 µm). Th eref ore, all the light from the

single-mode fiber is coupled into the larger diameter core of the

multi-mode pigtail.

The PIN/Preamp contains a PIN photodiode, trans-impedance

amplifier and non-limiting post-amplifier in one package. The

PIN diode produces a current output, which is directly propor-

tional to the intensity of the incoming light. The trans-imped-

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

ance amplifier performs current-to-voltage conversion, and the

non-limiting post-amplifier quantizes the signal into a digital out-

put.

The receiver contains a RX power monitor output, which is a

voltage output directly p roportiona l to the average optical input

power.

The Limiting Post-Amplifier provides additional voltage amplifi-

cation, and also provides a Loss Of Signal (RX_LOS) indica to r.

LOS wil l oc c ur a t a RX in pu t p ow e r lev e l less than t he s pe c if i ed

RX Sensitivity, and is an indication that t he RX is taki ng bit

errors.

The Clock and Data Recov ery (CDR) uses a PLL based approach

to recover the high speed clock from the incoming serial data

stream. A lock alarm, RX_L OS YNC, indicates if the CDR has lost

synchronization. This wil l occur if the i nput RX power level is

very low (below the LOS threshold level), or if the input data

rate is outside the specified frequency tolerance. In these

cases, the CDR will pha se lock to a Crystal Oscillator so it can

produce a valid clock output, with a frequency accuracy of ±20

ppm. In both cases of Loss Of Signal or Loss Of Synchroniza-

tion, the Transceiver IC will force all the RX output data bits,

RXDATAP/N [3:0] to a constant zero state.

Receiver (Demux section)

The incoming serial data is latched into the Transceiver IC by

the recovere d clock. The dat a and clock are applied to a 4 bit

wide Serial-to-Pa rallel Con verter (Demux), whic h demultiple xes

the data into a parallel format. The first bit received, i.e. the

MSB which is transmitted first in the serial data stream, is

placed into the highest or der bit of th e par allel output word, i.e.

Bit 3 = MSB. The Transceiver IC, however, doe s not perform a

frame alignment function. This means that the parallel output

word will contain the bits in the correct order, however, the

position of the bits within the parallel output word may be

shifted by an arbitrary amount between 0 and 4 bits. It is the

function of downstream framer logic to realign the bits.

The retimed RX output dat a, RXDATAP/N[3:0], is output at a

622.08 Mb/s data rate. The output clock, SDSCLKP/N, is at

622.08 MHz. The RXDATAP/N[3:0] data is clocked out on the

falling edge of SDSCLKP. (See RX Output Timing Diagram).

Loopback Operation

Four loopback modes of operation are provided.

Line Loopback is enabled with the LLEB_L input. In Line Loop-

back operation, the RX Serial Data and Clock inputs to the

Transc eiver IC (RSDP/N and RSCLKP/N) are routed directly to

the TX Serial outputs of the IC (TSDP/N and TSCLKP/N). This

effectively eliminates the Transceiver IC from the signal path.

Diag nostic Loop b ack is enabled with the DLEB_L input. In Diag-

nostic Loopback operation, the TX output Serial Data and Clock

of the Transceiver IC (TSDP/N and TSCLKP/N) are routed

directly to the RX Serial Data and Clock inputs of the IC (RSDP/

N and RSCLKP/N). This effectively eliminates the optical and

elec tro-opt ical components from the signal path.

Reference Loop Time is enabled with the RLPTIME input. In

Reference Loop Time operation, a divide-by-4 version of the

POCLKP/N output of the RX is used as the reference clock

input to the TX.

Serial Loop Time is enabled with the SLPTIME input. In Serial

Loop Time operat ion, the recovered high-speed clock (RSCLKP/

N) from the RX section is used in place of the synthesized

transmit clock.

Jitter

The transponder is specified to meet the Sonet Jitter perfor-

mance as outlined in ITU-T G.958 and Bellcore GR-253.

Jitter Generation i s def i ne d as the amount of j itter that is ge ne r -

ated by the transponder. The Jitter Generation specifications

are referenced to the optical OC-48 signal s. If no or minimum

jit ter is applied to the electrical inputs of the transmitter, then

Jitter Generation can simply be defined as the amount of jitter

on the TX Optical output. The Sonet specifications for Jitter

Generation are 0.01 UI rms, maximum and 0.1 UI p-p, maxi-

mum. Both are measured with a 12 KHz-20 MHz filter in line. A

UI is a Unit Interval, which is equivalent to one bit slot. At OC-

48, the bit slot is 4 00 ps, so the Jitter Gen eration specification

translates to 4 ps rms, max. and 40 ps p-p, max.

Jitter Tolerance is defined as the amount of jitter applied to the

RX Optical input that the receiver will tolerate while producing

less than a 1 dB penalty in RX Sensiti v ity. The mini mum Jitter

Tolerance levels are normally expressed as a mask of jitter

amplitude versus jitter frequency. Measured Jitter Tolerance

levels must be greater than the mask limits. The Jitter Toler-

ance mask specified in the Bellcore GR-253 do cument covers

jitter frequencies down to 10 Hz. The transponder is designed

to meet this mask.

Sonet Jit ter Transf er Mask (ITU-T G.958 & Bellcor e GR-253)

Sonet Jitter Tolerance Mask (Bellcore GR-253)

Jitter Transfer is defined as the ratio of output jitter to input jit-

ter. Referenced to an optical transponder, it is defined as the

ratio of TX Optical Output Jitter to RX Optical Input Jitter. To

measure Jitter Transfer, the transponder must be operating in

electrical loopbac k mode, with the RX electrical outputs looped

back into th e TX electrical inputs. Jitter Transfer is defined to be

less than 0.1 dB up to 2 MHz, then dropping at –20 dB decade

thereafter, per ITU-T G.958 and Bellcore GR-253. The Jitter

Transfer must be less than the following mask l imits .

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

Block Diagram

Functional Signal Description

Transmit Functions

Laser

Driver

Demux

1:4

Clk Osc.

155.52 MHz

20 ppm

MUX

&PLL

4:1

PIN-Diode

Preamp

Clk-Data

Recovery Postamp

622 MHz

SDSCLK

Data

OC-48

1300 nm

Laser

Diode

TXD

Fiber

622 MHz Pclk

TXFault

BiasMonitor

RXMonitor

LoSynch

Los

Clk

Lasercontrol

622 MHz

TXClk

Data

155.52 MHz

RefClk

Clk

Signal Name Level I/O Pin # Description

TXDATAP0

TXDATAN0

TXDATAP1

TXDATAN1

TXDATAP2

TXDATAN2

TXDATAP3

TXDATAN3

LVDS I 1

Transmit Parallel input data

at 622.08 Mb/s, aligned to

the TXCLKP/N parallel input

clock. TXDATAP/N[3] is the

most significant bit (MSB),

and is the first bit transmit-

ted in the outgoing OC-48

serial dat a st ream. TX-

DATAP/N[3:0] is sampled

on the rising edge of TX -

CLKP. DC coupled and in-

ternall y term inat e d.

TXCLKP

TXCLKN LVDS I 27

25 Transmit Parallel input

clock, 622. 08 MHz, to

which TXD ATAP/N[3:0] is

aligned. TXC L K tran sf e rs

the data on the TXDATAP/

N inputs into a 4-bit wide

latch in th e T rans c e i ve r IC.

Data is sampled on the ris-

ing edge of TXCLKP. DC

coupled and internally ter-

minated.

REFCLKP

REFCLKN LVPECL I 31

33 155.52 M H z T ransmit Ref -

erence Clock input to the

bit clock frequency synthe-

sizer of the Transceiver IC.

DC coupled and int ernally

biased.

PHASE_INITP

PHASE_INITN LVDS I 37

39 Phase Initializatio n. Rising

edge of PHASE_I NITP will

realign internal timing. DC

coupled. No internal termi-

nation.

LASER_

DISABLE LVTTL I 49 Laser Disable. Control in-

put to disable Transmit la-

ser. High = Disable laser.

Pulled low through 1 kΩ=

resistor.

TXLOCK LVTTL O 51 Los s Of Lo ck alar m for TX

PLL of the Transcei ver IC.

High = Locke d . Asynchro-

nous output.

PHASE_ERRP

PHASE_ERRN LVDS O 45

43 Phase Error. Active high.

PHASE_ERRP w ill pulses

high during each clock cy-

cle for which there is a po-

tential set-up and hold

timing violation betw een

the internal byte clock of

the Transcei ver IC and the

TXCLK timing domains.

DC coupled and intern ally

terminated.

TX_FAULT LVTTL O 53 Transmit Fault alarm out-

put. Indicates that the laser

has been automatically

shut off due to a fault in the

TX la ser ci rcuit . H ig h = TX

Fault . Fault may be cleare d

by cycling DC power, or by

strobing the RESET _L i n-

put.

TX_BIASMON LVTTL O 59 Transmit Bias Monitor

alarm output. Indicates that

the bias current of the TX

laser is currently outsi de

normal operating limits.

High = TX Bias outside lim-

its.

Signal Name Level I/O Pin # Description

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

Receive Functions

Loopback Modes

DC Power

PCLKP

PCLKN LVDS O 10

8622.08 M Hz Parallel Clock

output. Generated by divid-

ing the internal high-speed

TX clock by 4.

RESET_L LVTTL I 56 Master Reset input. A Low

level re se ts the TX Mux

and Laser Driver. RESET_L

must be held low for at

least 6 millisec. Pulled high

through a 1 kΩ resistor .

Signal Name Level I/O Pin # Description

RXDATAP0

RXDATAN0

RXDATAP1

RXDATAN1

RXDATAP2

RXDATAN2

RXDATAP3

RXDATAN3

LVDS O 44

Pa ralle l Output D a ta at

622.08 Mb/ s from t he Re-

ceiver, aligned to the Parallel

Output Clock (RXCLKP/N).

RXDATAP/N[3] is the Most

Significant Bit, and is the first

bit received in the incoming

OC-48 serial data stream.

RXDATAP/N[3:0] is clocked

out on the falling edge of

SDSCLKP. All data outputs

are forced to zero level under

Loss Of Signal or Loss Of

Synchronization conditions.

DC co upled ou tputs. Interna l-

ly termi n a ted.

SDSCLKN

SDSCLKP LVDS O 16

14 Parallel Output Clock from

the Receiver at 622.08 MHz.

This clock is aligned to the

RXDATAP/N[3:0] parallel out-

put data. RXDATAP/N[3:0] is

clocked out on the falling

edge of SDSCLKP. Clock out-

put is continuous under Loss

Of Signal or Loss Of Syn-

chronization conditions. DC

coupled output. Interna l ly

terminated.

RX_LOS LVTTL O 55 Receive Loss Of Signal alarm

output. A High output level

indicates RX input power is

below the s ensitiv it y level of

the receiver (high BER condi-

tion).

RX_LO SYNC LVTTL O 57 Recei ve Lo ss Of Synchroni-

zation alarm output. A High

output level indicates that

the receive Cloc k Recovery

unit has lost synchronization,

due to either very low RX in-

put power level, or input data

rate outside of frequency tol-

erance.

RX_MON Ana log O 58 Recei ve p o w er m o nitor

output. A voltage output

which is directly proportional

to th e op tical R X inpu t

power.

Signal Name Level I/O Pin # Description Signal

Name Level I/O Pin # Description

LLEB_L LVTTL I 38 Line Loopback Enable input. A

Low leve l e nab le s Line Loopback

mode. When active, the RX inputs

to the Transceiver IC will be r outed

directly to the TX outputs. Pulled

high through a 1 kΩ resist or.

DLEB_L LVTTL I 40 Diagnostic Loopback Enable input.

A Low level enables Diagnostic

Loopback mode. When active, the

TX outputs of the Transceiver IC

are routed directly to the RX in-

puts. Pulled high through a 1 kΩ re-

sistor.

RLP-

TIME LVTTL I 4 Reference Loop Time Enable in-

put. A High level enables Refer-

ence Loop Time. When active, a

divide-by-4 version of the PO -

CLKP/N output of the RX is used as

the reference clock input to the TX.

Pulled low through a 1 kΩ resist or.

SLP-

TIME LVTTL I 2 Serial Loop Time Enable input. A

High level enables Ser ial Loo p

Time. When ac tive, the recover ed

high-speed clock (RSCLKP/N) from

the RX section is used in place of

the synthesized transmit clock.

Pulled low through a 1 kΩ resistor.

Signal

Name Level I/O Pin # Description

GROUND 0 V DC I 5,6,

11,12,

17,18,

23,24,

29,30,

35,36,

Blade

Ground connection for both

signal and chassis ground

on the transponder. The

blade contact of the 60 pin

interface connector is tied to

ground in the transponder.

Therefore, the blade of the

user‘s ma ting co nnector

should be connected to

ground, as well.

VCC +3.3 V DC I 41,47,

46,48,

50,52,

DC Power Input. +3.3 V DC,

nominal.

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

Functional Diagrams

TX Input Timing Diagram

RX Output Timing Diagram

TECHNICAL DATA

Recommen ded Operating Conditions

Note

1. TCASE is measured on top of the transp onder (see details on page 1,

outline dimensions)

DC Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units

Operating Case Tempera-

ture(1) TC070

Transpon der Total Power

Consumption PTOT 2.8 3.46 W

3.3 V Supply Volta ge VCC 3.13 3.3 3.46 V

3.3 V Supply Current ICC 0.85 1.0 A

Input Differential Noise ,

All Pins NDIFF 15 mV

0-p

Parameter Symbol Min. Typ. Max. Units

LVDS Input High Volt-

age LVDS VIH 1.1 1.9 V

LVDS Inp ut Lo w V ol t-

age LVDS VIL 0.6 1.5

LVDS Input Voltage

Differential LVDS

VINDIFF 200 1200 mV

LVDS Input Single

Ended Voltage LVDS

VINSING 100 600

LVDS Differential In-

put Resistance LVDS RDIFF 80 100 120 Ω

LVDS Output High

Voltage LVDS VOH 1.13 1.8 V

LVDS Output Low

Voltage LVDS VOL 0.7 1.4

LVDS Output Differ-

ential Voltage LVDS

VOUTDIFF 440 740 1100 mV

LVDS Output Single

Ended Voltage LVDS

VOUTSIN-

GLE

220 370 550

LVPECL Input Low

Voltage LVPECL VIL VCC

–1.9 VCC

–1.4 V

LVPECL Input Hig h

Voltage LVPECL

VIH VCC

–1.1 VCC

–0.55

LVPECL Input Si ngl e

Ended Swing LVPECL

VINSINGLE 200 1200 mV

LVPECL Input Diff er-

ential Swing LVPECL

VINDIFF 400 2400

LVPECL Input DC

Bias LVPECL

VBIAS VCC

–0.5 VCC

–0.3 V

LVTT L Inpu t H ig h

Voltage LVTTL VIH 2.0 VCC

LVTT L Inpu t Low

Voltage LVTTL VIL 00.8

LVTT L Inpu t H ig h

Current LVTTL IIH 50 µA

LVTTL O ut p ut

Current LVTTL IO–500

LVTTL Outp ut High

Voltage LVTTL VOH 2.4 V

LVTTL O utput Low

Voltage LVTTL VOL 0.8

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

AC Electrical Characteristics

Notes

1. TCASE is measured on to p of the tr ansponder (s ee details on page 1,

outline dimensions)

2. Maximum allowable jitter on the reference clock input (REFCLKP/N)

such that the transmit ter will meet ITU-T G.958 and Bellcore GR-253

Jitter Generation requirements. Measured with a 12 KHz - 20 MHz

filter.

Parameter Sym-

bol Condi-

tions Min. Typ. Max. Units

Transmitter

TXDATAP/N[3: 0]

Inp u t B i t R ate 622.08 Mb/s

TXCLKP/N Input

Frequency 622.08 MHz

TXCLKP/N Input

Duty Cycle 40 60 %

TXCLKP/N Input

Rise/Fall Time 20-80% 100 300 ps

TXDATA Setup

Time with re-

spect to the Ris-

ing edge of

TXCLK P

TST See TX

Timing

Dia-

gram

200

TXDATA Hold

Time with re-

spect to the Ris-

ing edge of

TXCLK P

THT See TX

Timing

Dia-

gram

200

REFCLKP /N In-

put Frequency 155.520 MHz

REFCLKP /N In-

put Frequency

Tolerance

±20 ppm

REFCLKP /N In-

put Duty Cycle 45 55 %

REFCLKP /N In-

put Rise/Fall

Time

10-90% 500 ps

REFCLKP /N In-

put Jitter(2) 1ps,

rms

PHASE_INITP/N

Input Min. Pulse

Width

3.2 ns

PCLKP/N Out-

put Frequency 622.08 MHz

PCLKP/N Out-

put Duty Cycle 45 55 %

Return Loss, All

AC Inputs & Out-

puts

10 MHz

- 1 GHz 15 dB

RESET_L Input

Min. Pulse Width 6ms

Parameter Sym-

bol Condi-

tions Min. Typ. Max. Units

Receiver

RXDATAP/N[3:0]

Output Bit Rate 622.08 Mb/s

SDSCLKP/N Out-

put Frequency 622.08 MHz

SDSCLKP/N Out-

put Duty Cycle 40 60 %

SDSCLKP/N Out-

put Rise/Fall

Time

20-80% 100 300 ps

RXDATA Setup

Time with re-

spect to the Fall-

ing edge of

SDSCLKP

TSR See RX

Timing

Dia-

gram

600

RXDATA Hold

Time with re-

spect to the Fall-

ing edge of

SDSCLKP

THR See RX

Timing

Dia-

gram

600

Return Loss, all

AC Inputs & Ou t-

puts

10 MHz

- 1 GHz 15 dB

SDSCLKP/N Out-

put Frequency

Accuracy during

LOS or LO-

SYNC(1)

Over

operat-

ing

Temp

Range

±20 ppm

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

Transmitter Electro-Optical Characteristics

Notes

1. The laser driver contains a control circuit, which regulates the aver-

age optical output power. Nominal output power is f act or y set to be

within the specified ra nge.

2. The Ey e Diagram is compliant with Bel lcore GR-253 and ITU-T G.957

Eye Mask specifications.

3. Jitter Generation is defined as the amount of jit t er on t he TX Optical

Output, when there is no or minimum jitter on the TX electrical

inputs. Jitter Generati on is compliant with GR-253 and ITU-T G.958

specificati ons, when measur ed using a 12 KHz - 20 MHz filter, and

with a jitte r level on the REFCLKP/N in put wh ich is less than the

level specified in ”AC Electr ical Charact eristic s - Transmitter”.

4. If the +3. 3 V po w er s upply dr ops belo w t he specifi ed le v el, the l aser

bias and modulation current s will be held disabled until the supply

voltage rises above threshold and after the Power On Delay Time

period.

5. A fault, such as hi gh las er bias current or high av er age p ower, which

lasts longer than the specified Fault Delay time, will cause the trans-

mitter to be disabled. The fault can be cleared by cycling of DC

power, or by strobing the RESET_L input.

Receiver Electro-Optical Characteristics

Notes

1. Average RX power f or a 1x10–10 BER, and using a PRBS pattern of

223–1 length with 72 zeros and 72 ones inserted, as per ITU-T

G.958.

2. Jitter Tolera nce is defi ned as the amount of jitter applied to the RX

optical input that the receiver will tolerate without producing bit

errors. The minimum required Jitter Tolerance for a 1 dB power pen-

alty is defined to be 1 5 UI from 1 0 Hz to 600 Hz, 1.5 UI from 6 KHz to

100 KHz, and 0.15 UI from 1 MHz onwards, per Bellcore GR-253.

3. Jitter Transfer is defined as the ratio of TX Output Jitter to RX Input

Jit ter, when the transpon der is operated in ele ctrical loopback mode

(RX electrical outputs looped back into TX electrical inputs). Jitter

Transfer is specified to be less than 0.1 dB up to 2 MHz, and drop-

ping at –20 dB/Decade after that point, per ITU-T G.958 and B ellcore

GR-253.

4. The RX_LOS output is an active high LVTTL output, which is set

HIGH if there is a loss of RX opt ical signal input (LOS), A decrease in

optical input power below the asser t level will cause the RX_LOS

Parameter Symbol Min. Typ. Max. Units

Nominal Center Wave-

length TX λNOM 1310 nm

Range Of Center Wave-

lengths TX λMIN-

λMAX 1260 1360

Spectral Bandwidth TX

∆λRMS 5nm,

rms

Average Output

Power(1) TX PAVG –10 –4–3dBm

Extinction Ratio T X ER 8.2 14 dB

Output Rise Time

20%-80% TX TR100 200 ps

Output Fall Time

80%-20% TX TF175 250

Eye Diagram(2) TX ED

TX Jitter Generation,

rms(3) TX

JGEN rms 0.007 0.01 UI

rms

TX Jitter Generation,

p-p(3) TX

JGEN p-p 0.07 5 0. 1 UI p-p

Reset Threshold for

VCC(4) TX VTH 2.2 2.95 V

Po w er On Dela y for

VCC(4) TX TPOD 20 ms

Fault Delay(5) TX

TFAULT 20

TX Bias Monitor switch-

ing threshold TX IBIAS 60 mA

Parameter Symbol Min. Typ. Max. Units

Nominal Center

Wavelength RX λNOM 1310 nm

Sensit ivity (A ver age

Power)(1) RX PSENS –25 –18 dBm

Overload (Average

Power)(1) RX POL –3

Optical Return Loss RX RL 27 dB

RX Jitter Tolerance(2) RX JTOL

RX-to-TX Jitter Trans-

fer(3) RX-TX JXFR

Optical Path Penalty RX PPEN 1.0 dB

Clock Recovery Cap-

ture Frequency

Range(5)

RX FCAPT ±200 ppm

Clock Recovery Ac-

quisiti o n Lock Time RX TLOCK 32 250 µs

RX_LOS Output As-

sert rela tive T o RX

Optical Inpu t Power(4)

RX_

LOSASSERT –30 –25 dBm

RX_LOSYNC Output

Assert relative to RX

input frequency(5)

RX_

LOSYNCAS-

SERT

±450 ±600 ±770 ppm

RX_LOS Output Hys-

teresis(4) RX_

LOSHYST 3dB

RX_LOS &

RX_LOSYNC Output

Assert Time(4 , 5)

TASSERT 100 µs

RX_LOS &

RX_LOSYNC Output

Deassert Time(4, 5)

TDEASSERT 100

RX_MON Transfer

Slope(6) 4.4 mV/

µW

RX_MON Dark Offset

Voltage(6) 53 mV

RX_MON Output

Voltage at

PIN = –17 dBm(6)

142

RX_MON Output

Voltage at

PIN = –7 dBm(6)

900

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

output to switch HIGH (ON). Hysteresis occurs when the optical

input power is raised back above the threshold switching level. The

RX_LOSYNC output is an active high LVTTL output, which is set

HIGH if the Clock Data Recovery PLL becomes unlocked. Loss Of

Sync will occur at a lower optical input pow er level than L OS , but still

within the sp ec if ied inpu t p ower range.

5. The receiver lock range is typically ±300 ppm from nominal OC-48

data rate. When the data rate of the RX signal de viates b y more than

±600 ppm (typically) from nominal, or if t he RX is in a Loss Of Signal

(LOS) condition, then the Clock Recovery module will lock to an

internal 155.52 MHz crystal oscillator. Under this condition: The

appropriate fault output (RX_LOS or RX_LOSYNC) switches active;

The RXDATAP/N[3:0] output data is forced to all zeros; and, the

switching of the SDSCLKP/N output is done so that the clock is con-

tinuous, and t here are no viol ations of the min imum puls e width and

period.

6. RX_MON ouput voltage is measured between VCC (+) and

RX_MON (–). R X_M ON is specif ied up to a maximum optical inp ut

average power of –5 dBm (316.2 µW).

Connect or Pin Assignmen ts

Agency Certifications

Typical RX_MON Characteristic (Linear)

Typical RX_MON Characteristic (Logarithmic)

Pin # Sig n al Name Pin # Sign al Name

1 TXDATAP0 2 SLPTIME

3 TXDATAN0 4 RLPTIME

5 GND 6 GND

7 TXDATAP1 8 PCLKN

9 TXDATAN1 10 PCLKP

11 GND 12 GND

13 TXDATAP2 14 SDSCLKP

15 TXDATAN2 16 SDSCLKN

17 GND 18 GND

19 TXDATAP3 20 RXDATAN3

21 TXDATAN3 22 RXDATAP3

23 GND 24 GND

25 TXCLKN 26 RXDATAN2

27 TXCLKP 28 RXDATAP2

29 GND 30 GND

31 REFCLKP 32 RXDATAN1

33 REFCLKN 34 RXDATAP1

35 GND 36 GND

37 PHASE_INITP 38 LLEB_L

39 PHASE_INITN 40 DLEB_L

41 VCC 42 RXDATAN0

43 PHASE_ERRN 44 RXDATAP0

45 PHASE_ERRP 46 VCC

47 VCC 48 VCC

49 LASER_DISABLE 50 VCC

51 TXLOCK 52 VCC

53 TX_FAULT 54 VCC

55 RX_LOS 56 RESET_L

57 RX_LOSYNC 58 RX_MON

59 TX_BIASMON 60 SPARE

BLADE GND

Feature Standard Comments

Electrostatic Dis-

charge (ESD) to

the Electrical Pins

EIA/JESD22-A114-A

(MIL-STD 88 3D

Method 3015.7)

Class 1 (2000 V)

Immunity:

Electrostatic

Discharge (ESD)

to Housing/Pigtails

EN 6100 0- 4-2

IEC 610 00-4-2 Discharges r anging

from ±2 kV to ±15 kV

on housing/pigtails

cause no dama ge to

transponder (under

recommended condi-

tions).

Immunity:

Radio Frequency

Electromagnetic

Field

EN 6100 0- 4-3

IEC 610 00-4-3 With a field strength of

10 V/m rms, noise

frequency ranges from

10 MHz to 2 GHz . No

effect on transponder

performance betw een

the specification limits.

Emission:

Electromagnetic

Interference (EMI)

FCC Part 15, Class B

EN 5502 2 Cl ass B

CISPR 22

Noise frequency range:

250 MH z t o 18 G H z

0,2

0,4

0,6

0,8

1,2

1,4

1,6

0 0,1 0,2 0,3

RX Input Average Power (mW)

RX_MON Voltage (V)

0,2

0,4

0,6

0,8

1,2

1,4

1,6

-25 -20 -15 -10 -5

RX Input Average Power (dBm)

RX_MON Voltage (V)

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

EYE SAFETY

This laser based single mode transponder is a Class 1 product.

It complies with IEC 60825-1 and FDA 21 CFR 1040.10 and

1040.11.

The transpond er has been cer tified with FDA under accession

number 9911449-03.

To meet laser safety requirements the transponder shall be

operated within the Absolute Maximum Ratings.

Caution

All adjust m ent s have been made a t the factory prior to ship-

ment of the devices . N o ma i n tenanc e or alterati o n to th e

device is required.

Tampering with or modifying the performance of the device

will result in voided product warranty.

Note

Failure to adhere to the above restrictions could result in a modifica-

tion that is considered an act of “manufacturing”, and will require,

under la w, recertification of th e modified pr oduct with t he U . S . Food

and Drug Administration (ref. 21 CFR 1040.10 (i)).

Laser Data

Required Labels

Laser Emission

APPLICATION NOTES

INTERFACING THE 4-LINE TRANSPONDER

Scope

This Appli cation Note is meant to define the interfacing

between the Infineon 4-Line OC-48 Transponder, and the cus-

tomer equipment.

Introduction

The signals which interface to the OC-48 Transponder can be

grouped into Transmit (TX) and Receive (RX) functions.

The TX signals are:

TXDATAP/N[0..3]: 4 differential LVDS inputs for TX Data.

TXCLKP/N: A differential LVDS input for TX Clock.

REFCLKP/N: A differential LVPECL input for TX Reference

Clock.

PHASE_INITP/N: A differential LVDS input for Phase Initializa-

tion of the TX Mux.

PHASE_ERRP/N: A differential LVDS output fo r Phase Error of

the TX Mux.

The RX signals are:

RXDATAP/N[0..3]: 4 differential LVDS outputs for RX Data.

SDSCLKP/N: A differential LVDS output for RX Clock.

Interfacing

Interf acing Diagram

TX Signals

The customer OC-48 framer drives the TXDATA and TXCLK

inputs. In order to use DC Coupling, the framer should be a

+3.3 V LVDS device. Each of the inputs is terminated with

100 Ω differential between lines in the transponder.

The PHASE_ERR output is not true LVDS, but is LVDS level

compatible, which uses a 330 Ω to ground termination in the

transponder. The PHASE_INIT input is LVDS. In normal ope ra-

tion, PHASE_INITP is directly connected to PHASE_ERRP, and

PHASE_INITN is directly connected to PHASE_ERRN. These

connections must b e made on t he cust omer board.

The REFCLK input is a LVPECL input, which is driven by the

customer Clock Source, which should be an LVPECL device. DC

Wavelength 1310 nm

Total output power (as defined by IEC: 50 mm

aperture at 10 cm dis tance) 2 mW

Total output power (as defined by FDA: 7 mm

aperture at 20 cm dis tance) 180 µW

Beam divergence 5°

Class 1 Laser Product

IEC

Complies with 21 CFR

1040.10 and 1040.11

FDA

Top view

Pigtail

SC or LC

Indication of

laser aperture

and beam

Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km

coupling is acceptable if the clock source is a +3.3 V LVPECL.

The REFCLK input is terminated with 100 Ω differential

between lines in the transponder. It is necessary for the cus-

tomer to provide the external 330 Ω resistors to ground for the

source termination.

RX Signals

The customer framer accepts as input the RXDATA and RXCLK

outputs of the transpo nder. In order to use DC Coupling, the

framer should be a +3.3 V LVDS device. The RXDATA and

SDSCLK outputs of the transponder are not true LVDS, but are

LVDS level compatible, which use a 330 Ω to ground termina-

tion in the transponder. If the framer does not have a 100 Ω dif-

fer en t ia l ter m in ation between line s, t he n th e cu stomer will

have to supply the terminations on their board.

Line Impedance

For proper impedance matching, all LVDS traces should be con-

structed as a differential trace pair, with 100 Ω characteristic

impedance between the lines of each pair, and 50 Ω character-

istic impedance per line. The LVPECL traces should be con-

structed as 50 Ω per line.

CONV ERSION OF RX_MON OUTPUT TO A VOLTAGE WITH

RESPECT TO GROUND

MECHANICAL

Size

The outline size for the transponder housing is 2.3 in x 1.6 in x

0.54 inches. Please refer to the outline drawing.

Fiber & Connectors

The transponder has fiber pigtails for both TX and RX. The TX

pigtail is Single Mode Fiber, 9 µm/125 µm. The RX pigtail is

Multi Mode Fiber, 50 µm/1 25 µm, allowing a highly tolerant cou-

pling with a Single Mode Fiber. Each pigtail is terminated with a

LC/PC or SC/PC optical connector with 0 o polis h. The mi nimum

bend radius of the fiber pigtails is 30 mm (1.18 inches), typical.

The fiber length see Ordering Information on page 1, as mea-

sured from the transponder housing to the tip of the connector.

Interface Connector

The transponder interface connector is a 60 pin SMT, dual row,

header, 0.5 mm pitch, with ground blade, Samtec part numb er

QTH-030-01-L-D-A. The appropriate mating connector for the

customer pcb is a 60 pin SMT, dual row, socket, 0.5 mm pitch,

with mati ng al ignm ent p ins, S amt ec part n umb er QSH -030-01- L-

D-A. The internal blade of the connector should be connected

to signal ground on the user’s pcb. Contact Samtec for recom-

mended pcb layout pattern for Q SH connector.

Hostboard Contact Area

For detailed connector layout information, check

http://www.samtec.com, and go to “QSH” connector.

Dimensions in mm [inches]

Published by Infi neon Techno logies AG

Attention please!

The information herein is given to describe certain components and shall not be

considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

W e hereby disclaim any and all warr a nties, including but not limited to w a rranties

of non-infrin gem ent , regarding circuits, descri ptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices

please contact the Infineon Technologies offices or our Infineon Technologies

Representatives worldwide - see our webpage at

www.infineon.com/fiberoptics

Warnings

Due to technical requirements components may contain dangerous substances.

F or information on the types in question please contact your Infineon T echnologies

offices.

Infineon Technologies Components may only be used in life-support devices or

systems with the express written approval of Infineon Technologies, if a failure of

such components can reasonably be expected to cause the failure of that

life-support device or system, or to aff ect the saf ety or ef fectiveness of that device

or system. Life support devices or systems are intended to be implanted in the

human body, or to support and/or maintain and sustain and/or protect human life.

If they fail, it is reasonable to assume that the health of the user or other persons

may be endangered.

Infineon Technologies AG • Fiber Optics • Wernerwerkdamm 16 • Berlin D-13623, Germany

Infineon Technologies, Inc. • Fiber Optics • 1730 North Fir s t Str eet • San Jose, CA 95112, USA

Infineon Technologies K.K. • Fiber Optics • Takanawa Park Tower • 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku • Tokyo 141, Japan

For the guaranteed EMI-performance an optimal electrical con-

tact between the transponder housing and the user's pcb sig-

nal ground is necessary. For the user's pcb (hos tboard) we

recommend a full signal ground plane underneath the entire

transponder ho using (incl uding t he st andoff area, the EM I gas-

ket area and the optional heatsink area).

The transponder is equipped with an attached EMI gasket.

According to the drawing “Hostboard Contact Area” the con-

tact surface of the entire EMI gasket should be connected to

signal ground on the user's pcb. The area unde r the EMI gas-

kets (EMI gasket area) should be gold flash or tin plated copper

with no solder mask or other nonconductive coatings.

The four mounting screws of the housing also must be con-

nected to signal grou nd on the user' s pcb. Therefore the

mou nting scr e w ar eas shou ld ha ve sq uar e pad s of go ld fla sh or

tin plated copper, that a re connected to signal ground. These

pads are located on the pcb opposit e side to the tran sponder.

Use a torque wrench to tighten the mounting screws. The rec-

ommended torque value is 10 ±2 Ncm = 0.1 ±0.02 Nm =

14.16 ±2.83 oz-in. With a higher or lower value, the EMI-perfor-

mance will deteriorate.

The heatsi nk area under the center of the transponder is

optional and could be used for critical ambient temperature or

critical airflow. Currently it is not a complete replacement for

the regular heatsink. The cont act area should be conn ected to

signal ground. Gold (Au), Tin or other met a l platings are recom-

mended for good heat transfer. Any polymer coating will

decrease the heatsinking performance. Special heat transfer

pads are in progress. For reliable heatsinking to the hostboard,

the max. hostboard temperature must be lower or equal to the

specified ambient air temperature.

Scheme of tightening mounting screws

It is recommended to use a torque wrench to tighten the

mounting screws. Tightening torque value is:

10 ±2 Ncm = 0.1 ±0.02 Nm = 14.16 ±2.83 oz-in.

With a higher or lower value, the EMI-performance will deterio-

rate.

In order to avoid a mechanical stress of the users PCB and to

reduce the impacting forces (twisting or wresting of the PCB)

we recommen d a crosswise tightening of the 4 mount ing

screws.

Scheme

Please tighten the screws according to the following scheme:

1. Inser t four screws and tighten them very loose in the follow-

ing orde r:

2. Tigh ten the four scre w s ha nd-s cre wed in the foll o wing or de r:

3. Tighten the four screws with a torque wrench

10 ±2 Ncm = 0.1 ±0.02 Nm

14. 16 ±2.83 oz-in in the following order: