V23816-N1018-C312/L312(*) 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder OC-48 SONET/SDH Short Reach (SR) up to 2 km Preliminary Dimensions in mm [inches] V23816-N1018-L312 * * * * * * Laser bias monitor RX power monitor output Loopback operating modes 155.520 MHz LVPECL input TX reference clock 2.8 W Typical Power Consumption TX Fault output indicator ABSOLUTE MAXIMUM RATINGS Operation beyond these ratings may cause permanent damage to the transponder. FEATURES * Compliant with existing standards * Compact integrated transponder unit with - FP laser diode transmitter - InGaAs PIN photodiode receiver - Pigtailed optical connections - Integrated Mux, Demux and Clock Recovery * Class 1 FDA and IEC laser safety compliant * Single +3.3 V power supply * OC-48 optical transmit and receive at 2488.32 Mbit/s * 4-line LVDS differential interface at 622.08 Mbit/s * External control for laser shutoff * Loss of optical signal and Loss of synch indicators (RX) * Loss of lock indicator for TX high speed clock Fiber Optics Supply Voltage (VCC).................................................... 0 to 4.0 V LVDS Input Levels.......................................................... 0 to VCC LVPECL Input Level ...................................................... 0 to VCC LVTTL Input Level ........................................................ 0 to 5.5 V LVDS Output Source Current............................................. 5 mA LVPECL Output Source Current....................................... 24 mA LVTTL Output Source Current ........................................... 1 mA Operating Ambient Temperature ................................ 0 to 70 oC Storage Ambient Temperature ............................... -40 to 85 C Static Discharge Voltage, All Pins ................................... 1000 V (*) Ordering Information Connector type Fiber length Part number SC 24.1 0.8 " V23816-N1018-C312 LC 24.1 0.8 " V23816-N1018-L312 MAY 2001 DESCRIPTION recentered. However, if the REFCLKP/N input is, for instance, produced by a free running oscillator, then such potential violations may exist. When FIFO realignment occurs, up to 10 bytes of data will be lost. Automatic FIFO realignment can be enabled by simply connecting the PHASE_ERRP/N output directly to the PHASEINITP/N input. The user can also take the PHASE_ERRP/ N output, process it and send a signal to the PHASE_INITP/N in such a way that idle bytes are lost during the realignment process. The Infineon single mode SONET/SDH transponder is compliant with the Bellcore GR-253, ITU-T G.957, and ITU-T G.958 specifications. The transmitter section consists of a multiplexer (Mux), laser driver, Fabry Perot (FP) laser diode and pigtail single mode fiber with LC/PC or SC/PC 0 termination. The receiver section consists of a multimode fiber pigtail with LC/PC or SC/ PC termination, a packaged PIN photodiode and preamplifier, postamplifier, clock and data recovery (CDR), and a demultiplexer (Demux). The Mux and Demux functions are integrated together onto a single Transceiver IC. The 622.08 MHz parallel data interface frees the user from the concerns of pcb layout at 2.5 Gb/s. The pluggable connector blind mates easily to the customer pcb, and allows the transponder to be removed prior to any solder reflow or washing of the users pcb. The TX Clock Synthesizer section provides a lock alarm output signal, TXLOCK, which indicates if the clock synthesizer is properly phase locked. Transmitter (Electro-Optical Section) The serial data output, TSDP/N, of the Transceiver IC is input to a laser driver IC. The laser driver provides both bias and modulation to a laser diode. The laser bias current is controlled by a closed-loop circuit, which regulates the output average power of the laser over conditions of temperature and aging. The Monitor PIN diode, which is mechanically built into the laser, provides a feedback signal to the laser driver, and prevents the laser power from exceeding the factory preset operating limits. The transponder operates from a single +3.3 V power supply. The electrical interface is via a 60 pin pluggable connector. The transmit and receive electrical signals each consist of 4 parallel differential LVDS data, and a differential LVDS clock. The transmit input data and clock lines, and the receive output data and clock lines, are all internally biased and terminated. All lines are DC coupled to the interface connector. The laser driver includes an eye safety feature that will automatically shut off power to the laser if a fault condition occurs which causes excessively high laser bias current or excessively high average output power. Such a fault will be indicated on the TX_FAULT output. The fault can be cleared by cycling DC power, or by strobing the RESET_L input. The transponder is designed to transmit and receive serial OC48 (2488.32 Mb/s) data over standard non-dispersion-shifted single mode fiber at a wavelength of 1310 nm. Transmitter (Mux Section) Please refer to the transponder block diagram. The Mux and Laser Driver can be reset with the RESET_L input. During the time that RESET_L is held active, there will be no optical output from the transmitter. The RESET_L input will clear any fault indication that has occurred on the TX_FAULT output. The transmitter accepts a 4 bit wide parallel input data word, TXDATAP/N[3:0], at a 622.08 Mb/s data rate. The TX input clock, TXCLKP/N, is synchronous with the incoming data, at a frequency of 622.08 MHz. This clock is used to load the data into a 4-bit latch. The data is read in on the rising edge of the positive input clock. (See TX Input Timing Diagram). The laser can be switched off at any time with the LASER_DISABLE input. A reference input clock, REFCLKP/N, at 155.52 MHz, is supplied as a reference input to the high speed Clock Synthesizer. The high speed output of the clock synthesizer will clock the Timing Generator and the Parallel-to-Serial Converter. The Parallel-to-Serial Converter will output the retimed data as a serial bit stream, TSDP/N, at 2488.32 Mb/s data rate. Bit 3 of the TXDATAP/N parallel input word is the MSB, and is transmitted first in the data stream. Bit 0, the LSB, is transmitted last. The TX_BIASMON output is provided as an alarm to indicate if the laser bias current is outside of the normal operating range. This output can be used to monitor the aging of the laser. The laser diode is a Fabry-Perot type, which, due to the cavity nature of its design, will emit light at several longitudinal wavelengths, or modes centered about 1310 nm. This type of laser is suitable for the short reach transmission over single-mode fiber that this transponder is intended for. The laser has a singlemode fiber pigtail, which is terminated in an LC/PC or SC/PC 0 optical connector. The output of the high speed Clock Synthesizer, which is internally set to 2488.32 MHz, is tapped off the Timing Generator, and is divided to 622.08 MHz. This output (PCLKP/N) is intended to be used as a reference clock for TX upstream logic. Receiver (Electro-Optical Section) The PHASE_INITP/N input signal is used to realign the internal timing of the Timing Generator by resetting and centering the FIFO in the Transceiver IC. The realignment will occur on the rising edge of PHASE_INITP, which must be held high for at least 10 ns. The input light to the RX is coupled from the transmission fiber into a PIN/Preamp assembly on the transponder. The PIN/ Preamp contains a multi-mode fiber pigtail, which is terminated in an LC/PC or SC/PC 0 optical connector. The multi-mode fiber pigtail has a larger core diameter (50 m) than the singlemode transmission fiber (9 m). Therefore, all the light from the single-mode fiber is coupled into the larger diameter core of the multi-mode pigtail. The PHASE_ERRP/N output will pulse high during each clock cycle when there is a potential set-up & hold timing violation between the internal byte clock and the TXCLKP/N input, indicating that PHASE_INITP/N must be strobed. The PIN/Preamp contains a PIN photodiode, trans-impedance amplifier and non-limiting post-amplifier in one package. The PIN diode produces a current output, which is directly proportional to the intensity of the incoming light. The trans-imped- If the Reference Clock input, REFCLKP/N, is derived from and is synchronous with the TX Byte Clock, TXCLKP/N, then there should never be any short setup and hold times between the two timing domains, and the FIFO should never need to be Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 2 ance amplifier performs current-to-voltage conversion, and the non-limiting post-amplifier quantizes the signal into a digital output. Serial Loop Time is enabled with the SLPTIME input. In Serial Loop Time operation, the recovered high-speed clock (RSCLKP/ N) from the RX section is used in place of the synthesized transmit clock. The receiver contains a RX power monitor output, which is a voltage output directly proportional to the average optical input power. Jitter The transponder is specified to meet the Sonet Jitter performance as outlined in ITU-T G.958 and Bellcore GR-253. The Limiting Post-Amplifier provides additional voltage amplification, and also provides a Loss Of Signal (RX_LOS) indicator. LOS will occur at a RX input power level less than the specified RX Sensitivity, and is an indication that the RX is taking bit errors. Jitter Generation is defined as the amount of jitter that is generated by the transponder. The Jitter Generation specifications are referenced to the optical OC-48 signals. If no or minimum jitter is applied to the electrical inputs of the transmitter, then Jitter Generation can simply be defined as the amount of jitter on the TX Optical output. The Sonet specifications for Jitter Generation are 0.01 UI rms, maximum and 0.1 UI p-p, maximum. Both are measured with a 12 KHz-20 MHz filter in line. A UI is a Unit Interval, which is equivalent to one bit slot. At OC48, the bit slot is 400 ps, so the Jitter Generation specification translates to 4 ps rms, max. and 40 ps p-p, max. The Clock and Data Recovery (CDR) uses a PLL based approach to recover the high speed clock from the incoming serial data stream. A lock alarm, RX_LOSYNC, indicates if the CDR has lost synchronization. This will occur if the input RX power level is very low (below the LOS threshold level), or if the input data rate is outside the specified frequency tolerance. In these cases, the CDR will phase lock to a Crystal Oscillator so it can produce a valid clock output, with a frequency accuracy of 20 ppm. In both cases of Loss Of Signal or Loss Of Synchronization, the Transceiver IC will force all the RX output data bits, RXDATAP/N [3:0] to a constant zero state. Jitter Tolerance is defined as the amount of jitter applied to the RX Optical input that the receiver will tolerate while producing less than a 1 dB penalty in RX Sensitivity. The minimum Jitter Tolerance levels are normally expressed as a mask of jitter amplitude versus jitter frequency. Measured Jitter Tolerance levels must be greater than the mask limits. The Jitter Tolerance mask specified in the Bellcore GR-253 document covers jitter frequencies down to 10 Hz. The transponder is designed to meet this mask. Receiver (Demux section) The incoming serial data is latched into the Transceiver IC by the recovered clock. The data and clock are applied to a 4 bit wide Serial-to-Parallel Converter (Demux), which demultiplexes the data into a parallel format. The first bit received, i.e. the MSB which is transmitted first in the serial data stream, is placed into the highest order bit of the parallel output word, i.e. Bit 3 = MSB. The Transceiver IC, however, does not perform a frame alignment function. This means that the parallel output word will contain the bits in the correct order, however, the position of the bits within the parallel output word may be shifted by an arbitrary amount between 0 and 4 bits. It is the function of downstream framer logic to realign the bits. Sonet Jitter Transfer Mask (ITU-T G.958 & Bellcore GR-253) The retimed RX output data, RXDATAP/N[3:0], is output at a 622.08 Mb/s data rate. The output clock, SDSCLKP/N, is at 622.08 MHz. The RXDATAP/N[3:0] data is clocked out on the falling edge of SDSCLKP. (See RX Output Timing Diagram). Sonet Jitter Tolerance Mask (Bellcore GR-253) Loopback Operation Four loopback modes of operation are provided. Line Loopback is enabled with the LLEB_L input. In Line Loopback operation, the RX Serial Data and Clock inputs to the Transceiver IC (RSDP/N and RSCLKP/N) are routed directly to the TX Serial outputs of the IC (TSDP/N and TSCLKP/N). This effectively eliminates the Transceiver IC from the signal path. Diagnostic Loopback is enabled with the DLEB_L input. In Diagnostic Loopback operation, the TX output Serial Data and Clock of the Transceiver IC (TSDP/N and TSCLKP/N) are routed directly to the RX Serial Data and Clock inputs of the IC (RSDP/ N and RSCLKP/N). This effectively eliminates the optical and electro-optical components from the signal path. Jitter Transfer is defined as the ratio of output jitter to input jitter. Referenced to an optical transponder, it is defined as the ratio of TX Optical Output Jitter to RX Optical Input Jitter. To measure Jitter Transfer, the transponder must be operating in electrical loopback mode, with the RX electrical outputs looped back into the TX electrical inputs. Jitter Transfer is defined to be less than 0.1 dB up to 2 MHz, then dropping at -20 dB decade thereafter, per ITU-T G.958 and Bellcore GR-253. The Jitter Transfer must be less than the following mask limits. Reference Loop Time is enabled with the RLPTIME input. In Reference Loop Time operation, a divide-by-4 version of the POCLKP/N output of the RX is used as the reference clock input to the TX. Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 3 Block Diagram 622 MHz Pclk TXFault BiasMonitor Data TXClk TXD 4 MUX &PLL 4:1 622 MHz RefClk TXD Laser Driver Laser Diode OC-48 1300 nm Lasercontrol 155.52 MHz D Fiber D Data SDSCLK 4 622 MHz Demux 1:4 D Clk Clk-Data Recovery PIN-Diode Preamp Postamp D Clk RXMonitor LoSynch Clk Osc. 155.52 MHz 20 ppm Los Functional Signal Description Signal Name Level I/O Pin # Description Transmit Functions LASER_ DISABLE LVTTL I 49 Laser Disable. Control input to disable Transmit laser. High = Disable laser. Pulled low through 1 k= resistor. TXLOCK LVTTL O 51 Loss Of Lock alarm for TX PLL of the Transceiver IC. High = Locked. Asynchronous output. PHASE_ERRP LVDS PHASE_ERRN O 45 43 Phase Error. Active high. PHASE_ERRP will pulses high during each clock cycle for which there is a potential set-up and hold timing violation between the internal byte clock of the Transceiver IC and the TXCLK timing domains. DC coupled and internally terminated. TX_FAULT LVTTL O 53 Transmit Fault alarm output. Indicates that the laser has been automatically shut off due to a fault in the TX laser circuit. High = TX Fault. Fault may be cleared by cycling DC power, or by strobing the RESET_L input. TX_BIASMON LVTTL O 59 Transmit Bias Monitor alarm output. Indicates that the bias current of the TX laser is currently outside normal operating limits. High = TX Bias outside limits. Signal Name Level I/O Pin # Description TXDATAP0 TXDATAN0 TXDATAP1 TXDATAN1 TXDATAP2 TXDATAN2 TXDATAP3 TXDATAN3 LVDS I TXCLKP TXCLKN LVDS REFCLKP REFCLKN LVPECL I PHASE_INITP LVDS PHASE_INITN Fiber Optics I I 1 3 7 9 13 15 19 21 Transmit Parallel input data at 622.08 Mb/s, aligned to the TXCLKP/N parallel input clock. TXDATAP/N[3] is the most significant bit (MSB), and is the first bit transmitted in the outgoing OC-48 serial data stream. TXDATAP/N[3:0] is sampled on the rising edge of TXCLKP. DC coupled and internally terminated. 27 25 Transmit Parallel input clock, 622.08 MHz, to which TXDATAP/N[3:0] is aligned. TXCLK transfers the data on the TXDATAP/ N inputs into a 4-bit wide latch in the Transceiver IC. Data is sampled on the rising edge of TXCLKP. DC coupled and internally terminated. 31 33 37 39 155.52 MHz Transmit Reference Clock input to the bit clock frequency synthesizer of the Transceiver IC. DC coupled and internally biased. Phase Initialization. Rising edge of PHASE_INITP will realign internal timing. DC coupled. No internal termination. V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 4 Signal Name Level I/O Pin # Description PCLKP PCLKN LVDS O RESET_L LVTTL I 10 8 56 Loopback Modes Signal Name 622.08 MHz Parallel Clock output. Generated by dividing the internal high-speed TX clock by 4. Master Reset input. A Low level resets the TX Mux and Laser Driver. RESET_L must be held low for at least 6 millisec. Pulled high through a 1 k resistor. Level I/O Pin # Description LLEB_L LVTTL I 38 Line Loopback Enable input. A Low level enables Line Loopback mode. When active, the RX inputs to the Transceiver IC will be routed directly to the TX outputs. Pulled high through a 1 k resistor. DLEB_L LVTTL I 40 Diagnostic Loopback Enable input. A Low level enables Diagnostic Loopback mode. When active, the TX outputs of the Transceiver IC are routed directly to the RX inputs. Pulled high through a 1 k resistor. RLPTIME LVTTL I 4 Reference Loop Time Enable input. A High level enables Reference Loop Time. When active, a divide-by-4 version of the POCLKP/N output of the RX is used as the reference clock input to the TX. Pulled low through a 1 k resistor. SLPTIME LVTTL I 2 Serial Loop Time Enable input. A High level enables Serial Loop Time. When active, the recovered high-speed clock (RSCLKP/N) from the RX section is used in place of the synthesized transmit clock. Pulled low through a 1 k resistor. Receive Functions Signal Name Level I/O Pin # Description RXDATAP0 RXDATAN0 RXDATAP1 RXDATAN1 RXDATAP2 RXDATAN2 RXDATAP3 RXDATAN3 O SDSCLKN SDSCLKP RX_LOS LVDS LVDS O LVTTL O 44 42 34 32 28 26 22 20 16 14 55 Parallel Output Data at 622.08 Mb/s from the Receiver, aligned to the Parallel Output Clock (RXCLKP/N). RXDATAP/N[3] is the Most Significant Bit, and is the first bit received in the incoming OC-48 serial data stream. RXDATAP/N[3:0] is clocked out on the falling edge of SDSCLKP. All data outputs are forced to zero level under Loss Of Signal or Loss Of Synchronization conditions. DC coupled outputs. Internally terminated. Parallel Output Clock from the Receiver at 622.08 MHz. This clock is aligned to the RXDATAP/N[3:0] parallel output data. RXDATAP/N[3:0] is clocked out on the falling edge of SDSCLKP. Clock output is continuous under Loss Of Signal or Loss Of Synchronization conditions. DC coupled output. Internally terminated. Signal Name LVTTL O 57 Receive Loss Of Synchronization alarm output. A High output level indicates that the receive Clock Recovery unit has lost synchronization, due to either very low RX input power level, or input data rate outside of frequency tolerance. RX_MON Analog O 58 Receive power monitor output. A voltage output which is directly proportional to the optical RX input power. Level GROUND 0 V DC Receive Loss Of Signal alarm output. A High output level indicates RX input power is below the sensitivity level of the receiver (high BER condition). RX_LOSYNC Fiber Optics DC Power VCC I/O Pin # Description I Ground connection for both signal and chassis ground on the transponder. The blade contact of the 60 pin interface connector is tied to ground in the transponder. Therefore, the blade of the user`s mating connector should be connected to ground, as well. +3.3 V DC I 5,6, 11,12, 17,18, 23,24, 29,30, 35,36, Blade 41,47, DC Power Input. +3.3 V DC, 46,48, nominal. 50,52, 54 V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 5 Functional Diagrams DC Electrical Characteristics Parameter TX Input Timing Diagram RX Output Timing Diagram Symbol Min. Typ. Max. Units V LVDS Input High Volt- LVDS VIH age 1.1 1.9 LVDS Input Low Volt- LVDS VIL age 0.6 1.5 LVDS Input Voltage Differential LVDS VINDIFF 200 1200 LVDS Input Single Ended Voltage LVDS VINSING 100 600 LVDS Differential Input Resistance LVDS RDIFF 80 LVDS Output High Voltage LVDS VOH LVDS Output Low Voltage mV 120 1.13 1.8 V LVDS VOL 0.7 1.4 LVDS Output Differential Voltage LVDS VOUTDIFF 440 740 1100 LVDS Output Single Ended Voltage LVDS VOUTSIN- 220 370 550 100 mV GLE TECHNICAL DATA LVPECL Input Low Voltage LVPECL VIL VCC -1.9 VCC -1.4 Recommended Operating Conditions LVPECL Input High Voltage LVPECL VIH VCC -1.1 VCC -0.55 LVPECL VINSINGLE 200 1200 Parameter Symbol Min. Typ. Max. Units 70 oC LVPECL Input Single Ended Swing 2.8 3.46 W LVPECL Input Differ- LVPECL ential Swing VINDIFF 400 2400 3.3 3.46 V LVPECL Input DC Bias LVPECL VBIAS VCC -0.5 VCC -0.3 0.85 1.0 A 2.0 VCC mV 0-p LVTTL Input High Voltage LVTTL VIH 15 LVTTL Input Low Voltage LVTTL VIL 0 0.8 Note 1. TCASE is measured on top of the transponder (see details on page 1, outline dimensions) LVTTL Input High Current LVTTL IIH LVTTL Output Current LVTTL IO LVTTL Output High Voltage LVTTL VOH 2.4 LVTTL Output Low Voltage LVTTL VOL Operating Case Tempera- TC ture(1) 0 Transponder Total Power PTOT Consumption 3.3 V Supply Voltage VCC 3.3 V Supply Current ICC Input Differential Noise, All Pins NDIFF Fiber Optics 3.13 50 V mV V A -500 V 0.8 V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 6 AC Electrical Characteristics Parameter Sym- Condibol tions Min. Typ. Max. Units Parameter Transmitter Sym- Condibol tions Min. Typ. Max. Units Receiver TXDATAP/N[3:0] Input Bit Rate 622.08 Mb/s RXDATAP/N[3:0] Output Bit Rate 622.08 Mb/s TXCLKP/N Input Frequency 622.08 MHz SDSCLKP/N Output Frequency 622.08 MHz 60 % SDSCLKP/N Output Duty Cycle ps SDSCLKP/N Output Rise/Fall Time TXCLKP/N Input Duty Cycle 40 TXCLKP/N Input Rise/Fall Time 20-80% 100 300 TXDATA Setup TST Time with respect to the Rising edge of TXCLKP See TX Timing Diagram 200 TXDATA Hold THT Time with respect to the Rising edge of TXCLKP See TX Timing Diagram 200 REFCLKP/N Input Frequency 155.520 REFCLKP/N Input Frequency Tolerance REFCLKP/N Input Duty Cycle REFCLKP/N Input Rise/Fall Time 45 10-90% Return Loss, All AC Inputs & Outputs RESET_L Input Min. Pulse Width Fiber Optics ppm 55 % 500 ps 1 3.2 PCLKP/N Output Frequency PCLKP/N Output Duty Cycle 20 60 % 20-80% 100 300 ps RXDATA Setup TSR Time with respect to the Falling edge of SDSCLKP See RX Timing Diagram 600 RXDATA Hold THR Time with respect to the Falling edge of SDSCLKP See RX Timing Diagram 600 Return Loss, all AC Inputs & Outputs 10 MHz 15 - 1 GHz SDSCLKP/N Output Frequency Accuracy during LOS or LOSYNC(1) Over operating Temp Range dB 20 ppm Notes REFCLKP/N Input Jitter(2) PHASE_INITP/N Input Min. Pulse Width MHz 40 10 MHz 15 - 1 GHz 6 2. Maximum allowable jitter on the reference clock input (REFCLKP/N) such that the transmitter will meet ITU-T G.958 and Bellcore GR-253 Jitter Generation requirements. Measured with a 12 KHz - 20 MHz filter. ns 622.08 45 1. TCASE is measured on top of the transponder (see details on page 1, outline dimensions) ps, rms MHz 55 % dB ms V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 7 Transmitter Electro-Optical Characteristics Min. Parameter Symbol Nominal Center Wavelength TX NOM 1310 Range Of Center Wavelengths TX MIN- 1260 MAX 1360 Spectral Bandwidth TX RMS 5 Average Output Power(1) TX PAVG -3 Extinction Ratio TX ER Output Rise Time 20%-80% TX TR 100 200 Output Fall Time 80%-20% TX TF 175 250 Eye Diagram(2) TX ED TX Jitter Generation, rms(3) TX JGEN rms 0.007 0.01 TX Jitter Generation, p-p(3) TX JGEN p-p 0.075 0.1 Reset Threshold for VCC(4) TX VTH Power On Delay for VCC(4) TX TPOD Fault Delay(5) TX TFAULT TX Bias Monitor switching threshold TX IBIAS -10 Typ. Receiver Electro-Optical Characteristics Max. Units Parameter Symbol Nominal Center Wavelength RX NOM 1310 Sensitivity (Average Power)(1) RX PSENS -25 nm, rms Overload (Average Power)(1) RX POL -3 dBm Optical Return Loss RX RL 27 nm -4 RX Jitter 8.2 14 2.2 dB 2.95 20 Typ. Max. Units nm -18 dBm dB RX JTOL RX-to-TX Jitter Trans- RX-TX JXFR fer(3) ps Optical Path Penalty RX PPEN Clock Recovery Capture Frequency Range(5) RX FCAPT 200 UI rms Clock Recovery Acquisition Lock Time RX TLOCK 32 UI p-p RX_LOS Output As- RX_ LOSASSERT sert relative To RX Optical Input Power(4) V RX_LOSYNC Output Assert relative to RX input frequency(5) ms RX_ LOSYNCAS- mA Notes RX_LOS & RX_LOSYNC Output Deassert Time(4, 5) 1. The laser driver contains a control circuit, which regulates the average optical output power. Nominal output power is factory set to be within the specified range. 2. The Eye Diagram is compliant with Bellcore GR-253 and ITU-T G.957 Eye Mask specifications. 3. Jitter Generation is defined as the amount of jitter on the TX Optical Output, when there is no or minimum jitter on the TX electrical inputs. Jitter Generation is compliant with GR-253 and ITU-T G.958 specifications, when measured using a 12 KHz - 20 MHz filter, and with a jitter level on the REFCLKP/N input which is less than the level specified in "AC Electrical Characteristics - Transmitter". 4. If the +3.3 V power supply drops below the specified level, the laser bias and modulation currents will be held disabled until the supply voltage rises above threshold and after the Power On Delay Time period. 1.0 -30 450 dB ppm 250 s -25 dBm 600 770 ppm SERT RX_LOS Output Hys- RX_ LOSHYST teresis(4) RX_LOS & RX RX_LOSYNC Output TASSERT Assert Time(4, 5) 20 60 Tolerance(2) Min. RX TDEASSERT 3 100 dB s 100 RX_MON Transfer Slope(6) 4.4 mV/ W RX_MON Dark Offset Voltage(6) 53 mV RX_MON Output Voltage at PIN = -17 dBm(6) 142 RX_MON Output Voltage at PIN = -7 dBm(6) 900 Notes 1. Average RX power for a 1x10-10 BER, and using a PRBS pattern of 223-1 length with 72 zeros and 72 ones inserted, as per ITU-T G.958. 5. A fault, such as high laser bias current or high average power, which lasts longer than the specified Fault Delay time, will cause the transmitter to be disabled. The fault can be cleared by cycling of DC power, or by strobing the RESET_L input. 2. Jitter Tolerance is defined as the amount of jitter applied to the RX optical input that the receiver will tolerate without producing bit errors. The minimum required Jitter Tolerance for a 1 dB power penalty is defined to be 15 UI from 10 Hz to 600 Hz, 1.5 UI from 6 KHz to 100 KHz, and 0.15 UI from 1 MHz onwards, per Bellcore GR-253. 3. Jitter Transfer is defined as the ratio of TX Output Jitter to RX Input Jitter, when the transponder is operated in electrical loopback mode (RX electrical outputs looped back into TX electrical inputs). Jitter Transfer is specified to be less than 0.1 dB up to 2 MHz, and dropping at -20 dB/Decade after that point, per ITU-T G.958 and Bellcore GR-253. 4. The RX_LOS output is an active high LVTTL output, which is set HIGH if there is a loss of RX optical signal input (LOS), A decrease in optical input power below the assert level will cause the RX_LOS Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 8 Agency Certifications output to switch HIGH (ON). Hysteresis occurs when the optical input power is raised back above the threshold switching level. The RX_LOSYNC output is an active high LVTTL output, which is set HIGH if the Clock Data Recovery PLL becomes unlocked. Loss Of Sync will occur at a lower optical input power level than LOS, but still within the specified input power range. 5. The receiver lock range is typically 300 ppm from nominal OC-48 data rate. When the data rate of the RX signal deviates by more than 600 ppm (typically) from nominal, or if the RX is in a Loss Of Signal (LOS) condition, then the Clock Recovery module will lock to an internal 155.52 MHz crystal oscillator. Under this condition: The appropriate fault output (RX_LOS or RX_LOSYNC) switches active; The RXDATAP/N[3:0] output data is forced to all zeros; and, the switching of the SDSCLKP/N output is done so that the clock is continuous, and there are no violations of the minimum pulse width and period. 6. RX_MON ouput voltage is measured between VCC (+) and RX_MON (-). RX_MON is specified up to a maximum optical input average power of -5 dBm (316.2 W). Feature Standard Electrostatic Discharge (ESD) to the Electrical Pins EIA/JESD22-A114-A Class 1 (2000 V) (MIL-STD 883D Method 3015.7) Immunity: EN 61000-4-2 Electrostatic IEC 61000-4-2 Discharge (ESD) to Housing/Pigtails Discharges ranging from 2 kV to 15 kV on housing/pigtails cause no damage to transponder (under recommended conditions). Immunity: Radio Frequency Electromagnetic Field With a field strength of 10 V/m rms, noise frequency ranges from 10 MHz to 2 GHz. No effect on transponder performance between the specification limits. Pin # Signal Name Pin # Signal Name 1 TXDATAP0 2 SLPTIME 3 TXDATAN0 4 RLPTIME 5 GND 6 GND 1,6 7 TXDATAP1 8 PCLKN 1,4 9 TXDATAN1 10 PCLKP 11 GND 12 GND 13 TXDATAP2 14 SDSCLKP RX_MON Voltage (V) Typical RX_MON Characteristic (Linear) 1,2 1 15 TXDATAN2 16 SDSCLKN 17 GND 18 GND 19 TXDATAP3 20 RXDATAN3 21 TXDATAN3 22 RXDATAP3 0,4 23 GND 24 GND 0,2 25 TXCLKN 26 RXDATAN2 27 TXCLKP 28 RXDATAP2 29 GND 30 GND 31 REFCLKP 32 RXDATAN1 33 REFCLKN 34 RXDATAP1 35 GND 36 GND 37 PHASE_INITP 38 LLEB_L 1,6 1,4 40 DLEB_L VCC 42 RXDATAN0 43 PHASE_ERRN 44 RXDATAP0 45 PHASE_ERRP 46 VCC 47 VCC 48 VCC 49 LASER_DISABLE 50 VCC 51 TXLOCK 52 VCC 53 TX_FAULT 54 VCC 55 RX_LOS 56 RESET_L 57 RX_LOSYNC 58 RX_MON 59 TX_BIASMON 60 SPARE BLADE GND Fiber Optics 0,8 0,6 0 0 0,1 0,2 0,3 RX Input Average Power (mW) Typical RX_MON Characteristic (Logarithmic) RX_MON Voltage (V) PHASE_INITN 41 EN 61000-4-3 IEC 61000-4-3 Emission: FCC Part 15, Class B Noise frequency range: Electromagnetic EN 55022 Class B 250 MHz to 18 GHz Interference (EMI) CISPR 22 Connector Pin Assignments 39 Comments 1,2 1 0,8 0,6 0,4 0,2 0 -25 -20 -15 -10 -5 RX Input Average Power (dBm) V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 9 EYE SAFETY APPLICATION NOTES This laser based single mode transponder is a Class 1 product. It complies with IEC 60825-1 and FDA 21 CFR 1040.10 and 1040.11. INTERFACING THE 4-LINE TRANSPONDER The transponder has been certified with FDA under accession number 9911449-03. This Application Note is meant to define the interfacing between the Infineon 4-Line OC-48 Transponder, and the customer equipment. Scope To meet laser safety requirements the transponder shall be operated within the Absolute Maximum Ratings. Introduction Caution The signals which interface to the OC-48 Transponder can be grouped into Transmit (TX) and Receive (RX) functions. All adjustments have been made at the factory prior to shipment of the devices. No maintenance or alteration to the device is required. Tampering with or modifying the performance of the device will result in voided product warranty. The TX signals are: TXDATAP/N[0..3]: 4 differential LVDS inputs for TX Data. TXCLKP/N: A differential LVDS input for TX Clock. REFCLKP/N: A differential LVPECL input for TX Reference Clock. PHASE_INITP/N: A differential LVDS input for Phase Initialization of the TX Mux. PHASE_ERRP/N: A differential LVDS output for Phase Error of the TX Mux. Note Failure to adhere to the above restrictions could result in a modification that is considered an act of "manufacturing", and will require, under law, recertification of the modified product with the U.S. Food and Drug Administration (ref. 21 CFR 1040.10 (i)). Laser Data The RX signals are: Wavelength 1310 nm Total output power (as defined by IEC: 50 mm aperture at 10 cm distance) 2 mW RXDATAP/N[0..3]: 4 differential LVDS outputs for RX Data. SDSCLKP/N: A differential LVDS output for RX Clock. Total output power (as defined by FDA: 7 mm aperture at 20 cm distance) 180 W Interfacing Beam divergence 5 Interfacing Diagram Required Labels FDA IEC Complies with 21 CFR 1040.10 and 1040.11 Class 1 Laser Product Laser Emission Pigtail SC or LC Top view Indication of laser aperture and beam TX Signals The customer OC-48 framer drives the TXDATA and TXCLK inputs. In order to use DC Coupling, the framer should be a +3.3 V LVDS device. Each of the inputs is terminated with 100 differential between lines in the transponder. The PHASE_ERR output is not true LVDS, but is LVDS level compatible, which uses a 330 to ground termination in the transponder. The PHASE_INIT input is LVDS. In normal operation, PHASE_INITP is directly connected to PHASE_ERRP, and PHASE_INITN is directly connected to PHASE_ERRN. These connections must be made on the customer board. The REFCLK input is a LVPECL input, which is driven by the customer Clock Source, which should be an LVPECL device. DC Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 10 coupling is acceptable if the clock source is a +3.3 V LVPECL. The REFCLK input is terminated with 100 differential between lines in the transponder. It is necessary for the customer to provide the external 330 resistors to ground for the source termination. Interface Connector The transponder interface connector is a 60 pin SMT, dual row, header, 0.5 mm pitch, with ground blade, Samtec part number QTH-030-01-L-D-A. The appropriate mating connector for the customer pcb is a 60 pin SMT, dual row, socket, 0.5 mm pitch, with mating alignment pins, Samtec part number QSH-030-01-LD-A. The internal blade of the connector should be connected to signal ground on the user's pcb. Contact Samtec for recommended pcb layout pattern for QSH connector. RX Signals The customer framer accepts as input the RXDATA and RXCLK outputs of the transponder. In order to use DC Coupling, the framer should be a +3.3 V LVDS device. The RXDATA and SDSCLK outputs of the transponder are not true LVDS, but are LVDS level compatible, which use a 330 to ground termination in the transponder. If the framer does not have a 100 differential termination between lines, then the customer will have to supply the terminations on their board. Hostboard Contact Area Dimensions in mm [inches] Line Impedance 2) 1) 1) 1) For proper impedance matching, all LVDS traces should be constructed as a differential trace pair, with 100 characteristic impedance between the lines of each pair, and 50 characteristic impedance per line. The LVPECL traces should be constructed as 50 per line. CONVERSION OF RX_MON OUTPUT TO A VOLTAGE WITH RESPECT TO GROUND 1) 1) 2) 1) MECHANICAL 1) 1) 1) The outline size for the transponder housing is 2.3 in x 1.6 in x 0.54 inches. Please refer to the outline drawing. 1) 2) Size Fiber & Connectors The transponder has fiber pigtails for both TX and RX. The TX pigtail is Single Mode Fiber, 9 m/125 m. The RX pigtail is Multi Mode Fiber, 50 m/125 m, allowing a highly tolerant coupling with a Single Mode Fiber. Each pigtail is terminated with a LC/PC or SC/PC optical connector with 0 o polish. The minimum bend radius of the fiber pigtails is 30 mm (1.18 inches), typical. The fiber length see Ordering Information on page 1, as measured from the transponder housing to the tip of the connector. 1) 2) For detailed connector layout information, check http://www.samtec.com, and go to "QSH" connector. Fiber Optics V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km 11 For the guaranteed EMI-performance an optimal electrical contact between the transponder housing and the user's pcb signal ground is necessary. For the user's pcb (hostboard) we recommend a full signal ground plane underneath the entire transponder housing (including the standoff area, the EMI gasket area and the optional heatsink area). Scheme of tightening mounting screws The transponder is equipped with an attached EMI gasket. According to the drawing "Hostboard Contact Area" the contact surface of the entire EMI gasket should be connected to signal ground on the user's pcb. The area under the EMI gaskets (EMI gasket area) should be gold flash or tin plated copper with no solder mask or other nonconductive coatings. In order to avoid a mechanical stress of the users PCB and to reduce the impacting forces (twisting or wresting of the PCB) we recommend a crosswise tightening of the 4 mounting screws. The four mounting screws of the housing also must be connected to signal ground on the user's pcb. Therefore the mounting screw areas should have square pads of gold flash or tin plated copper, that are connected to signal ground. These pads are located on the pcb opposite side to the transponder. Use a torque wrench to tighten the mounting screws. The recommended torque value is 10 2 Ncm = 0.1 0.02 Nm = 14.16 2.83 oz-in. With a higher or lower value, the EMI-performance will deteriorate. The heatsink area under the center of the transponder is optional and could be used for critical ambient temperature or critical airflow. Currently it is not a complete replacement for the regular heatsink. The contact area should be connected to signal ground. Gold (Au), Tin or other metal platings are recommended for good heat transfer. Any polymer coating will decrease the heatsinking performance. Special heat transfer pads are in progress. For reliable heatsinking to the hostboard, the max. hostboard temperature must be lower or equal to the specified ambient air temperature. It is recommended to use a torque wrench to tighten the mounting screws. Tightening torque value is: 10 2 Ncm = 0.1 0.02 Nm = 14.16 2.83 oz-in. With a higher or lower value, the EMI-performance will deteriorate. Scheme Please tighten the screws according to the following scheme: 1. Insert four screws and tighten them very loose in the following order: 1 3 4 2 2. Tighten the four screws hand-screwed in the following order: 2 4 3 1 3. Tighten the four screws with a torque wrench 10 2 Ncm = 0.1 0.02 Nm 14.16 2.83 oz-in in the following order: 3 1 2 4 Published by Infineon Technologies AG Warnings (c) Infineon Technologies AG 2001 All Rights Reserved Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your Infineon Technologies offices. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact the Infineon Technologies offices or our Infineon Technologies Representatives worldwide - see our webpage at www.infineon.com/fiberoptics Infineon Technologies AG * Fiber Optics * Wernerwerkdamm 16 * Berlin D-13623, Germany Infineon Technologies, Inc. * Fiber Optics * 1730 North First Street * San Jose, CA 95112, USA Infineon Technologies K.K. * Fiber Optics * Takanawa Park Tower * 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku * Tokyo 141, Japan