Flash-Erasable Reprogrammable
CMOS PAL® Device
PALCE16V8
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03025 Rev. *A Revised April 22, 2004
Features
• Active pull-u p on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI-compliant
• User-programmable macrocell
— Output polarity control
— Individua lly selectable for registered or combina-
torial operation
• Up to 16 input terms and eight outputs
• 7.5 ns com’l version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
• 10 ns military/industri al versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
• High reliability
— Proven Flash technology
— 100% programmin g and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
8888888 8
10987654321
11 12 13 14 15 16 17 18 19 20
PROGRAMMABLE
AND ARRAY
(64 x 32)
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
GND I8I7I6I5I4I3I2I1CLK/I0
OE/I9I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7VCC
Logic Block Diagram (PDIP/CDIP)
Pin Configurations PLCC/LCC
Top View
18
17
16
15
14
4
5
6
7
89 10111213
321 19
I
I
CLK/I
I/O
20
VCC
OE/I
I/O
I/O
CLK/I0
I1
I2
I3
I4
I8
GND OE/I9
VCC
I/O7
I/O6
I/O4
I/O3
I/O2
I/O0
I/O5
I5
I6
I7I/O1
1
2
3
4
5
6
7
8
9
10 11
12
16
15
14
13
17
20
19
18
DIP
I3
I4
I5
I6
I7
2
1
0
7
I/O6
I/O4
I/O3
I/O2
I/O5
8
I
GND
9
0
1
Top View
PALCE16V8
Document #: 38-03025 Rev. *A Page 2 of 13
Functional Description
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip
carrier, and a 20-lead square plastic leaded chip carrier.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
The PALCE16V8 features 8 pr oduct terms per output an d 32
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that a pply to al l macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is pro gra mmed.
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology , and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Selection Guide
Generic Part Number tPD ns tS ns tCO ns ICC mA
Com’l/Ind Mil Com’l/Ind Mil Com’l/Ind Mil Com’l Mil/Ind
PALCE16V8-5 534115
PALCE16V8-7 7.5 7 5 115
PALCE16V8-10 10 10 10 10 710 90 130
PALCE16V8-15 15 15 12 12 10 10 90 130
PALCE16V8-25 25 25 15 20 12 12 90 130
PALCE16V8L-15 15 15 12 12 10 12 55 65
PALCE16V8L-25 25 25 15 20 12 20 55 65
Shaded areas contain preliminary information.
Configuration Table
CG0CG1CL0xCell Configuration Devices Emulated
0 1 0 Registered Output Registered Med PALs
0 1 1 Combinatorial I/O Registered Med PALs
1 0 0 Combinatorial Output Small PALs
1 0 1 Input Small PALs
1 1 1 Combinatorial I/O 16L8 only
PALCE16V8
Document #: 38-03025 Rev. *A Page 3 of 13
Macrocell
Q
QD
CLK
1
1
0
0
1
X
CL1x
0
1
X
0
11
I/Ox
From
Adjacent
Pin
CL0x
CG1for pin 13 to 18
CG0for pin 12 and 19
1
0
0
1
11
00
0
1X
0
11OE
VCC
To
Adjacent
Macrocell
CL0x
CG1
VCC
PALCE16V8
Document #: 38-03025 Rev. *A Page 4 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ............. ....................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)............ ... ............................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State................ ...............................–0.5V to +7.0V
DC Input Voltage .............. ... ...........................–0.5V to +7.0V
Output Current into Outputs (LOW).............................24 mA
DC Programming Voltage.................. ... ... .....................12.5V
Latch-Up Current....................................................> 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +75°C 5V ±5%
Military[1] –55°C to +125°C 5V ±10%
Industrial –40°C to +85°C5V ±10%
Electrical Characteristics Over the Operatin g Range[2]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
VIN = VIH or VIL IOH = –3.2 mA Com’l 2.4 V
IOH = –2 mA Mil/Ind
VOL Output LOW Voltage VCC = Min.,
VIN = VIH or VIL IOL = 24 mA Com’l 0.5 V
IOL = 12 mA Mil/Ind
VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 V
VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] –0.5 0.8 V
IIH Input or I/O HIGH Leakage
Current 3.5V < VIN < VCC 10 µA
IIL[5] Input or I/O LOW Leakage
Current 0V < VIN < VIN (Max.) –100 µA
ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7] –30 –150 mA
ICC Operating Power Supply
Current VCC = Max.,
VIL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
(counter)
5, 7 ns Com’l 115 mA
10, 15, 25 ns 90 mA
15L, 25L ns 55 mA
10, 15, 25 ns Mil/Ind 130 mA
15L, 25L ns Mil. 65 mA
15L, 25L ns Ind. 65 mA
Capacitance[7]
Parameter Description Test Conditions Typ. Unit
CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5 pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 5 pF
Endurance Characteristics[7]
Parameter Description Test Conditions Min. Max. Unit
N Minimum Reprogramming Cycles Normal Programming Conditions 100 Cycles
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. A ll ove rshoots due to system or tester noise are included.
4. VIL (Min.) is equal to –3.0V for pulse durations less than 20 ns.
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
PALCE16V8
Document #: 38-03025 Rev. *A Page 5 of 13
AC Test Loads and Waveforms
Specification S1CL
Commercial Military Measured Output ValueR1R2R1R2
tPD, tCO Closed 50 pF 200Ω390Ω390Ω750Ω1.5V
tPZX, tEA Z · H: Open
Z · L: Closed 1.5V
tPXZ, tER H · Z: Open
L · Z: Closed 5 pF H · Z: VOH – 0.5V
L · Z: VOL + 0.5V
Commercial and Industrial Switching Characteristics[2]
Parameter Description 16V8-5 16V8-7 16V8-10 16V8-15 16V8-25 Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPD Input to Output
Propagation Delay[8, 9] 15 3 7.5 3 10 3 15 3 25 ns
tPZX OE to Output Enable 16 6 10 15 20 ns
tPXZ OE to Output Disable 15 6 10 15 20 ns
tEA Input to Output
Enable Delay[7] 16 9 10 15 25 ns
tER Input to Output
Disable Delay[7, 10] 15 9 10 15 25 ns
tCO Clock to Output Delay[8, 9] 142527210212ns
tSInput or Feedback
Set-up Time 35 7.5 12 15 ns
tHInput Hold Ti me 0000 0 ns
tPExternal Clock
Period (tCO + tS)710 14.5 22 27 ns
Shaded areas conta in preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in a given access cycle.
10.This parameter is measured as th e time after O E pin or internal disable input di sables or enables the outp ut pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below VOH min. or a pre vious LOW level has rise n to 0.5 volt s above VOL max.
11. This specification indicates the guaranteed maximum frequency at which a state machine configurat ion with external feedback can operate.
12.This specification indicates the guarante ed maximum frequency at which the device can operate in data path mode.
13.This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14.This parameter is calculated from the clock period at f MAX internal (1/fMAX3) as measured (see Note 7 above) minus tS.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
<2ns <2ns
OUTPUT
R2
R1
CL
S1
5V
TEST POINT
PALCE16V8
Document #: 38-03025 Rev. *A Page 6 of 13
tWH Clock Width HIGH[7] 346812ns
tWL Clock Width LOW[7] 346812ns
fMAX1 External Maximum
Frequency (1/(tCO + tS))[7, 1 1] 143 100 69 45.5 37 MHz
fMAX2 Dat a Path Maximum
Frequency (1/(tWH + tWL))[7, 12] 166 125 83 62.5 41.6 MHz
fMAX3 Internal Feedback
Maximum Frequency
(1/(tCF + tS))[7, 13]
166 125 74 50 40 MHz
tCF Register Clock to
Feedback Input[7, 14] 3 3 6 8 10 ns
tPR Power-Up Reset Time[7] 1111 1 µs
Commercial and Industrial Switching Characteristics (continued)[2]
Parameter Description 16V8-5 16V8-7 16V8-10 16V8-15 16V8-25 Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Military Switching Characteristics[7]
16V8-10 16V8-15 16V8-25
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tPD Input to Output
Propagation Delay[8, 9] 310315325ns
tPZX OE to Output Enable 10 15 20 ns
tPXZ OE to Output Disable 10 15 20 ns
tEA Input to Output Enable Delay[7] 10 15 25 ns
tER Input to Output Disable Delay[7, 10] 10 15 25 ns
tCO Clock to Output Delay[8, 9] 27210212ns
tSInput or Feedback Set-up Time 10 12 15 ns
tHInput Hold Time .5 .5 .5 ns
tPExternal Clock Period (tCO + tS)17 22 27 ns
tWH Clock Width HIGH[7] 6812ns
tWL Clock Width LOW[7] 6812ns
fMAX1 External Maximum Frequency
(1/(tCO + tS)[7, 11] 58 45.5 37 MHz
fMAX2 Data Path Maximum Frequency
(1/(tWH + tWL))[7, 12] 83 62.5 41.6 MHz
fMAX3 Internal Feedback Maximum
Frequency (1/(tCF + tS))[7, 13] 62.5 50 40 MHz
tCF Register Clock to
Feedback Input[7, 14] 6810ns
tPR Power-Up Reset Time[7] 111µs
PALCE16V8
Document #: 38-03025 Rev. *A Page 7 of 13
Switching Waveform
Power-Up Reset Waveform
tStHtWL
tWH
tP
tCO
tPD
tPXZ,t
ER
INPUTS, I/O,
REGISTERED
FEEDBACK
CP
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
tPXZ,t
ER
tEA,t
PZX
tEA,t
PZX
[10]
[10] [10]
[10]
tPR
POWER
CLOCK
tS
tWL
10%
REGISTERED
ACTIVE LOW
OUTPUTS
SUPPLY VOLTAGE
tPR MAX= 1 µs
90% VCC
PALCE16V8
Document #: 38-03025 Rev. *A Page 8 of 13
Functional Logic Diagram for PALCE16V8
0
116 20 24 28
00
12843119 23 27151173
2
19
0 1620242812843119 23 27151173 11
MC7
CL1=2048
CL0=2120
PTD=2128
-2135
3
18
MC6
CL1=2049
CL0=2121
PTD=2136
-2143
4
17
MC5
CL1=2050
CL0=2122
PTD=2144
-2151
5
16
MC4
CL1=2051
CL0=2123
PTD=2152
-2159
6
15
MC3
CL1=2052
CL0=2124
PTD=2160
-2167
7
14
MC2
CL1=2053
CL0=2125
PTD=2168
-2175
8
13
MC1
CL1=2054
CL0=2126
PTD=2176
-2183
9
12
MC0
CL1=2055
CL0=2127
PTD=2184
-2191
10 USER ELECTRONIC SIGNATURE ROW
BYTE0 BYTE1BYTE2BYTE3BYTE4 BYTE5 BYTE6 BYTE7
2056 2064 2072 2080 2088 2096 2104 2112 2119
MSB MSB LSBLSB
CG0=2192
CG1=2193
20
VCC
PRODUCTLINE FIRSTCELL NUMBERS
PIN NUMBERS INPUT LINE
NUMBERS
PIN NUMBERS
32
96
160
224
64
128
192
256 288
352
416
480
320
384
448
512 544
608
672
736
576
640
704
768 800
864
928
992
832
896
960
10241056
1120
1184
1248
1088
1152
1216
12801312
1376
1440
1504
1344
1408
1472
15361568
1632
1696
1760
1600
1664
1728
17921824
1888
1952
2016
1856
1920
1984
GLOBALARCHBITS
PALCE16V8
Document #: 38-03025 Rev. *A Page 9 of 13
Ordering Information
ICC
(mA) tPD
(ns) tS
(ns) tCO
(ns) Ordering Code Package
Name Packag e Type Operating
Range
115 534PALCE16V8-5JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
115 7.5 5 5 PALCE16V8-7JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8-7PC P5 20-Lead (300-Mil) Molded DIP
90 10 7.5 7 PALCE16V8 -10JC J61 20-Le ad Plastic Leaded Chip Carrier
PALCE16V8-10PC P5 20-Lead (300-Mil) Molded DIP
130 10 7.5 7 PALCE16V8-10JI J61 20-Le ad Plastic Leaded Chip Carrier Industrial
PALCE16V8-10PI P5 20-Lead (300-Mi l) Molded DIP
130 10 10 7 PALCE16V8-10DMB D6 20-Lead (300-Mil) CerDIP Mi litary
PALCE16V8-10LMB L61 20-Pin Square Leadless Chip Carrier
90 15 12 10 PALCE16V8-15JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8-15PC P5 20-Lead (300 -Mil) Molded DIP
130 15 12 10 PALCE16V8-15PI P5 20-Lead(300Mil) Molded DIP Industrial
PALCE16V8-15DMB D6 20-Lead (300-Mil) CerDIP Mi litary
PALCE16V8-15LMB L61 20-Pin Square Leadless Chip Carrier
90 25 15 12 PALCE16V8-25JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8-25PC P5 20-Lead (300 -Mil) Molded DIP
130 25 15 12 PALCE16V8-25JI J61 20-Lead Plastic Lea ded Chip Carrier Industrial
PALCE16V8-25DMB D6 20-Lead (300-Mil) CerDIP Mi litary
PALCE16V8-25LMB L61 20-Pin Square Leadless Chip Carrier
55 10 7.5 7 PALCE16V8L-10JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8L-10PC P5 20-Lead (300-Mil) Molded DIP
65 10 10 7 PALCE16V8L-10JI J61 20-Lead Plastic Leaded Chi p Carrier Industrial
PALCE16V8L-10PI P5 20-Lead (300-Mil) Molded DIP
55 15 12 10 PALCE16V8L-15JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8L-15PC P5 20-Lead (300-Mil) Molded DIP
65 15 12 10 PALCE16V8L-15DMB D6 20-Lead (300-Mil) CerDIP Military
PALCE16V8L-15LMB L61 20-Pin Square Leadless Chip Carrier
55 25 15 12 PALCE16V8L-25JC J61 20-Lead Plastic Leaded Chip Carrier Commercial
PALCE16V8L-25PC P5 20-Lead (300-Mil) Molded DIP Military65 25 15 12 PALCE16V8L-25DMB D6 20-Lead (300-Mil) CerDIP
PALCE16V8L-25LMB L61 20-Pin Square Leadless Chip Carrier
Shaded areas conta in preliminary information.
PALCE16V8
Document #: 38-03025 Rev. *A Page 10 of 13
MILITARY SPECIFICAT IONS
Group A Subgroup Testing
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tCO 9, 10, 11
tS9, 10, 11
tH9, 10, 11
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D-8 Config. A
51-80029-**
PALCE16V8
Document #: 38-03025 Rev. *A Page 11 of 13
Package Diagrams (continued)
20-Lead Plastic Leaded Chip Carrier J61
51-85000-*A
20-Square Leadless Chip Carrier L61
51-80049-**
PALCE16V8
Document #: 38-03025 Rev. *A Page 12 of 13
© Cypress Semi con duct or C orpo ra ti on , 20 04 . The i nfo r mat ion con tained here i n is su bject to change wit hout notice. Cypr ess S em iconduct or Corpo ration assu mes no resp onsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cy press. Furtherm ore, Cypress doe s not authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Ultra37000 is a trademark o f Cypress Semiconductor Corporation. PAL is a registere d trademark of Advanced Micro Device s,
Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85011-*A
20-Lead (300-Mil) Molded DIP P5
PALCE16V8
Document #: 38-03025 Rev. *A Page 13 of 13
Document History Page
Document Title: PALCE16V8 Flash Erasable Reprogrammable CMOS PAL® Device
Document Number: 38-03025
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106370 07/11/01 SZV Change from Spec Number: 38-00364 to 38-03025
*A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”
