INDUSTRIAL TEMPERATURE RANGE
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
1JANUARY 2004INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC-4949/2
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µµ
µµ
µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in TSSOP package
FUNCTIONAL DIAGRAM
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
STATE DIAGRAM
IDT74LVC163A
DESCRIPTION:
The LVC163A is a synchronous presettable binary counter, which
features an internal look-ahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all the flip-flops
clocked simultaniously on the positive-going edge of the clock (CP).
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
COUNTER WITH SYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
fmax = tp(max) (CP to TC) + tsu (CEP to CP)
1
01234
5
6
7
8
9
101112
13
14
15
Outputs (Q0 to Q3) may be preset to a high or low level. A low level at the
parallel enable input (PE) disables the counting action and causes the data
at the data inputs (D0 to D3) to be loaded into the counter on the positive-going
edge of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count enable
inputs (CEP and CET). A low level at the master reset input (MR) sets all
four outputs of the flip-flops (Q0 to Q3) to low level after the next positive-going
transition on the clock (CP) input (provided that the set-up and hold time
requirements for PE are met).
This action occurs regardless of the levels of CP, PE, CET, and CEP
inputs. This synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to a high level output of Q0. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up
time, according to the following formula:
PARALLEL LOAD
CIRCUITRY
BINARY COUNTER
3456
14 13 12 11
Q0Q1Q2Q3
D0D1D2D3
PE
CET
CEP
CP
MR
TC
9
10
7
2
1
15
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
FUNCTIONAL BLOCK DIAGRAM
FF1
D
CP
Q
Q
Q1
FF0
D
CP
Q
Q
Q0
D
CP
Q
Q
Q2
FF3
D
CP
Q
Q
FF2
Q3 TC
D2D1D0 D3
CET
CEP
PE
CP
MR
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
3
Pin Names Description
MR Asynchronous Master Reset (Active LOW)
CP Clock Input (LOW-to-HIGH, Edge-Triggered)
Dx Data Inputs
CEP Count Enable Inputs
GND Ground (0V)
PE Parallel Enable Input (Active LOW)
CET Count Enable Carry Input
Qx Flip-Flop Outputs
TC Terminal Count Output
Vcc Positive Supply Voltage
PIN DESCRIPTION
TYPICAL TIMING SEQUENCE
TSSOP
TOP VIEW
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 5.5 8 pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, –50 mA
IOK VI < 0 or VO < 0
ICC Continuous Current through each ±10 0 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
RESET PRESET COUNT INHIBIT
12 13 14 15 012
2
3
1
CP
VCC
MR
5
6
4
CEP 710 CET
15
14
16
12
11
13
D0
GND 89PE
TC
D1
D2
D3
Q0
Q1
Q2
Q3
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH(2) Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5µA
IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V, VIN = GND or VCC —— 10µA
ICCH
ICCZ
∆ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 50 0 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. Clock Pin (CP) requires a minimum VIH of 2.5V.
FUNCTION TABLE (1)
OPERATING INPUTS OUTPUTS
MODES MR CP CEP CET PE Dx Qx TC
Reset (clear) l ↑XXXX L L
Parallel load h ↑XXll L L
h↑XXlh H *
Count h ↑h h h X count *
Hold h X l X h X Q(2) *
(do nothing) h X X l h X Q(2) L
NOTE:
1. H = HIGH Voltage Level
h = HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW Voltage Level
l = LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = Don’t care
* = The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).
↑= LOW-to-HIGH clock transition
2. Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
5
OPERA TING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol Parameter Test Conditions Typical Unit
CPD Power Dissipation Capacitance CL = 0pF, f = 10Mhz — pF
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1 .7 —
VCC = 2.7V 2.2 —
VCC = 3V 2.4 —
VCC = 3V IOH = – 24mA 2 .2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6mA — 0.4
IOL = 12mA — 0.7
VCC = 2.7V IOL = 12mA — 0.4
VCC = 3V IOL = 24mA — 0.55
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Unit
tPLH Propagation Delay — 9 — 8 ns
tPHL CP to Qx
tPLH Propagation Delay — 11 — 9.5 ns
tPHL CP to TC
tPLH Propagation Delay — 8.8 — 7.8 ns
tPHL CET to TC
tWClock Pulse Width, HIGH or LOW 5 — 4 — ns
tSU Set-Up Time, Dx to CP 3.5 — 3 — ns
tSU Set-Up Time, MR, PE to CP 3 .5 — 3 — ns
tSU Set-Up Time, CEP, CET to CP 5.5 — 5 — ns
tHHold Time, Dx, PE, CEP, CET, MR to CP 0 — 0 — ns
tSK(o) Output Skew(2) — — — 500 ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
LVC QUAD Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x )
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUA D Li nk
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
SAME PH ASE
INPUT TRANSITION
OPPOSIT E PH AS E
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VT
VIH
VT
VT
VIH
VT
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
LVC QUA D Li nk
LVC QUA D Li nk
LVC QUAD Link
LVC QUAD Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Output Skew - tSK(X)Pulse Width
Symbol VCC(1)= 2.5V±0.2V VCC(2)= 3.3V±0.3V & 2.7V Unit
VLOAD 2 x Vcc 6 V
VIH Vcc 2.7 V
VTVcc / 2 1.5 V
VLZ 150 300 mV
VHZ 150 300 mV
CL30 50 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
7
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
IDT XX LVC XXXX XX
PackageDevice T ype
3.3V CMOS Presettable Synchronous 4-Bit Binary Counter with
Synchronous R eset, 5 Volt Tolerant I/O, ±24mA
163A
PG Thin Shrink Small Outline Package
Temp. Range
74 –40°C to +85°C
