AT24CM02-SSHM-T - MICROCHIP TECHNOLOGY

AT24CM02

I²C-Compatible (Two-Wire)

Serial EEPROM 2‑Mbit (262,144 x 8)

Features

• Low-Voltage and Standard-Voltage Operation:

– VCC = 1.7V to 5.5V

– VCC = 2.5V to 5.5V

• Internally Organized as 262,144 x 8 (2‑Mbit)

• Industrial Temperature Range: -40°C to +85°C

• I2C-Compatible (Two-Wire) Serial Interface:

– 100 kHz Standard mode, 1.7V to 5.5V

– 400 kHz Fast mode, 1.7V to 5.5V

– 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• Write-Protect Pin for Full Array Hardware Data Protection

• Ultra Low Active Current (3 mA maximum) and Standby Current (3 µA maximum)

• 256-byte Page Write Mode:

– Byte write and partial page writes allowed

• Random and Sequential Read Modes

• Self-Timed Write Cycle:

– All write operations complete within 10 ms maximum

• Built-in Error Detection and Correction

• High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

• Green Package Options (Lead-free/Halide-free/RoHS compliant)

• Die Sale Options: Wafer Form and Bumped Wafers

Packages

• 8-Lead SOIC and Thin or Standard Thickness 8-Ball WLCSP.

Table of Contents

Features.......................................................................................................................... 1

Packages.........................................................................................................................1

1. Package Types (not to scale).................................................................................... 4

2. Pin Descriptions.........................................................................................................5

2.1. Device Address Input (A2)........................................................................................................... 5

2.2. Ground......................................................................................................................................... 5

2.3. Serial Data (SDA).........................................................................................................................5

2.4. Serial Clock (SCL)........................................................................................................................5

2.5. Write-Protect (WP)....................................................................................................................... 6

2.6. Device Power Supply................................................................................................................... 6

3. Description.................................................................................................................7

3.1. System Configuration Using Two-Wire Serial EEPROMs ........................................................... 7

3.2. Block Diagram.............................................................................................................................. 8

4. Electrical Characteristics........................................................................................... 9

4.1. Absolute Maximum Ratings..........................................................................................................9

4.2. DC and AC Operating Range.......................................................................................................9

4.3. DC Characteristics....................................................................................................................... 9

4.4. AC Characteristics......................................................................................................................10

4.5. Electrical Specifications..............................................................................................................12

5. Device Operation and Communication....................................................................14

5.1. Clock and Data Transition Requirements...................................................................................14

5.2. Start and Stop Conditions.......................................................................................................... 14

5.3. Acknowledge and No-Acknowledge...........................................................................................15

5.4. Standby Mode............................................................................................................................ 15

5.5. Software Reset...........................................................................................................................16

6. Memory Organization.............................................................................................. 17

6.1. Device Addressing..................................................................................................................... 17

7. Write Operations......................................................................................................19

7.1. Byte Write...................................................................................................................................19

7.2. Page Write..................................................................................................................................19

7.3. Internal Writing Methodology......................................................................................................20

7.4. Acknowledge Polling.................................................................................................................. 20

7.5. Write Cycle Timing..................................................................................................................... 21

7.6. Write Protection..........................................................................................................................21

8. Read Operations..................................................................................................... 23

8.1. Current Address Read................................................................................................................23

8.2. Random Read............................................................................................................................ 23

AT24CM02

8.3. Sequential Read.........................................................................................................................24

9. Device Default Condition from Microchip................................................................ 25

10. Packaging Information.............................................................................................26

10.1. Package Marking Information.....................................................................................................26

11. APPENDIX A: Revision History............................................................................... 32

The Microchip Website..................................................................................................33

Product Change Notification Service.............................................................................33

Customer Support......................................................................................................... 33

Product Identification System........................................................................................34

Microchip Devices Code Protection Feature................................................................. 35

Legal Notice...................................................................................................................35

Trademarks................................................................................................................... 35

Quality Management System........................................................................................ 36

Worldwide Sales and Service........................................................................................37

AT24CM02

1. Package Types (not to scale)

8-Lead SOIC

(Top View)

NC 1

GND

VCC

SCL

SDA

8-Ball WLCSP

Thin or Standard Thickness

VCC

SCL

SDA

GND

(Top View)

AT24CM02

Package Types (not to scale)

2. Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table

Name 8‑Lead SOIC 8‑Ball WLCSP Function

NC 1 A3 No Connect

NC 2 B4 No Connect

A2(1)3 C4 Device Address Input

GND 4 D3 Ground

SDA 5 D2 Serial Data

SCL 6 C1 Serial Clock

WP(1)7 B2 Write-Protect

VCC 8 A2 Device Power Supply

Note:

1. If the A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a

wide variety of application environments, the pull-down mechanism is intentionally designed to be

somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point

(~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting these pins

to a known state whenever possible.

2.1 Device Address Input (A2)

The A2 pin is a device address input that is hard-wired (directly to GND or to VCC) for compatibility with

other two-wire Serial EEPROM devices. When the pin is hard-wired, as many as two devices may be

addressed on a single bus system. A device is selected when a corresponding hardware and software

match is true. If the pin is left floating, the A2 pin will be internally pulled down to GND. However, due to

capacitive coupling that may appear in customer applications, Microchip recommends always connecting

the address pin to a known state. When using a pull-up resistor, Microchip recommends using 10 kΩ or

less.

2.2 Ground

The ground reference for the power supply. GND should be connected to the system ground.

2.3 Serial Data (SDA)

The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the

device. The SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value)

and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on

the same bus.

2.4 Serial Clock (SCL)

The SCL pin is used to provide a clock to the device and to control the flow of data to and from the

device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL,

while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be

forced high when the serial bus is idle or pulled high using an external pull-up resistor.

AT24CM02

Pin Descriptions

2.5 Write-Protect (WP)

The write-protect input, when connected to GND, allows normal write operations. When the WP pin is

connected directly to VCC, all write operations to the protected memory are inhibited.

If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive

coupling that may appear in customer applications, Microchip recommends always connecting the WP

pin to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.

Table 2-2. Write-Protect

WP Pin Status Part of the Array Protected

At VCC Full Array

At GND Normal Write Operations

2.6 Device Power Supply

The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may

produce spurious results and should not be attempted.

AT24CM02

Pin Descriptions

3. Description

The AT24CM02 provides 2,097,152 bits of Serial Electrically Erasable and Programmable Read-Only

Memory (EEPROM) organized as 262,144 words of 8 bits each. The device's cascading feature allows up

to four devices to share a common two-wire bus. This device is optimized for use in many industrial and

commercial applications where low-power and low-voltage operations are essential. The device is

available in space-saving 8-lead SOIC and 8-ball WLCSP packages. All packages operate from 1.7V to

5.5V.

3.1 System Configuration Using Two-Wire Serial EEPROMs

I2C Bus Master:

Microcontroller

VCC

GND

SCL

SDA

RPUP(max) = tR(max)

0.8473 x CL

RPUP(min) = VCC - VOL(max)

IOL

Slave 0

AT24CXXX

VCC

SDA

SCL

GND

Slave 1

AT24CXXX

VCC

SDA

SCL

GND

VCC

AT24CM02

Description

3.2 Block Diagram

1 page

Start

Stop

Detector

GND

Memory

System Control

Module

High Voltage

Generation Circuit

Data & ACK

Input/Output Control

Address Register

and Counter

Write

Protection

Control

DOUT

DIN

Hardware

Address

Comparator

VCC

SCL

SDA

Power-on

Reset

Generator

EEPROM Array

Column Decoder

Row Decoder

Data Register

AT24CM02

Description

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

Temperature under bias -55°C to +125°C

Storage temperature -65°C to +150°C

VCC 6.25V

Voltage on any pin with respect to ground -1.0V to +7.0V

DC output current 5.0 mA

ESD protection >3 kV

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operation listings of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range

AT24CM02

Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C

VCC Power Supply Low-Voltage Grade 1.7V to 5.5V

Standard-Voltage Grade 2.5V to 5.5V

4.3 DC Characteristics

Table 4-2. DC Characteristics

Parameter Symbol Minimum Typical(1)Maximum Units Test Conditions

Supply Voltage,

1.7V Option

VCC1 1.7 — 5.5 V

Supply Voltage,

2.5V Option

VCC2 2.5 — 5.5 V

Supply Current,

Read

ICC — 0.1 0.5 mA VCC = 1.8V (2), Read at

400 kHz

— 0.3 1.0 mA VCC = 5.0V, Read at

1 MHz

AT24CM02

Electrical Characteristics

...........continued

Parameter Symbol Minimum Typical(1)Maximum Units Test Conditions

Supply Current,

Write(3)

ICC — 0.4 1.0 mA VCC = 1.8V (2),

averaged during tWR

— 1.7 3.0 mA VCC = 5.0V, averaged

during tWR

Standby Current ISB — 0.08 1.0 μA VCC = 1.8V (2), VIN =

VCC or VSS

— 0.08 2.0 μA VCC = 2.5V, VIN = VCC

or VSS

— 0.15 3.0 μA VCC = 5.5V, VIN = VCC

or VSS

Input Leakage

Current

ILI — 0.10 3.0 μA VIN = VCC or VSS

Output Leakage

Current

ILO — 0.05 3.0 μA VOUT = VCC or VSS

Input Low Level VIL -0.6 — VCC x 0.3 V Note 2

Input High Level VIH VCC x 0.7 — VCC + 0.5 V Note 2

Output Low Level VOL1 — — 0.2 V VCC = 1.7V, IOL =

0.15 mA

Output Low Level VOL2 — — 0.4 V VCC = 3.0V, IOL =

2.1 mA

Note:

1. Typical values characterized at TA = +25°C unless otherwise noted.

2. This parameter is characterized but is not 100% tested in production.

3. Averaged during tWR.

4.4 AC Characteristics

Table 4-3. AC Characteristics(1)

Parameter Symbol Standard Mode Fast Mode Fast Mode Plus Units

VCC = 1.7V to 5.5V VCC = 1.7V to 5.5V VCC = 2.5V to 5.5V

Min. Max. Min. Max. Min. Max.

Clock Frequency, SCL fSCL — 100 — 400 — 1000 kHz

Clock Pulse Width

Low

tLOW 4,700 — 1,300 — 500 — ns

Clock Pulse Width

High

tHIGH 4,000 — 600 — 400 — ns

AT24CM02

Electrical Characteristics

...........continued

Parameter Symbol Standard Mode Fast Mode Fast Mode Plus Units

VCC = 1.7V to 5.5V VCC = 1.7V to 5.5V VCC = 2.5V to 5.5V

Min. Max. Min. Max. Min. Max.

Input Filter Spike

Suppression

(SCL,SDA)(2)

tI— 100 — 100 — 50 ns

Clock Low to Data Out

Valid

tAA — 4,500 — 900 — 450 ns

Bus Free Time

between Stop and

Start(2)

tBUF 4,700 — 1,300 — 500 — ns

Start Hold Time tHD.STA 4,000 — 600 — 250 — ns

Start Set-up Time tSU.STA 4,700 — 600 — 250 — ns

Data In Hold Time tHD.DAT 0 — 0 — 0 — ns

Data In Set-up Time tSU.DAT 200 — 100 — 100 — ns

Inputs Rise Time(1)tR— 1,000 — 300 — 100 ns

Inputs Fall Time(1)tF— 300 — 300 — 100 ns

Stop Condition Set-up

Time

tSU.STO 4,700 — 600 — 250 — ns

Write-Protect Setup

Time

tSU.WP 4,000 — 600 — 250 — ns

Write-Protect Hold

Time

tHD.WP 4,000 — 600 — 250 — ns

Data Out Hold Time tDH 100 — 50 — 50 — ns

Write Cycle Time tWR — 10 — 10 — 10 ms

Note:

1. AC measurement conditions:

– CL: 100 pF

– RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz), 10 kΩ (100

kHz)

– Input pulse voltages: 0.3 x VCC to 0.7 x VCC

– Input rise and fall times: ≤50 ns

– Input and output timing reference voltages: 0.5 x VCC

2. These parameters are determined through product characterization and are not 100% tested in

production.

AT24CM02

Electrical Characteristics

Figure 4-1. Bus Timing

SCL

SDA In

SDA Out

tHIGH

tLOW

tDH

tAA tBUF

tSU.STO

tSU.DAT

tHD.DAT

tHD.STA

tSU.STA

4.5 Electrical Specifications

4.5.1 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT24CM02 should monotonically rise from GND to

the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.

4.5.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up

sequence, the AT24CM02 includes a Power-on Reset (POR) circuit. Upon power-up, the device will not

respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the

device out of Reset and into Standby mode.

The system designer must ensure the instructions are not sent to the device until the VCC supply has

reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is

greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the

first command to the device. See Table 4-4 for the values associated with these power-up parameters.

Table 4-4. Power-Up Conditions(1)

Symbol Parameter Min. Max. Units

tPUP Time required after VCC is stable before the device can accept commands 100 －µs

VPOR Power-on Reset Threshold Voltage －1.5 V

tPOFF Minimum time at VCC = 0V between power cycles 1 －ms

Note:

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the VCC level supplied to the AT24CM02 drops below the

maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by first

driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up

sequence in compliance with the requirements defined in this section.

AT24CM02

Electrical Characteristics

4.5.2 Pin Capacitance

Table 4-5. Pin Capacitance(1)

Symbol Test Condition Max. Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A2 and SCL) 6 pF VIN = 0V

Note:

1. This parameter is characterized but is not 100% tested in production.

4.5.3 EEPROM Cell Performance Characteristics

Table 4-6. EEPROM Cell Performance Characteristics

Operation Test Condition Min. Max. Units

Write Endurance(1)TA = 25°C, VCC(min.) < VCC < VCC(max.),

Byte(2) or Page Write mode

1,000,000 — Write Cycles

Data Retention(1)TA = 55°C 100 — Years

Note:

1. Performance is determined through characterization and the qualification process.

2. Due to the memory array architecture, the Write Cycle Endurance is specified for writes in groups

of 4 data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any

integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value

(i.e., 4*N+3). See Internal Writing Methodology for more details on this implementation.

AT24CM02

Electrical Characteristics

5. Device Operation and Communication

The AT24CM02 operates as a slave device and utilizes a simple I2C-compatible two-wire digital serial

interface to communicate with a host controller, commonly referred to as the bus master. The master

initiates and controls all read and write operations to the slave devices on the serial bus, and both the

master and the slave devices can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA).

The SCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used to

receive command and data information from the master as well as to send data back to the master.

Data is always latched into the AT24CM02 on the rising edge of SCL and always output from the device

on the falling edge of SCL. Both the SCL and SDA pins incorporate integrated spike suppression filters

and Schmitt Triggers to minimize the effects of input spikes and bus noise.

All command and data information is transferred with the Most Significant bit (MSb) first. During bus

communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have

been transferred, the receiving device must respond with either an Acknowledge (ACK) or a

No-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by

the master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no

unused clock cycles during any read or write operation, so there must not be any interruptions or breaks

in the data stream during each data byte transfer and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain

stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop

condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication

between the master and the slave devices. The number of data bytes transferred between a Start and a

Stop condition is not limited and is determined by the master. In order for the serial bus to be idle, both

the SCL and SDA pins must be in the logic high state at the same time.

5.1 Clock and Data Transition Requirements

The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor.

SCL is an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on

the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will

indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters with

respect to SCL and SDA for the AT24CM02 are shown in the timing waveform in Figure 4-1. The AC

timing characteristics and specifications are outlined in AC Characteristics.

5.2 Start and Stop Conditions

5.2.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a

stable logic ‘1’ state and will bring the device out of Standby mode. The master uses a Start condition to

initiate any data transfer sequence; therefore, every command must begin with a Start condition.

The device will continuously monitor the SDA and SCL pins for a Start condition but will not respond

unless one is detected. Refer to Figure 5-1 for more details.

5.2.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable

in the logic ‘1’ state.

AT24CM02

Device Operation and Communication

The master can use the Stop condition to end a data transfer sequence with the AT24CM02, which will

subsequently return to Standby mode. The master can also utilize a repeated Start condition instead of a

Stop condition to end the current data transfer if the master will perform another operation. Refer to

Figure 5-1 for more details.

5.3 Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it

has successfully received the data byte by responding with what is known as an Acknowledge (ACK).

An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the

eighth clock cycle followed by the receiving device responding with a logic ‘0’ during the entire high period

of the ninth clock cycle.

When the AT24CM02 is transmitting data to the master, the master can indicate that it is done receiving

data and wants to end the operation by sending a logic ‘1’ response to the AT24CM02 instead of an ACK

response during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished

by the master sending a logic ‘1’ during the ninth clock cycle, at which point the AT24CM02 will release

the SDA line so the master can then generate a Stop condition.

The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line

at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’

to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth

clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in

Figure 5-1 to better illustrate these requirements.

Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge

SCL

SDA

Must Be

Stable

SDA

Change

Allowed

SDA

Change

Allowed

Acknowledge

Valid

Stop

Condition

Start

Condition

1 2 8 9

SDA

Must Be

Stable Acknowledge Window

The transmitting device (Master or Slave)

must release the SDA line at this point to allow

the receiving device (Master or Slave) to drive the

SDA line low to ACK the previous 8-bit word.

The receiver (Master or Slave)

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

5.4 Standby Mode

The AT24CM02 features a low-power Standby mode that is enabled when any one of the following

occurs:

• A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).

• A Stop condition is received by the device unless it initiates an internal write cycle (see Write

Operations).

• At the completion of an internal write cycle (see Write Operations).

AT24CM02

Device Operation and Communication

5.5 Software Reset

After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset

by clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until

SDA is released by the EEPROM will vary. The software Reset sequence should not take more than nine

dummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to the

device by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.

Figure 5-2. Software Reset

SCL 9

Device is

8321

SDA

Dummy Clock Cycles

SDA Released

Software Reset

by EEPROM

In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must

be used to reset the device (see Power-Up Requirements and Reset Behavior).

AT24CM02

Device Operation and Communication

6. Memory Organization

The AT24CM02 is internally organized as 1,024 pages of 256 bytes each.

6.1 Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the

device for a read or write operation. Since multiple slave devices can reside on the serial bus, each slave

device must have its own unique address so the master can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The

device type identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see

Table 6‑1).

Following the 4-bit device type identifier is the hardware slave address bit, A2. This bit can be used to

expand the address space by allowing up to two Serial EEPROM devices on the same bus. The

hardware slave address bit must correlate with the voltage level on the corresponding hardwired device

address input pin A2. The A2 pin uses an internal proprietary circuit that automatically biases the pin to a

logic ‘0’ state if the pin is allowed to float. In order to operate in a wide variety of application

environments, the pull‑down mechanism is intentionally designed to be somewhat strong. Once the pin is

biased above the CMOS input buffer's trip point (~0.5 x VCC), the pull‑down mechanism disengages.

Microchip recommends connecting the A2 pin to a known state whenever possible.

Following the A2 hardware slave address bit are A17 and A16 (bit 2 and bit 1 of the device address byte),

which are the Most Significant bits of the memory array word address. Refer to Table 6‑1 to review the bit

position.

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CM02 will return an ACK. If a valid

comparison is not made, the device will NACK.

Table 6-1. Device Addressing

Package Device Type Identifier Hardware Slave

Address Bit

Most Significant Bits

of the Word Address

R/W Select

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SOIC,WLCSP 1010 A2A17 A16 R/W

For all operations except the current address read, two 8‑bit word address bytes must be transmitted to

the device immediately following the device address byte. The word address bytes contain the lower 16

significant memory array address bits, and are used to specify which byte location in the EEPROM to

start reading or writing. See Table 6-2 and Table 6-3 to review their bit positions.

Table 6-2. First Word Address Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A15 A14 A13 A12 A11 A10 A9 A8

AT24CM02

Memory Organization

Table 6-3. Second Word Address Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A7 A6 A5 A4 A3 A2 A1 A0

AT24CM02

Memory Organization

7. Write Operations

All write operations for the AT24CM02 begin with the master sending a Start condition, followed by a

device address byte with the R/W bit set to logic ‘0’, and then by the word address bytes. The data

value(s) to be written to the device immediately follow the word address bytes.

7.1 Byte Write

The AT24CM02 supports the writing of a single 8-bit byte. Selecting a data word in the AT24CM02

requires 18-bit word address.

Upon receipt of the proper device address and the word address bytes, the EEPROM will send an

Acknowledge. The device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit

data word, the EEPROM will respond with an ACK. The addressing device, such as a bus master, must

then terminate the write operation with a Stop condition. At that time, the EEPROM will enter an internally

self-timed write cycle, which will be completed within tWR, while the data word is being programmed into

the nonvolatile EEPROM. All inputs are disabled during this write cycle, and the EEPROM will not

respond until the write is complete.

Figure 7-1. Byte Write

SCL

SDA

Start Condition

by Master

Device Address Byte First Word Address Byte

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A2

A17 A16 0 0

Second Word Address Byte Data Word

Stop Condition

by Master

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 0

A14 A13 A12 A11 A10 A9 A8 0

ACK

from Slave

ACK

from Slave

ACK

from Slave

ACK

from Slave

A7 A6 A5 A4 A3 A2 A1 A0 0

A15

7.2 Page Write

A page write operation allows up to 256 bytes to be written in the same write cycle, provided all bytes are

in the same row of the memory array (where address bits A17 through A8 are the same). Partial page

writes of less than 256 bytes are also allowed.

A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition

after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data

word, the bus master can transmit up to 255 additional data words. The EEPROM will respond with an

ACK after each data word is received. Once all data to be written has been sent to the device, the bus

master must issue a Stop condition (see Figure 7-2) at which time the internally self-timed write cycle will

begin.

The lower eight bits of the word address are internally incremented following the receipt of each data

word. The higher order address bits are not incremented and retain the memory page row location. Page

AT24CM02

Write Operations

write operations are limited to writing bytes within a single physical page, regardless of the number of

bytes actually being written. When the incremented word address reaches the page boundary, the

address counter will rollover to the beginning of the same page. Nevertheless, creating a rollover event

should be avoided as previously loaded data in the page could become unintentionally altered.

Figure 7-2. Page Write

SCL

SDA

Start Condition

by Master ACK

from Slave

ACK

from Slave

Device Address Byte First Word Address Byte

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A2

A17 A16 0 0 A15 A14 A13 A12 A11 A10 A9 A8 0

ACK

from Slave

ACK

from Slave

Stop Condition

by Master

ACK

from Slave

Second Word Address Byte Data Word (n) Data Word (n+x), max of 256 without rollover

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0

MSB MSB MSB

7.3 Internal Writing Methodology

The AT24CM02 incorporates a built-in error detection and correction (EDC) logic scheme. The EEPROM

array is internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error

Correction Code) bits of EEPROM. These 38 bits are referred to as the internal physical data word.

During a read sequence, the EDC logic compares each 4-byte physical data word with its corresponding

six ECC bits. If a single bit out of the 4-byte region reads incorrectly, the EDC logic will detect the bad bit

and replace it with a correct value before the data is serially clocked out. This architecture significantly

improves the reliability of the AT24CM02 compared to an implementation that does not utilize EDC.

It is important to note that data is always physically written to the part at the internal physical data word

level, regardless of the number of bytes written. Writing single bytes is still possible with the Byte Write

operation, but internally, the other three bytes within that 4-byte location where the single byte was

written, along with the six ECC bits will be updated. Due to this architecture, the AT24CM02 EEPROM

write endurance is rated at the internal physical data word level (4-byte word). The system designer

needs to optimize the application writing algorithms to observe these internal word boundaries in order to

reach the endurance rating.

7.4 Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would

prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know

immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be

started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated.

This involves repeatedly sending a Start condition followed by a valid device address byte with the R/W

bit set at logic ‘0’. The device will not respond with an ACK while the write cycle is ongoing. Once the

internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or write

AT24CM02

Write Operations

operation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustrate

this technique.

Figure 7-3. Acknowledge Polling Flowchart

Did

the device

ACK?

Send any

Write

protocol.

Send

Stop

condition

to initiate the

Write cycle.

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0.

Proceed to

next Read or

Write operation.

YES

7.5 Write Cycle Timing

The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that

begins the internal write cycle to the Start condition of the first device address byte sent to the AT24CM02

that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement.

During the internally self-timed write cycle, any attempts to read from or write to the memory array will not

be processed.

Figure 7-4. Write Cycle Timing

tWR

Stop

Condition

Start

Condition

Data Word n

ACKD0

SDA

Stop

Condition

SCL 8 9

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum tWR

can only be determined through

the use of an ACK Polling routine.

7.6 Write Protection

The AT24CM02 utilizes a hardware data protection scheme that allows the user to write‑protect the entire

memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin

is at GND or left floating.

Table 7-1. AT24CM02 Write-Protect Behavior

WP Pin Voltage Part of the Array Protected

VCC Full Array

GND None － Write Protection Not Enabled

AT24CM02

Write Operations

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation

prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition

has been sent will not alter or interrupt the execution of the write cycle. The WP pin state must be valid

with respect to the associated setup (tSU.WP) and hold (tHD.WP) timing as shown in Figure 7-5 below.

The WP setup time is the amount of time that the WP state must be stable before the Stop condition is

issued. The WP hold time is the amount of time after the Stop condition that the WP must remain stable

(see Table 4-3, AC Characteristics,” for timing specs for tHD.WP and tSU.WP).

If an attempt is made to write to the device while the WP pin has been asserted, the device will

acknowledge the device address, word address and data bytes, but no write cycle will occur when the

Stop condition is issued. The device will immediately be ready to accept a new read or write command.

Figure 7-5. Write-Protect Setup and Hold Timing

AT24CM02

Write Operations

8. Read Operations

Read operations are initiated the same way as write operations with the exception that the Read/Write

Select bit in the device address byte must be a logic ‘1’. There are three read operations:

• Current Address Read

• Random Address Read

• Sequential Read

8.1 Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write

operation, incremented by one. This address stays valid between operations as long as the VCC is

maintained to the part. The address roll-over during a read is from the last byte of the last page to the first

byte of the first page of the memory.

A current address read operation will output data according to the location of the internal data word

address counter. This is initiated with a Start condition, followed by a valid device address byte with the

R/W bit set to logic ‘1’. The device will ACK this sequence and the current address data word is serially

clocked out on the SDA line. All types of read operations will be terminated if the bus master does not

respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may

send a Stop condition to complete the protocol, or it can send a Start condition to begin the next

sequence.

Figure 8-1. Current Address Read

SCL

SDA

Device Address Byte Data Word (n)

Start Condition

by Master ACK

from Slave

NACK

from Master

Stop Condition

by Master

MSB MSB

1 0 1 0 A2 X X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

8.2 Random Read

A random read begins in the same way as a byte write operation does to load in a new data word

address. This is known as a “dummy write” sequence; however, the data byte and the Stop condition of

the byte write must be omitted to prevent the part from entering an internal write cycle. Once the device

address and word address are clocked in and acknowledged by the EEPROM, the bus master must

generate another Start condition. The bus master now initiates a current address read by sending a Start

condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The EEPROM will ACK

the device address and serially clock out the data word on the SDA line. All types of read operations will

be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle.

After the NACK response, the master may send a Stop condition to complete the protocol, or it can send

a Start condition to begin the next sequence.

AT24CM02

Read Operations

Figure 8-2. Random Read

SCL

SDA

Start Condition

by Master

Device Address Byte First Word Address Byte

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A2

A17 A16 0 0

Dummy Write

Start Condition

by Master

Device Address Byte Data Word (n)

Stop Condition

by Master

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A2 XX 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1

A14 A13 A12 A11 A10 A9 A8 0

ACK

from Slave

ACK

from Slave

ACK

from Slave

NACK

from Master

Second Word Address Byte

MSB

A7 A6 A5 A4 A3 A2 A1 A0 0

ACK

from Slave

A15

8.3 Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus master

receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will

continue to increment the word address and serially clock out sequential data words. When the maximum

memory address is reached, the data word address will roll-over and the sequential read will continue

from the beginning of the memory array. All types of read operations will be terminated if the bus master

does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the

master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the

next sequence.

Figure 8-3. Sequential Read

SCL

SDA

Start

Master

ACK

from

Slave

ACK

from

Master

Device Address Byte Data Word (n)

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A2 X X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0

ACK

from

Master

NACK

from

Master

Stop

Master

ACK

from

Master

Data Word (n+1) Data Word (n+2) Data Word (n+x)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1

MSB MSB MSB

AT24CM02

Read Operations

9. Device Default Condition from Microchip

The AT24CM02 is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.

AT24CM02

Device Default Condition from Microchip

10. Packaging Information

10.1 Package Marking Information

Catalog Number Truncation

AT24CM02 Truncation Code ##: 2H

YYWWNNN

## % CO

ATMLHYWW

8-lead SOIC

Note 2: Package drawings are not to scale

Note 1: designates pin 1

8-ball WLCSP

Thin and Standard Thickness Options

## % CO

ATMLUYWW

YYWWNNN

Date Codes Voltages

YY = Year WW = Work Week of Assembly % = Minimum Voltage

15: 2015 19: 2019 02: Week 2 M: 1.7V min

16: 2016 20: 2020 04: Week 4 D: 2.5V min

17: 2017 21: 2021 ...

18: 2018 22: 2022 52: Week 52

Country of Origin Device Grade Atmel Truncation

CO = Country of Origin H or U: Industrial Grade ATML: Atmel

Lot Number or Trace Code

NNN = Alphanumeric Trace Code (2 Characters for small packages)

AT24CM02: Package Marking Information

AT24CM02

Packaging Information

0.25 CA–B D

SEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10 C

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

NOTE 5

NX b

0.10 CA–B

H0.23

(L1)

R0.13

VIEW C

SEE VIEW C

NOTE 1

AT24CM02

Packaging Information

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Foot Angle 0° - 8°

15°-5°

Mold Draft Angle Bottom

15°-5°

Mold Draft Angle Top

0.51-0.31

Lead Width

0.25-0.17

Lead Thickness

1.27-0.40LFoot Length

0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10

Standoff

--1.25A2Molded Package Thickness

1.75--AOverall Height

1.27 BSC

Pitch

8NNumber of Pins

MAXNOMMINDimension Limits

MILLIMETERSUnits

protrusions shall not exceed 0.15mm per side.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

4. Dimensioning and tolerancing per ASME Y14.5M

Notes:

Footprint L1 1.04 REF

5. Datums A & B to be determined at Datum H.

AT24CM02

Packaging Information

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-SN Rev B

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Dimension Limits

Units

CContact Pad Spacing

Contact Pitch

MILLIMETERS

1.27 BSC

MIN

MAX

5.40

Contact Pad Length (X8)

Contact Pad Width (X8)

1.55

0.60

NOM

SILK SCREEN

AT24CM02

Packaging Information

DRAWING NO. REV. TITLE GPC

8U-11 E

8/7/15

8U-11, 8-ball 4x4 Array, Custom Pitch

Wafer Level Chip Scale Package (WLCSP) with BSC GEN

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN TYP MAX NOTE

A 0.313 0.334 0.355

A1 — 0.094 —

A2 — 0.240 — 3

D Contact Microchip for details

d1 1.00 BSC

d2 1.40 BSC

E Contact Microchip for details

e 0.50 BSC

e1 2.10 BSC

b 0.170 0.185 0.200

NC = Not Connected

PIN ASSIGNMENT MATRIX

1 2 3

n/a

SCL

n/a

VCC

n/a

SDA

n/a

GND

n/a

BOTTOM SIDE

TOP VIEW

SIDE VIEW

k0.20 C

vd0.015 C

0.05 C A B

Note: 1. Dimensions are NOT to scale.

2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.

3. Product offered with Back Side Coating.

4 3 2 1

Dd1

SEATING PLANE

1 2 3 4

A1 CORNER

k0.015 (4X)

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

AT24CM02

Packaging Information

DRAWING NO. REV. TITLE GPC

8U-18 01

4/5/16

8U-18, 8-ball 4x4 Array, Custom Pitch

Wafer Level Chip Scale Package (WLCSP) GQA

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN TYP MAX NOTE

A 0.456 0.495 0.534

A1 — 0.190 —

A2 — 0.305 —

D Contact Microchip for details.

d1 1.00 BSC

d2 1.40 BSC

E Contact Microchip for details.

e 0.50 BSC

e1 2.10 BSC

b — 0.270 —

NC = Not Connected

PIN ASSIGNMENT MATRIX

1 2 3

n/a

SCL

n/a

VCC

n/a

SDA

n/a

GND

n/a

SIDE VIEW

Note: 1. Dimensions are NOT to scale.

2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.

4 3 2 1

Dd1

-C-

SEATING PLANE

1 2 3 4

k0.20 C

BOTTOM SIDE

0.015 (4X)

TOP VIEW

vd0.015 C

0.05 C A B

A1 CORNER A1 CORNER

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

AT24CM02

Packaging Information

11. APPENDIX A: Revision History

Doc Rev. Date Comments

A 05/2019 Updated to Microchip template. Microchip DS20006197 replaces Atmel document

8812. Corrected tLOW typo from 400 ns to 500 ns. Corrected tAA typo from 550 ns to

450 ns. Updated Part Marking Information. Updated the “Software Reset” section.

Added ESD rating. Removed lead finish designation. Update trace code format in

package markings. Updated section content throughout for clarification. Updated

SOIC package drawing to Microchip format.

E 01/2017 Atmel Document 8828 - Updated Power-on Requirements and Reset Behavior

section.

D 05/2016 Atmel Document 8828 - Added the 8U-18 standard thickness WLCSP package

option. Updated the “Clock and Data Transition Requirements” section and the “DC

Characteristics” table.

C 11/2015 Atmel Document 8828 - Corrected 8-ball WLCSP pinout.

B 08/2015 Atmel Document 8828 - Updated the 8U-11 package drawing, data retention

discrepancy, and 8-ball pinout.

A 05/2015 Atmel Document 8828 - Initial document release.

AT24CM02

APPENDIX A: Revision History

The Microchip Website

Microchip provides online support via our website at http://www.microchip.com/. This website is used to

make files and information easily available to customers. Some of the content available includes:

•Product Support – Data sheets and errata, application notes and sample programs, design

resources, user’s guides and hardware support documents, latest software releases and archived

software

•General Technical Support – Frequently Asked Questions (FAQs), technical support requests,

online discussion groups, Microchip design partner program member listing

•Business of Microchip – Product selector and ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Microchip sales offices, distributors and factory

representatives

Product Change Notification Service

Microchip’s product change notification service helps keep customers current on Microchip products.

Subscribers will receive email notification whenever there are changes, updates, revisions or errata

related to a specified product family or development tool of interest.

To register, go to http://www.microchip.com/pcn and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Embedded Solutions Engineer (ESE)

• Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also

available to help customers. A listing of sales offices and locations is included in this document.

Technical support is available through the web site at: http://www.microchip.com/support

AT24CM02

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Product Family

24C = Standard I2C-compatible

Serial EEPROM

Device Density

Shipping Carrier Option

Device Grade or

Wafer/Die Thickness

Package Option

M = Megabit Family

02 = 2 Megabit

B = Bulk (Tubes)

T = Tape and Reel, Standard Quantity Option

E = Tape and Reel, Extended Quantity Option

Operating Voltage

D = 2.5V to 5.5V

M = 1.7V to 5.5V

H or U = Industrial Temperature Range

(-40°C to +85°C)

11 = 11mil Wafer Thickness

SS = SOIC

U1 = thin height WLCSP

U2 = standard height WLCSP

WWU = Wafer Unsawn

A T 24CM02-SSHD-B

Examples

Device Package Package

Drawing

Code

Package

Option

Voltage Shipping

Carrier

Option

Device Grade

AT24CM02‑SSHM‑B SOIC SN SS 1.7V to

5.5V

Bulk (Tubes) Industrial

Temperature

(-40°C to 85°C)

AT24CM02‑SSHM‑T SOIC SN SS 1.7V to

5.5V

Tape and

Reel

AT24CM02‑SSHD‑B SOIC SN SS 2.5V to

5.5V

Bulk (Tubes)

AT24CM02‑SSHD‑T SOIC SN SS 2.5V to

5.5V

Tape and

Reel

AT24CM02‑U1UM0B‑T

(1)(2)

WLCSP 8U-11 U1 1.7V to

5.5V

Tape and

Reel

AT24CM02‑U2UM‑T(2) WLCSP 8U-18 U2 1.7V to

5.5V

Tape and

Reel

Note:

1. This device includes a backside coating to increase product robustness.

2. CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in EEPROM cells.

Therefore, customers who use a WLCSP package or the product at a die level must ensure that

exposure to ultraviolet light does not occur.

AT24CM02

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the

operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is

engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their

code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the

code protection features of our products. Attempts to break Microchip’s code protection feature may be a

violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software

or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for

your convenience and may be superseded by updates. It is your responsibility to ensure that your

application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS

CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life

support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting

from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks,

BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,

HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB,

megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC,

picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC,

SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR,

UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed

Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge,

ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium,

TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

AT24CM02

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky,

BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,

Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient

Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,

Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered

trademarks of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-4582-1

AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex,

DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,

Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile

are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit http://

www.microchip.com/quality.

AT24CM02

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Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Novi, MI

Tel: 248-848-4000

Houston, TX

Tel: 281-894-5983

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

China - Nanjing

Tel: 86-25-8473-2460

China - Qingdao

Tel: 86-532-8502-7355

China - Shanghai

Tel: 86-21-3326-8000

China - Shenyang

Tel: 86-24-2334-2829

China - Shenzhen

Tel: 86-755-8864-2200

China - Suzhou

Tel: 86-186-6233-1526

China - Wuhan

Tel: 86-27-5980-5300

China - Xian

Tel: 86-29-8833-7252

China - Xiamen

Tel: 86-592-2388138

China - Zhuhai

Tel: 86-756-3210040

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Tel: 91-20-4121-0141

Japan - Osaka

Tel: 81-6-6152-7160

Japan - Tokyo

Tel: 81-3-6880- 3770

Korea - Daegu

Tel: 82-53-744-4301

Korea - Seoul

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

Tel: 60-4-227-8870

Philippines - Manila

Tel: 63-2-634-9065

Singapore

Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Finland - Espoo

Tel: 358-9-4520-820

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Germany - Haan

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-72400

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Tel: 972-9-744-7705

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

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