©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
File Number
3975.2
RFF60P06
25A†, 60V, 0.030 Ohm, P-Channel Power
MOSFET
The RFF60P06 P-Channel power MOSFET is manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Reliability screening is available as either commercial or
TX/TXV equivalent of MIL-S-19500. Contact Intersil
Corporation High-Reliability Marketing group for any desired
deviations from the data sheet.
Formerly developmental type TA09835.
Commercial Version: RFG60P06E.
† Current is limited by the package capability.
Features
• 25A, 60V
•r
DS(ON)
= 0.030
Ω
• Temperature Compensating PSPICE
®
Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
•150
o
C Operating Temperature
• Reliability Screened
Symbol
Packaging
JEDEC TO-254AA
CAUTION: Berylia Warning per MIL-S-19500.
Refer to package specifications.
Ordering Information
PART NUMBER PACKAGE BRAND
RFF60P06 TO-254AA RFF60P06
NOTE: When ordering, use the entire part number.
D
G
S
GATE
SOURCE
DRAIN
PACKAGE TAB
(ISOLATED)
Data Sheet September 1998
T
itle
F
F6
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er-
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,
-
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f
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k
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©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFF60P06 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
-60 V
Drain to Gate Voltage (RGS = 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
-60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
25 (Note 5)
Refer to Peak Current Curve
A
Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
1.0
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
260
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V -60 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A -2.0 -3.0 -4.5 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
,V
GS
= 0V - - -25
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 125
o
C - - -250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V, T
C
= 125
o
C--
±
100
µ
A
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 25A, V
GS
= -10V, (Figure 9) - - 0.030
Ω
Turn-On Time t
ON
V
DD
= -30V, I
D
= 25A, R
L
= 1.2
Ω
, V
GS
= -10V
R
G
= 2.35
Ω
(Figures 13, 16, 17)
--195ns
Turn-On Delay Time t
d(ON)
-2570 ns
Rise Time t
r
- 50 125 ns
Turn-Off Delay Time t
d(OFF)
- 80 200 ns
Fall Time t
f
-3075 ns
Turn-Off Time t
OFF
--275ns
Total Gate Charge Q
g(TOT)
V
GS
= 0 to -20V V
DD
= -30V, I
D
= 25A,
R
L
= 1.2
Ω
I
G(REF)
= -4.2mA
(Figures 18, 19)
--450nC
Gate Charge at -10V Q
g(-10)
V
GS
= 0 to -10V - - 225 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0 to -2V - - 15 nC
Input Capacitance C
ISS
V
DS
= -25V, V
GS
= 0V
f = 1MHz
- 7200 - pF
Output Capacitance C
OSS
- 1800 - pF
Reverse Transfer Capacitance C
RSS
-400 - pF
Thermal Resistance Junction to Case R
θ
JC
- - 1.0
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
--48
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V
SD
I
SD
= -25A - -1.1 -1.5 V
Diode Reverse Recovery Time t
rr
I
SD
= -25A, dI
SD
/dt = -100A/
µ
s - 130 200 ns
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3)
4. Current is limited by package capability.
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
POWER DISSIPATION MULTIPLIER
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
150
100755025
-10
0
-20
-30
-5
-15
-25
125
ID, DRAIN CURRENT (A)
2
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
t, RECTANGULAR PULSE DURATION (s)
THERMAL IMPEDANCE
ZθJC, NORMALIZED
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
-500
-100
-10
-10 -100
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
VDSS MAX = -60V
ID, DRAIN CURRENT (A)
10ms
100µs
1ms
-1
-1
100ms
DC
TC = 25oC
TJ = MAX RATED
10-5 10-4 10-3 10-2 10-1 100101
-102
-103
t, PULSE WIDTH (s)
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION VGS = -10V
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
II
25
150 TC
–
125
---------------------



=
-101TC = 25oC
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
-100
-75
-10 0.1 1 10 100
tAV , TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
If R = 0
If R ≠ 0
-200
00 -2 -4 -6 -8 -10
VGS = -5V
VGS = -6V
VGS = -8V VGS = -7V
VGS = -10V
-25
-50
-75
-150
VGS = -4.5V
VGS = -20V
-100
-125
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 250µs
TC = 25oC
0 -2 -4 -6 -8 -10
VGS, GATE TO SOURCE VOLTAGE (V)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
0
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
-55oC
150oC
25oC
-25
-50
-100
-75
-125
-150 VDD = -15V
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80
TJ, JUNCTION TEMPERATURE (oC)
120 160
2.5
NORMALIZED DRAIN TO SOURCE
PULSE DURATION = 250µs, VGS = -10V, ID = 25A
ON RESISTANCE
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 160120
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
NORMALIZED GATE
VGS = VDS, ID = 250µA2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuit and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
CISS
COSS
CRSS
6000
4000
2000
0
0-5 -10 -15 -20 -25
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
8000
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
-60
-45
-30
-15
0
-10
-7.5
-5.0
-2.5
0
20
IG(REF)
IG(ACT)
80
IG(REF)
IG(ACT)
t, TIME (µs)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = BVDSS VDD = BVDSS
RL = 1.0Ω
IG(REF) = 4.2mA
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
VGS = -10V
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuit and Waveforms (Continued)
RL
VGS
+
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = -2V
Qg(-10)
VGS = -10V
Qg(TOT)
VGS = -20V
VDS
-VGS
IG(REF)
0
0
Data Packages - Intersil Power Transistors
TX and TXV Equivalents
1. TX/TXV Equivalent - Standard Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet
2. TX/TXV Equivalent - Optional Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
- Precondition Lot Traveler
- Pre and Post Burn-In Read and Record Data
D. Group A - Attributes Data Sheet
- Group A Lot Traveler
E. Group B - Attributes Data Sheet
- Group B Lot Traveler
- Pre and Post Read and Record Data for Intermittent
Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating Life
Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Group C Lot Traveler
- Pre and Post Read and Record Data for Intermittent
Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
PSPICE Electrical Model
.SUBCKT RFF60P06 2 1 3 REV 9/20/94
CA 12 8 1.01e-8
CB 15 14 1.05e-8
CIN 6 8 6.9e-9
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 5 11 17 18 -76.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 8 6 1
EVTO 20 6 8 18 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 7.9e-9
LSOURCE 3 7 4.18e-9
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 12.83e-3
RGATE 9 20 1.55
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.25e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.83
.MODEL DBDMOD D (IS=1.24e-12 RS=4.72e-3 TRS1=1.43e-3 TRS2=-4.91e-7 CJO=6.98e-9 TT=1.5e-7)
.MODEL DBKMOD D (RS=1.11e-1 TRS1=1.34e-3 TRS2=4.46e-12)
.MODEL DPLCAPMOD D (CJO=15e-10 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.71 KP=31.5 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=9.42e-4 TC2=0)
.MODEL RDSMOD RES (TC1=5.85e-3 TC2=7.69e-6)
.MODEL RVTOMOD RES (TC1=-3.39e-3 TC2=1.07e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.6 VOFF=2.6)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.6 VOFF=4.6)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.16 VOFF=-3.84)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.84 VOFF=1.16)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
MOS1
10
DPLCAP RDRAIN
DBREAK
LDRAIN
DRAIN
LSOURCE
DBODY
RBREAK
RVTO
VBAT
+
-
19
IT
RSOURCE
EBREAK
MOS2
EDSEGS
RIN CIN
VTO
ESG
S1A S2A
S2BS1B
CBCA
EVTO
RGATE
GATE
LGATE
5
2
1817
7
11
21
8
6
16
2091
12 15
14
13
13
8
14
13
6
8
5
8
18
8
6
817
18
+
-
+
-
+
-
+
-
+
-
+
-
3
RFF60P06
©2001 Fairchild Semiconductor Corporation RFF60P06 Rev. A
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTX/JANTXV Equivalent)
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current IGSS VGS = ±20V, TC = 25oC±20 (Note 4) nA
Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value, TC = 25oC±25 (Note 4) µA
On Resistance rDS(ON) TC = 125oC at Rated ID±20% (Note 5) Ω
Gate Threshold Voltage VGS(TH) ID = 1.0mA, TC = 25oC±20% (Note 5) V
NOTES:
5. Or 100% of Initial Reading (whichever is greater).
6. Of Initial Reading.
Screening Information
TEST JANTX/JANTXV EQUIVALENT
Gate Stress VGS = -30V, t = 250µs
Pind Optional
PDA 10%
Pre Burn-In Test (Note 1) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 168 hours
Final Electrical Tests (Note 6) MIL-S-19500, Group A, Subgroup 2
NOTE:
7. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = -48V, t = 10ms 8.0 A
Unclamped Inductive Switching IAS VGS(PEAK) = -15V, L = 0.1mH 75 A
Thermal Response ∆VSD tH = 100ms; VH = 25V, IH = 4A 142 mV
Thermal Impedance ∆VSD tH = 500ms; VH = 25V, IH = 4A 182 mV
RFF60P06
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAST
FASTr™
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GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
Rev. H
ACEx™
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CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
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F ACT Quiet Series™
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SuperSOT™-6
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SyncFET™
TinyLogic™
UHC™
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VCX™